commit 402735b8934bb99b00aef1a73312d2287ada5cf5
author Tien Fong Chee <tien.fong.chee@intel.com> Tue Dec 05 15:58:02 2017 +0800
committer Marek Vasut <marex@denx.de> Fri May 18 10:30:47 2018 +0200
tree 40e5da58a958f474b55e9fc7d40a3f88159bf819
parent 3710de7362263a544ebc5ae6f8fc933464136b89

ARM: socfpga: Add DDR driver for Arria 10

Add DDR driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

arch/arm/mach-socfpga/include/mach/sdram_arria10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
index 8ae8d1b..25b82fb 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -7,6 +7,7 @@
 #define _SOCFPGA_SDRAM_ARRIA10_H_
 
 #ifndef __ASSEMBLY__
+int ddr_calibration_sequence(void);
 
 struct socfpga_ecc_hmc {
 	u32 ip_rev_id;
@@ -203,6 +204,7 @@
 	u32 niosreserve1;
 	u32 niosreserve2;
 };
+
 #endif /*__ASSEMBLY__*/
 
 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK		0x1F000000