commit 3fb5b2f9789e722649c59f3825ed3a6c6f603165
author Tom Rini <trini@konsulko.com> Wed Mar 30 18:07:23 2022 -0400
committer Tom Rini <trini@konsulko.com> Fri Apr 08 10:46:22 2022 -0400
tree d9c1f95b2ba4e6b44b917431a764afcced7fe72b
parent ca57d3b622c4bc8f9a86b916f3ca3ce186f579e1

spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig

This is a little tricky since SoCFPGA has code to determine this as
runtime.  Introduce a guard variable for platforms to select if they
have a static value to use.  Then for ARCH_SOCFPGA, call
cm_get_qspi_controller_clk_hz() and otherwise continue the previous
behavior.

Cc: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

configs/j721e_hs_evm_r5_defconfig

diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig
index 1e4a93f..aaf3c2b 100644
--- a/configs/j721e_hs_evm_r5_defconfig
+++ b/configs/j721e_hs_evm_r5_defconfig
@@ -114,6 +114,8 @@
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y