diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
index 42114a5..ab08727 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -138,7 +138,6 @@
 #define DDR3_MR2_TWL(n) \
 	(((n - 5) & 0x7) << 3)
 
-
 #ifdef CONFIG_TPL_BUILD
 
 static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
@@ -524,7 +523,6 @@
 	pctl_timing->tckesr = pctl_timing->tcke + 1;  /* JESD-79: tCKE + 1tCK */
 	pctl_timing->tdpd = 0;    /* RK3368 TRM: "allowed values for DDR3: 0" */
 
-
 	/*
 	 * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
 	 * We want to use the smallest multiplier that satisfies the tFAW
@@ -987,7 +985,6 @@
 	.get_info = rk3368_dmc_get_info,
 };
 
-
 static const struct udevice_id rk3368_dmc_ids[] = {
 	{ .compatible = "rockchip,rk3368-dmc" },
 	{ }
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 10dc05d..954995c 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -333,7 +333,6 @@
 			return -EINVAL;
 		}
 
-
 		params->bank_params[bank].sdram_timing =
 			(struct stm32_sdram_timing *)
 			 ofnode_read_u8_array_ptr(bank_node,
@@ -346,7 +345,6 @@
 			return -EINVAL;
 		}
 
-
 		bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
 						"st,sdram-refcount", 8196);
 		bank++;
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c
index d7834b3..0e37ea9 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
@@ -707,7 +707,6 @@
 		break;
 	}
 
-
 	if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
 		ret = board_ddr_power_init(STM32MP_DDR3);
 	else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) {