| // SPDX-License-Identifier: GPL-2.0+ |
| * dts file for Xilinx ZynqMP Mini Configuration |
| * (C) Copyright 2018, Xilinx, Inc. |
| * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> |
| model = "ZynqMP MINI EMMC1"; |
| compatible = "xlnx,zynqmp"; |
| stdout-path = "serial0:115200n8"; |
| reg = <0x0 0x0 0x0 0x20000000>; |
| compatible = "fixed-clock"; |
| clock-frequency = <200000000>; |
| compatible = "simple-bus"; |
| compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; |
| reg = <0x0 0xff170000 0x0 0x1000>; |
| clock-names = "clk_xin", "clk_ahb"; |
| clocks = <&clk_xin &clk_xin>; |