diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c
index 4f23012..94651dc 100644
--- a/cpu/mpc8260/cpu.c
+++ b/cpu/mpc8260/cpu.c
@@ -49,6 +49,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_GET_CPU_STR_F)
+extern int get_cpu_str_f (char *buf);
+#endif
+
 int checkcpu (void)
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
@@ -81,7 +85,12 @@
 	if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
 		return -1;	/* whoops! someone moved the IMMR */
 
+#if defined(CONFIG_GET_CPU_STR_F)
+	get_cpu_str_f (buf);
+	printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
+#else
 	printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
+#endif
 
 	/*
 	 * the bottom 16 bits of the immr are the Part Number and Mask Number
diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c
index 640026b..7dcc949 100644
--- a/cpu/mpc8260/cpu_init.c
+++ b/cpu/mpc8260/cpu_init.c
@@ -28,6 +28,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+extern unsigned long board_get_cpu_clk_f (void);
+#endif
+
 static void config_8260_ioports (volatile immap_t * immr)
 {
 	int portnum;
@@ -90,6 +94,7 @@
 	}
 }
 
+#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
 /*
  * Breath some life into the CPU...
  *
@@ -102,6 +107,9 @@
 #if !defined(CONFIG_COGENT)		/* done in start.S for the cogent */
 	uint sccr;
 #endif
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+	unsigned long cpu_clk;
+#endif
 	volatile memctl8260_t *memctl = &immr->im_memctl;
 	extern void m8260_cpm_reset (void);
 
@@ -119,10 +127,27 @@
 	immr->im_clkrst.car_rmr = CFG_RMR;
 
 	/* BCR - Bus Configuration Register (4-25) */
+#if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE)
+	if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
+		immr->im_siu_conf.sc_bcr = CFG_BCR_60x;
+	} else {
+		immr->im_siu_conf.sc_bcr = CFG_BCR_SINGLE;
+	}
+#else
 	immr->im_siu_conf.sc_bcr = CFG_BCR;
+#endif
 
 	/* SIUMCR - contains debug pin configuration (4-31) */
+#if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH)
+	cpu_clk = board_get_cpu_clk_f ();
+	if (cpu_clk >= 100000000) {
+		immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_HIGH;
+	} else {
+		immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_LOW;
+	}
+#else
 	immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
+#endif
 
 	config_8260_ioports (immr);
 
@@ -157,7 +182,8 @@
 #endif
 
 	/* now restrict to preliminary range */
-	memctl->memc_br0 = CFG_BR0_PRELIM;
+	/* the PS came from the HRCW, don´t change it */
+	memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK);
 	memctl->memc_or0 = CFG_OR0_PRELIM;
 
 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index b14fc15..1edd6fb 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -274,7 +274,23 @@
 				  | SIUMCR_CS10PC00
 				  | SIUMCR_BCTLC00
 				  | SIUMCR_MMR11;
-
+#elif defined(CONFIG_TQM8272)
+#if 0
+	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+						~SIUMCR_LBPC11 &
+						~SIUMCR_CS10PC11 &
+						~SIUMCR_LBPC11) |
+					SIUMCR_LBPC01 |
+					SIUMCR_CS10PC01 |
+					SIUMCR_APPC10;
+#else
+#if 0
+	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr |
+					SIUMCR_APPC10);
+#else
+	immap->im_siu_conf.sc_siumcr = 0x88000000;
+#endif
+#endif
 #else
 	/*
 	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
@@ -288,6 +304,7 @@
 					SIUMCR_CS10PC01 |
 					SIUMCR_APPC10;
 #endif
+printf("%s siumcr: %x\n", __FUNCTION__, immap->im_siu_conf.sc_siumcr);
 
 	/* Make PCI lowest priority */
 	/* Each 4 bits is a device bus request	and the MS 4bits
diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c
index 360404f..38cd0d9 100644
--- a/cpu/mpc8260/speed.c
+++ b/cpu/mpc8260/speed.c
@@ -25,6 +25,10 @@
 #include <mpc8260.h>
 #include <asm/processor.h>
 
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+extern unsigned long board_get_cpu_clk_f (void);
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /* ------------------------------------------------------------------------- */
@@ -112,8 +116,12 @@
 #if !defined(CONFIG_8260_CLKIN)
 #error clock measuring not implemented yet - define CONFIG_8260_CLKIN
 #else
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+	clkin = board_get_cpu_clk_f ();
+#else
 	clkin = CONFIG_8260_CLKIN;
 #endif
+#endif
 
 	sccr = immap->im_clkrst.car_sccr;
 	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index 3521731..b198ff4 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -156,7 +156,7 @@
 	out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
 }
 
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 	int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
 	ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
@@ -188,6 +188,7 @@
 	 */
 	board_nand_select_device(nand, cs);
 	out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222);
+	return 0;
 }
 
 #endif