armv8: lsch3: Use SVR based timer base address detection
Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.
Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 09c1033..2df56f7 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -23,7 +23,8 @@
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
-#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
+#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
+#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 58e90d8..3ccacb9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -30,7 +30,7 @@
#define pex_lut_in32(a) in_be32(a)
#define pex_lut_out32(a, v) out_be32(a, v)
#endif
-
+#ifndef __ASSEMBLY__
struct cpu_type {
char name[15];
u32 soc_ver;
@@ -39,7 +39,7 @@
#define CPU_TYPE_ENTRY(n, v, nc) \
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
-
+#endif
#define SVR_WO_E 0xFFFFFE
#define SVR_LS1012A 0x870400
#define SVR_LS1043A 0x879200
@@ -51,6 +51,8 @@
#define SVR_LS2085A 0x870100
#define SVR_LS2040A 0x870130
+#define SVR_DEV_LS2080A 0x8701
+
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
@@ -63,6 +65,7 @@
#define AHCI_PORT_TRANS_CFG 0x08000029
#define AHCI_PORT_AXICC_CFG 0x3fffffff
+#ifndef __ASSEMBLY__
/* AHCI (sata) register map */
struct ccsr_ahci {
u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
@@ -105,4 +108,5 @@
bool soc_has_dp_ddr(void);
bool soc_has_aiop(void);
+#endif
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */