Merge branch 'master' of git://git.denx.de/u-boot-fdt
* 'master' of git://git.denx.de/u-boot-fdt:
powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandles
fdt: update fdt_alloc_phandle to use fdt_get_phandle
fdt: check for fdt errors in fdt_create_phandle
fdt: Add a do_fixup_by_path_string() function
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
index 112ea56..8d25496 100644
--- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
@@ -27,16 +27,16 @@
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
- SET_QP_INFO( 1, 2, 1, 0),
- SET_QP_INFO( 3, 4, 2, 1),
- SET_QP_INFO( 5, 6, 3, 2),
- SET_QP_INFO( 7, 8, 4, 3),
- SET_QP_INFO( 9, 10, 5, 4),
- SET_QP_INFO( 0, 0, 0, 5),
- SET_QP_INFO( 0, 0, 0, 6),
- SET_QP_INFO( 0, 0, 0, 7),
- SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
- SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
+ SET_QP_INFO(1, 2, 1, 0),
+ SET_QP_INFO(3, 4, 2, 1),
+ SET_QP_INFO(5, 6, 3, 2),
+ SET_QP_INFO(7, 8, 4, 3),
+ SET_QP_INFO(9, 10, 5, 0),
+ SET_QP_INFO(11, 12, 1, 1),
+ SET_QP_INFO(13, 14, 2, 2),
+ SET_QP_INFO(15, 16, 3, 3),
+ SET_QP_INFO(17, 18, 4, 0), /* for now sdest to 0 */
+ SET_QP_INFO(19, 20, 5, 0), /* for now sdest to 0 */
};
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
index 9836588..96f3272 100644
--- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
@@ -27,16 +27,16 @@
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
- SET_QP_INFO( 1, 2, 1, 0),
- SET_QP_INFO( 3, 4, 2, 1),
- SET_QP_INFO( 5, 6, 3, 2),
- SET_QP_INFO( 7, 8, 4, 3),
- SET_QP_INFO( 9, 10, 5, 4),
- SET_QP_INFO( 0, 0, 0, 5),
- SET_QP_INFO( 0, 0, 0, 6),
- SET_QP_INFO( 0, 0, 0, 7),
- SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
- SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
+ SET_QP_INFO(1, 2, 1, 0),
+ SET_QP_INFO(3, 4, 2, 1),
+ SET_QP_INFO(5, 6, 3, 2),
+ SET_QP_INFO(7, 8, 4, 3),
+ SET_QP_INFO(9, 10, 5, 0),
+ SET_QP_INFO(11, 12, 1, 1),
+ SET_QP_INFO(13, 14, 2, 2),
+ SET_QP_INFO(15, 16, 3, 3),
+ SET_QP_INFO(17, 18, 4, 0), /* for now sdest to 0 */
+ SET_QP_INFO(19, 20, 5, 0), /* for now sdest to 0 */
};
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/p3060_serdes.c b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c
index 6387276..e720dcf 100644
--- a/arch/powerpc/cpu/mpc85xx/p3060_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c
@@ -83,8 +83,6 @@
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
- u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
- u32 ec1_ext, ec2_ext;
/* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */
@@ -116,23 +114,5 @@
devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1;
}
- ec1_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT;
- if (ec1_ext) {
- if ((ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII) ||
- (ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII))
- devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_4;
- }
-
- ec2_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT;
- if (ec2_ext) {
- if ((ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII) ||
- (ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII))
- devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4;
- }
-
- if ((rcwsr13 & FSL_CORENET_RCWSR13_EC3) ==
- FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII)
- devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4;
-
out_be32(&gur->devdisr2, devdisr2);
}
diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
index 2911c13..4254dd5 100644
--- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
@@ -27,16 +27,16 @@
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
- SET_QP_INFO( 1, 2, 1, 0),
- SET_QP_INFO( 3, 4, 2, 1),
- SET_QP_INFO( 5, 6, 3, 2),
- SET_QP_INFO( 7, 8, 4, 3),
- SET_QP_INFO( 9, 10, 5, 4),
- SET_QP_INFO( 0, 0, 0, 5),
- SET_QP_INFO( 0, 0, 0, 6),
- SET_QP_INFO( 0, 0, 0, 7),
- SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
- SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
+ SET_QP_INFO(1, 2, 1, 0),
+ SET_QP_INFO(3, 4, 2, 1),
+ SET_QP_INFO(5, 6, 3, 0),
+ SET_QP_INFO(7, 8, 4, 1),
+ SET_QP_INFO(9, 10, 5, 0),
+ SET_QP_INFO(11, 12, 1, 1),
+ SET_QP_INFO(13, 14, 2, 0),
+ SET_QP_INFO(15, 16, 3, 1),
+ SET_QP_INFO(17, 18, 4, 0),
+ SET_QP_INFO(19, 20, 5, 1),
};
#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index a29fe35..1bbf986 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1708,16 +1708,6 @@
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
#endif
-#if defined(CONFIG_PPC_P3060)
-#define FSL_CORENET_RCWSR13_EC1_EXT 0x1c000000
-#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII 0x04000000
-#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII 0x08000000
-#define FSL_CORENET_RCWSR13_EC2_EXT 0x01c00000
-#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII 0x00400000
-#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII 0x00800000
-#define FSL_CORENET_RCWSR13_EC3 0x00380000
-#define FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII 0x00100000
-#endif
#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \
|| defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index 5b6943d..efd9040 100644
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c
@@ -27,36 +27,9 @@
#include <asm/fsl_law.h>
#include <asm/mmu.h>
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
- * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
- * 0xe300_0000 0xe30f_ffff PCIe IO 1M
- * 0xf000_0000 0xf3ff_ffff SDRAM 64M
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- *
- * LAW 0 is reserved for boot mapping
- */
-
struct law_entry law_table[] = {
-#ifdef CONFIG_SYS_PCI2_MEM_PHYS
- SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
-#endif
- /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ /* LBC window - maps 256M */
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 3bcaac4..a8d57cd 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -50,10 +50,10 @@
uint cpu_board_rev = get_cpu_board_revision ();
- printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
- get_board_version (), pci_slot);
-
- printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ puts("Board: MPC8548CDS");
+ printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
+ get_board_version(), pci_slot);
+ printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
/*
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index b2c1b31..eb29e07 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -41,63 +41,63 @@
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
+ /* TLB 1 */
/*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
+ * Entry 0:
+ * FLASH(cover boot page) 16M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
/*
- * TLB 1: 1G Non-cacheable, guarded
- * 0x80000000 1G PCI1/PCIE 8,9,a,b
+ * Entry 1:
+ * CCSRBAR 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1G, 1),
+ 0, 1, BOOKE_PAGESZ_1M, 1),
/*
- * TLB 2: 256M Non-cacheable, guarded
+ * Entry 2:
+ * LBC SDRAM 64M Cacheable, non-guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
+ CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 2, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 3: 256M Non-cacheable, guarded
+ * Entry 3:
+ * CADMUS registers 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
+ 0, 3, BOOKE_PAGESZ_1M, 1),
/*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 1M PCI1 IO
- * 0xe210_0000 1M PCI2 IO
- * 0xe300_0000 1M PCIe IO
+ * Entry 4:
+ * PCI and PCIe MEM 1G Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
+ 0, 4, BOOKE_PAGESZ_1G, 1),
/*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
+ * Entry 5:
+ * PCI1 IO 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_64M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
/*
- * TLB 7: 64M Non-cacheable, guarded
- * 0xf8000000 64M CADMUS registers, relocated L2SRAM
+ * Entry 6:
+ * PCIe IO 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_64M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_1M, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index d3d610d..bd70a66 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -562,6 +562,7 @@
MPC8541CDS_legacy powerpc mpc85xx mpc8541cds freescale - MPC8541CDS:LEGACY
MPC8544DS powerpc mpc85xx mpc8544ds freescale
MPC8548CDS powerpc mpc85xx mpc8548cds freescale - MPC8548CDS
+MPC8548CDS_36BIT powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:36BIT
MPC8548CDS_legacy powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:LEGACY
MPC8555CDS powerpc mpc85xx mpc8555cds freescale - MPC8555CDS
MPC8555CDS_legacy powerpc mpc85xx mpc8555cds freescale - MPC8555CDS:LEGACY
@@ -668,6 +669,7 @@
P2020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH
P2041RDB powerpc mpc85xx p2041rdb freescale
P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
+P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT
P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P3041DS powerpc mpc85xx corenet_ds freescale
P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
diff --git a/drivers/net/fm/p3060.c b/drivers/net/fm/p3060.c
index b25bca7..176e1d2 100644
--- a/drivers/net/fm/p3060.c
+++ b/drivers/net/fm/p3060.c
@@ -52,7 +52,6 @@
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
- u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
@@ -70,22 +69,6 @@
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
return PHY_INTERFACE_MODE_RGMII;
- if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) ==
- FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII))
- return PHY_INTERFACE_MODE_RGMII;
-
- if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) ==
- FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII))
- return PHY_INTERFACE_MODE_MII;
-
- if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) ==
- FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII))
- return PHY_INTERFACE_MODE_RGMII;
-
- if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) ==
- FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII))
- return PHY_INTERFACE_MODE_MII;
-
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c
index a13b48ce..9d9397a 100644
--- a/drivers/net/phy/teranetics.c
+++ b/drivers/net/phy/teranetics.c
@@ -21,6 +21,7 @@
*
*/
#include <config.h>
+#include <common.h>
#include <phy.h>
#ifndef CONFIG_PHYLIB_10G
@@ -43,6 +44,38 @@
int tn2020_startup(struct phy_device *phydev)
{
+ unsigned int timeout = 5 * 1000; /* 5 second timeout */
+
+#define MDIO_PHYXS_LANE_READY (MDIO_PHYXS_LNSTAT_SYNC0 | \
+ MDIO_PHYXS_LNSTAT_SYNC1 | \
+ MDIO_PHYXS_LNSTAT_SYNC2 | \
+ MDIO_PHYXS_LNSTAT_SYNC3 | \
+ MDIO_PHYXS_LNSTAT_ALIGN)
+
+ /*
+ * Wait for the XAUI-SERDES lanes to align first. Under normal
+ * circumstances, this can take up to three seconds.
+ */
+ while (--timeout) {
+ int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT);
+ if (reg < 0) {
+ printf("TN2020: Error reading from PHY at "
+ "address %u\n", phydev->addr);
+ break;
+ }
+ if ((reg & MDIO_PHYXS_LANE_READY) == MDIO_PHYXS_LANE_READY)
+ break;
+ udelay(1000);
+ }
+ if (!timeout) {
+ /*
+ * A timeout is bad, but it may not be fatal, so don't
+ * return an error. Display a warning instead.
+ */
+ printf("TN2020: Timeout waiting for PHY at address %u to "
+ "align.\n", phydev->addr);
+ }
+
if (phydev->port != PORT_FIBRE)
return gen10g_startup(phydev);
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index ab887c1..4b5f719 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -29,6 +29,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
@@ -74,6 +78,11 @@
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
@@ -106,6 +115,37 @@
#endif
#undef CONFIG_CLOCKS_IN_MHZ
+/*
+ * Physical Address Map
+ *
+ * 32bit:
+ * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
+ * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
+ * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
+ * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
+ * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
+ *
+ * 36bit:
+ * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
+ * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
+ * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
+ * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
+ * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
+ * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
+ * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
+ * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
+ * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
+ * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
+ * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
+ *
+ */
+
/*
* Local Bus Definitions
@@ -141,16 +181,24 @@
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
-#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
+#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
-#define CONFIG_SYS_BR0_PRELIM 0xff801001
-#define CONFIG_SYS_BR1_PRELIM 0xff001001
+#define CONFIG_SYS_BR0_PRELIM \
+ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \
+ | BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR1_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR0_PRELIM 0xff806e65
#define CONFIG_SYS_OR1_PRELIM 0xff806e65
-#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+ {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
@@ -168,12 +216,12 @@
/*
* SDRAM on the Local Bus
*/
-#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
-#define CONFIG_SYS_LBC_CACHE_SIZE 64
-#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
-#define CONFIG_SYS_LBC_NONCACHE_SIZE 64
-
-#define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
+#else
+#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
+#endif
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
@@ -194,7 +242,9 @@
* FIXME: the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861
+#define CONFIG_SYS_BR2_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
+ | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
@@ -265,15 +315,19 @@
#define CONFIG_FSL_CADMUS
#define CADMUS_BASE_ADDR 0xf8000000
-#define CONFIG_SYS_BR3_PRELIM 0xf8000801
+#ifdef CONFIG_PHYS_64BIT
+#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
+#else
+#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
+#endif
+#define CONFIG_SYS_BR3_PRELIM \
+ (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
-
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
@@ -326,47 +380,54 @@
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
-#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
-
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
+#else
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
+#endif
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
+#else
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#ifdef CONFIG_PCI2
-#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000
-#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
#endif
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_NAME "Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
+#else
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
+#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
+#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
+#endif
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
#endif
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
+#endif
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_LEGACY
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index b3d981f..4a1e9e9 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -630,22 +630,6 @@
#endif
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
-
-/* video */
-#define CONFIG_VIDEO
-#ifdef CONFIG_VIDEO
-#define CONFIG_BIOSEMU
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/