tree 3b18a7befc20e046b18d0c2dafbe64c6d80d5c4e
parent c80784102e973c7668df1b5801026a7ed1b336d5
author Jonathan Liu <net147@gmail.com> 1679567758 +1100
committer Kever Yang <kever.yang@rock-chips.com> 1682061361 +0800

ram: rk3399: add missing high row detection

For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin
prints:
"Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB"

U-Boot TPL prints:
"BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB"

Add missing high row detection so that U-Boot TPL prints Row=16, same as
the Rockchip ddr init bin:
"BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB"

Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>