diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S
index 5dcc24f..03aebe4 100644
--- a/cpu/bf533/cache.S
+++ b/cpu/bf533/cache.S
@@ -11,7 +11,7 @@
 	P0 = R2;
 	P1 = R1;
 	CSYNC;
-	1:
+1:
 	IFLUSH[P0++];
 	CC = P0 < P1(iu);
 	IF CC JUMP 1b(bp);
@@ -41,10 +41,10 @@
 	P0.H = (IMEM_CONTROL >> 16);
 	R7 =[P0];
 
-/*
- * Clear the IMC bit , All valid bits in the instruction
- * cache are set to the invalid state
- */
+	/*
+	 * Clear the IMC bit , All valid bits in the instruction
+	 * cache are set to the invalid state
+	 */
 	BITCLR(R7, IMC_P);
 	CLI R6;
 	/* SSYNC required before invalidating cache. */
@@ -80,10 +80,10 @@
 	P0.H = (DMEM_CONTROL >> 16);
 	R7 =[P0];
 
-/*
- * Clear the DMC[1:0] bits, All valid bits in the data
- * cache are set to the invalid state
- */
+	/*
+	 * Clear the DMC[1:0] bits, All valid bits in the data
+	 * cache are set to the invalid state
+	 */
 	BITCLR(R7, DMC0_P);
 	BITCLR(R7, DMC1_P);
 	CLI R6;
@@ -118,11 +118,11 @@
 	CC = P0 < P1(iu);
 	IF CC JUMP 1b(bp);
 
-/*
- * If the data crosses a cache line, then we'll be pointing to
- * the last cache line, but won't have flushed/invalidated it yet, so do
- * one more.
- */
+	/*
+	 * If the data crosses a cache line, then we'll be pointing to
+	 * the last cache line, but won't have flushed/invalidated it yet, so do
+	 * one more.
+	 */
 	FLUSHINV[P0];
 	SSYNC;
 	RTS;
diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c
index bd393d5..ac8ec51 100644
--- a/cpu/bf533/cpu.c
+++ b/cpu/bf533/cpu.c
@@ -30,6 +30,7 @@
 #include <command.h>
 #include <asm/entry.h>
 #include <asm/cplb.h>
+#include <asm/io.h>
 
 #define CACHE_ON 1
 #define CACHE_OFF 0
@@ -37,16 +38,6 @@
 extern unsigned int icplb_table[page_descriptor_table_size][2];
 extern unsigned int dcplb_table[page_descriptor_table_size][2];
 
-#ifdef DEBUG
-#define pr_debug(fmt,arg...)  printf(fmt,##arg)
-#else
-static inline int
-    __attribute__ ((format(printf, 1, 2))) pr_debug(const char *fmt, ...)
-{
-	return 0;
-}
-#endif
-
 int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
@@ -70,10 +61,6 @@
 {
 	unsigned int *I0, *I1;
 	int i, j = 0;
-#ifdef __ADSPBF537__
-	if ((*pCHIPID >> 28) < 2)
-		return;
-#endif
 
 	/* Before enable icache, disable it first */
 	icache_disable();
@@ -83,7 +70,7 @@
 	/* make sure the locked ones go in first */
 	for (i = 0; i < page_descriptor_table_size; i++) {
 		if (CPLB_LOCK & icplb_table[i][1]) {
-			pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
 				 icplb_table[i][0], icplb_table[i][1]);
 			*I0++ = icplb_table[i][0];
 			*I1++ = icplb_table[i][1];
@@ -93,7 +80,7 @@
 
 	for (i = 0; i < page_descriptor_table_size; i++) {
 		if (!(CPLB_LOCK & icplb_table[i][1])) {
-			pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
 				 icplb_table[i][0], icplb_table[i][1]);
 			*I0++ = icplb_table[i][0];
 			*I1++ = icplb_table[i][1];
@@ -107,31 +94,27 @@
 	/* Fill the rest with invalid entry */
 	if (j <= 15) {
 		for (; j <= 16; j++) {
-			pr_debug("filling %i with 0", j);
+			debug("filling %i with 0", j);
 			*I1++ = 0x0;
 		}
 
 	}
 
 	cli();
-	__builtin_bfin_ssync();
+	sync();
 	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-	__builtin_bfin_ssync();
+	sync();
 	sti();
 }
 
 void icache_disable(void)
 {
-#ifdef __ADSPBF537__
-	if ((*pCHIPID >> 28) < 2)
-		return;
-#endif
 	cli();
-	__builtin_bfin_ssync();
+	sync();
 	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-	__builtin_bfin_ssync();
+	sync();
 	sti();
 }
 
@@ -160,20 +143,20 @@
 	/* make sure the locked ones go in first */
 	for (i = 0; i < page_descriptor_table_size; i++) {
 		if (CPLB_LOCK & dcplb_table[i][1]) {
-			pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
 				 dcplb_table[i][0], dcplb_table[i][1]);
 			*I0++ = dcplb_table[i][0];
 			*I1++ = dcplb_table[i][1];
 			j++;
 		} else {
-			pr_debug("skip   %02i %02i 0x%08x 0x%08x\n", i, j,
+			debug("skip   %02i %02i 0x%08x 0x%08x\n", i, j,
 				 dcplb_table[i][0], dcplb_table[i][1]);
 		}
 	}
 
 	for (i = 0; i < page_descriptor_table_size; i++) {
 		if (!(CPLB_LOCK & dcplb_table[i][1])) {
-			pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
 				 dcplb_table[i][0], dcplb_table[i][1]);
 			*I0++ = dcplb_table[i][0];
 			*I1++ = dcplb_table[i][1];
@@ -187,33 +170,32 @@
 	/* Fill the rest with invalid entry */
 	if (j <= 15) {
 		for (; j <= 16; j++) {
-			pr_debug("filling %i with 0", j);
+			debug("filling %i with 0", j);
 			*I1++ = 0x0;
 		}
 	}
 
 	cli();
 	temp = *(unsigned int *)DMEM_CONTROL;
-	__builtin_bfin_ssync();
+	sync();
 	asm(" .align 8; ");
 	*(unsigned int *)DMEM_CONTROL =
 	    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
-	__builtin_bfin_ssync();
+	sync();
 	sti();
 }
 
 void dcache_disable(void)
 {
-
 	unsigned int *I0, *I1;
 	int i;
 
 	cli();
-	__builtin_bfin_ssync();
+	sync();
 	asm(" .align 8; ");
 	*(unsigned int *)DMEM_CONTROL &=
 	    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-	__builtin_bfin_ssync();
+	sync();
 	sti();
 
 	/* after disable dcache,
diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S
index 58fe4c8..4a6c64b 100644
--- a/cpu/bf533/flush.S
+++ b/cpu/bf533/flush.S
@@ -59,7 +59,7 @@
 	[--SP] = LC1;
 	[--SP] = LT1;
 	[--SP] = LB1;
-	
+
 	/* If it's a 1K or 4K page, then it's quickest to
 	 * just systematically flush all the addresses in
 	 * the page, regardless of whether they're in the
@@ -101,7 +101,7 @@
 	 * sub-bank, looking for dirty, valid tags that match our
 	 * address prefix.
 	 */
-	
+
 	P5.L = (ITEST_COMMAND & 0xFFFF);
 	P5.H = (ITEST_COMMAND >> 16);
 	P4.L = (ITEST_DATA0 & 0xFFFF);
@@ -119,7 +119,7 @@
 	 * fetching tags, so we only have to set Set, Bank,
 	 * Sub-bank and Way.
 	 */
-	
+
 	P2 = 4;
 	LSETUP (ifs1, ife1) LC1 = P2;
 ifs1:	P0 = 32;		/* iterate over all sets*/
@@ -180,8 +180,10 @@
 	SSYNC;
 	IFLUSH [P0++];		/* because CSYNC can't end loops.*/
 	LSETUP (isall, ieall) LC0 = P1;
-isall:IFLUSH [P0++];
-ieall: NOP;	
+isall:
+	IFLUSH [P0++];
+ieall:
+	NOP;
 	SSYNC;
 	JUMP ifinished;
 
@@ -236,7 +238,7 @@
 	[--SP] = LC1;
 	[--SP] = LT1;
 	[--SP] = LB1;
-	
+
 	/* If it's a 1K or 4K page, then it's quickest to
 	 * just systematically flush all the addresses in
 	 * the page, regardless of whether they're in the
@@ -250,9 +252,9 @@
 
 	/* We're only interested in the page's size, so extract
 	 * this from the CPLB (bits 17:16), and scale to give an
-	 * offset into the page_size and page_prefix tables.	
+	 * offset into the page_size and page_prefix tables.
 	 */
-		
+
 	R1 <<= 14;
 	R1 >>= 30;
 	R1 <<= 2;
@@ -298,13 +300,13 @@
 	 * R1 = Page length (actually, offset into size/prefix tables)
 	 * R2 = Bank select mask
 	 * R3 = sub-bank deposit values
-  	 *
+	 *
 	 * The cache has 2 Ways, and 64 sets, so we iterate through
 	 * the sets, accessing the tag for each Way, for our Bank and
 	 * sub-bank, looking for dirty, valid tags that match our
 	 * address prefix.
 	 */
-	
+
 	P5.L = (DTEST_COMMAND & 0xFFFF);
 	P5.H = (DTEST_COMMAND >> 16);
 	P4.L = (DTEST_DATA0 & 0xFFFF);
@@ -323,7 +325,7 @@
 	 * fetching tags, so we only have to set Set, Bank,
 	 * Sub-bank and Way.
 	 */
-	
+
 	P2 = 2;
 	LSETUP (fs1, fe1) LC1 = P2;
 fs1:	P0 = 64;		/* iterate over all sets*/
diff --git a/cpu/bf533/init_sdram.S b/cpu/bf533/init_sdram.S
index 1aae9e3..e1a8e2f 100644
--- a/cpu/bf533/init_sdram.S
+++ b/cpu/bf533/init_sdram.S
@@ -109,14 +109,14 @@
 	r0.l = (AMBCTL1VAL & 0xFFFF);
 	[p2] = r0;
 	ssync;
-	
+
 	p2.h = (EBIU_AMBCTL0 >> 16);
 	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
 	r0.h = (AMBCTL0VAL >> 16);
 	r0.l = (AMBCTL0VAL & 0xFFFF);
 	[p2] = r0;
 	ssync;
-	
+
 	p2.h = (EBIU_AMGCTL >> 16);
 	p2.l = (EBIU_AMGCTL & 0xffff);
 	r0 = AMGCTLVAL;
diff --git a/cpu/bf533/init_sdram_bootrom_initblock.S b/cpu/bf533/init_sdram_bootrom_initblock.S
index 21cfeec..99ed920 100644
--- a/cpu/bf533/init_sdram_bootrom_initblock.S
+++ b/cpu/bf533/init_sdram_bootrom_initblock.S
@@ -109,14 +109,14 @@
 	r0.l = (AMBCTL1VAL & 0xFFFF);
 	[p2] = r0;
 	ssync;
-	
+
 	p2.h = (EBIU_AMBCTL0 >> 16);
 	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
 	r0.h = (AMBCTL0VAL >> 16);
 	r0.l = (AMBCTL0VAL & 0xFFFF);
 	[p2] = r0;
 	ssync;
-	
+
 	p2.h = (EBIU_AMGCTL >> 16);
 	p2.l = (EBIU_AMGCTL & 0xffff);
 	r0 = AMGCTLVAL;
diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c
index eb55205..11a46be 100644
--- a/cpu/bf533/serial.c
+++ b/cpu/bf533/serial.c
@@ -49,8 +49,11 @@
 #include <asm/bitops.h>
 #include <asm/delay.h>
 #include <asm/uaccess.h>
+#include <asm/io.h>
 #include "bf533_serial.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 unsigned long pll_div_fact;
 
 void calc_baud(void)
@@ -84,29 +87,29 @@
 
 	/* Enable UART */
 	*pUART_GCTL |= UART_GCTL_UCEN;
-	__builtin_bfin_ssync();
+	sync();
 
 	/* Set DLAB in LCR to Access DLL and DLH */
 	ACCESS_LATCH;
-	__builtin_bfin_ssync();
+	sync();
 
 	*pUART_DLL = hw_baud_table[i].dl_low;
-	__builtin_bfin_ssync();
+	sync();
 	*pUART_DLH = hw_baud_table[i].dl_high;
-	__builtin_bfin_ssync();
+	sync();
 
 	/* Clear DLAB in LCR to Access THR RBR IER */
 	ACCESS_PORT_IER;
-	__builtin_bfin_ssync();
+	sync();
 
 	/* Enable  ERBFI and ELSI interrupts
 	 * to poll SIC_ISR register*/
 	*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
-	__builtin_bfin_ssync();
+	sync();
 
 	/* Set LCR to Word Lengh 8-bit word select */
 	*pUART_LCR = UART_LCR_WLS8;
-	__builtin_bfin_ssync();
+	sync();
 
 	return;
 }
diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c
index 5e2ce9b..248e34f 100644
--- a/cpu/bf533/traps.c
+++ b/cpu/bf533/traps.c
@@ -44,16 +44,7 @@
 #include "cpu.h"
 #include <asm/arch/anomaly.h>
 #include <asm/cplb.h>
-
-#ifdef DEBUG
-#define pr_debug(fmt,arg...)  printf(fmt,##arg)
-#else
-static inline int
-    __attribute__ ((format(printf, 1, 2))) pr_debug(const char *fmt, ...)
-{
-	return 0;
-}
-#endif
+#include <asm/io.h>
 
 void init_IRQ(void)
 {
@@ -83,13 +74,13 @@
 	unsigned short data = 0;
 
 	switch (trapnr) {
-		/* 0x26 - Data CPLB Miss */
+	/* 0x26 - Data CPLB Miss */
 	case VEC_CPLB_M:
 
 #ifdef ANOMALY_05000261
 		/*
-		 * Work around an anomaly: if we see a new DCPLB fault, 
-		 * return without doing anything. Then, 
+		 * Work around an anomaly: if we see a new DCPLB fault,
+		 * return without doing anything. Then,
 		 * if we get the same fault again, handle it.
 		 */
 		addr = last_cplb_fault_retx;
@@ -104,9 +95,9 @@
 	case VEC_CPLB_I_M:
 
 		if (data) {
-			addr = *pDCPLB_FAULT_ADDR;
+			addr = *(unsigned int *)pDCPLB_FAULT_ADDR;
 		} else {
-			addr = *pICPLB_FAULT_ADDR;
+			addr = *(unsigned int *)pICPLB_FAULT_ADDR;
 		}
 		for (i = 0; i < page_descriptor_table_size; i++) {
 			if (data) {
@@ -117,7 +108,7 @@
 				j = icplb_table[i][0];
 			}
 			if ((j <= addr) && ((j + size) > addr)) {
-				pr_debug("found %i 0x%08x\n", i, j);
+				debug("found %i 0x%08x\n", i, j);
 				break;
 			}
 		}
@@ -128,16 +119,16 @@
 
 		/* Turn the cache off */
 		if (data) {
-			__builtin_bfin_ssync();
+			sync();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL &=
 			    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-			__builtin_bfin_ssync();
+			sync();
 		} else {
-			__builtin_bfin_ssync();
+			sync();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-			__builtin_bfin_ssync();
+			sync();
 		}
 
 		if (data) {
@@ -150,16 +141,16 @@
 
 		j = 0;
 		while (*I1 & CPLB_LOCK) {
-			pr_debug("skipping %i %08p - %08x\n", j, I1, *I1);
+			debug("skipping %i %08p - %08x\n", j, I1, *I1);
 			*I0++;
 			*I1++;
 			j++;
 		}
 
-		pr_debug("remove %i 0x%08x  0x%08x\n", j, *I0, *I1);
+		debug("remove %i 0x%08x  0x%08x\n", j, *I0, *I1);
 
 		for (; j < 15; j++) {
-			pr_debug("replace %i 0x%08x  0x%08x\n", j, I0, I0 + 1);
+			debug("replace %i 0x%08x  0x%08x\n", j, I0, I0 + 1);
 			*I0++ = *(I0 + 1);
 			*I1++ = *(I1 + 1);
 		}
@@ -177,22 +168,22 @@
 		}
 
 		for (j = 0; j < 16; j++) {
-			pr_debug("%i 0x%08x  0x%08x\n", j, *I0++, *I1++);
+			debug("%i 0x%08x  0x%08x\n", j, *I0++, *I1++);
 		}
 
 		/* Turn the cache back on */
 		if (data) {
 			j = *(unsigned int *)DMEM_CONTROL;
-			__builtin_bfin_ssync();
+			sync();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL =
 			    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
-			__builtin_bfin_ssync();
+			sync();
 		} else {
-			__builtin_bfin_ssync();
+			sync();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-			__builtin_bfin_ssync();
+			sync();
 		}
 
 		break;
@@ -209,42 +200,41 @@
 		do_reset(NULL, 0, 0, NULL);
 	}
 
-      trap_c_return:
 	return;
 
 }
 
 void dump(struct pt_regs *fp)
 {
-	pr_debug("RETE:  %08lx  RETN: %08lx  RETX: %08lx  RETS: %08lx\n",
+	debug("RETE:  %08lx  RETN: %08lx  RETX: %08lx  RETS: %08lx\n",
 		 fp->rete, fp->retn, fp->retx, fp->rets);
-	pr_debug("IPEND: %04lx  SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
-	pr_debug("SEQSTAT: %08lx    SP: %08lx\n", (long)fp->seqstat, (long)fp);
-	pr_debug("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n",
+	debug("IPEND: %04lx  SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
+	debug("SEQSTAT: %08lx    SP: %08lx\n", (long)fp->seqstat, (long)fp);
+	debug("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n",
 		 fp->r0, fp->r1, fp->r2, fp->r3);
-	pr_debug("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n",
+	debug("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n",
 		 fp->r4, fp->r5, fp->r6, fp->r7);
-	pr_debug("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n",
+	debug("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n",
 		 fp->p0, fp->p1, fp->p2, fp->p3);
-	pr_debug("P4: %08lx    P5: %08lx    FP: %08lx\n",
+	debug("P4: %08lx    P5: %08lx    FP: %08lx\n",
 		 fp->p4, fp->p5, fp->fp);
-	pr_debug("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
+	debug("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
 		 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
 
-	pr_debug("LB0: %08lx  LT0: %08lx  LC0: %08lx\n",
+	debug("LB0: %08lx  LT0: %08lx  LC0: %08lx\n",
 		 fp->lb0, fp->lt0, fp->lc0);
-	pr_debug("LB1: %08lx  LT1: %08lx  LC1: %08lx\n",
+	debug("LB1: %08lx  LT1: %08lx  LC1: %08lx\n",
 		 fp->lb1, fp->lt1, fp->lc1);
-	pr_debug("B0: %08lx  L0: %08lx  M0: %08lx  I0: %08lx\n",
+	debug("B0: %08lx  L0: %08lx  M0: %08lx  I0: %08lx\n",
 		 fp->b0, fp->l0, fp->m0, fp->i0);
-	pr_debug("B1: %08lx  L1: %08lx  M1: %08lx  I1: %08lx\n",
+	debug("B1: %08lx  L1: %08lx  M1: %08lx  I1: %08lx\n",
 		 fp->b1, fp->l1, fp->m1, fp->i1);
-	pr_debug("B2: %08lx  L2: %08lx  M2: %08lx  I2: %08lx\n",
+	debug("B2: %08lx  L2: %08lx  M2: %08lx  I2: %08lx\n",
 		 fp->b2, fp->l2, fp->m2, fp->i2);
-	pr_debug("B3: %08lx  L3: %08lx  M3: %08lx  I3: %08lx\n",
+	debug("B3: %08lx  L3: %08lx  M3: %08lx  I3: %08lx\n",
 		 fp->b3, fp->l3, fp->m3, fp->i3);
 
-	pr_debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
-	pr_debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
+	debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
+	debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
 
 }