// SPDX-License-Identifier: GPL-2.0+
/*
 * ABB PGGA km8321 common ports Device Tree Source
 *
 * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
 *
 */

/dts-v1/;

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8321@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <16384>;		// L1, 16K
			i-cache-size = <16384>;		// L1, 16K
			timebase-frequency = <66000000>;
			bus-frequency = <264000000>;
			clock-frequency = <528000000>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;
	};

	soc: soc8321@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <264000000>;

		i2c0: i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl,mpc8313-i2c","fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			clock-frequency = <100000>;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <264000000>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8321-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8321-dma-channel",
					     "fsl,elo-dma-channel";
				reg = <0 0x80>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8321-dma-channel",
					     "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8321-dma-channel",
					     "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8321-dma-channel",
					     "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		ipic: pic@700 {
			#address-cells = <0>;
			#interrupt-cells = <2>;
			compatible = "fsl,pq2pro-pic", "fsl,ipic";
			interrupt-controller;
			reg = <0x700 0x100>;
			device_type = "ipic";
		};

		par_io: par_io@1400 {
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x1400 0x100>;
			ranges;
			device_type = "par_io";
			num-ports = <7>;

			qe_pio_d: gpio-controller@48 {
				#gpio-cells = <2>;
				compatible = "fsl,mpc8360-qe-pario-bank",
					     "fsl,mpc8323-qe-pario-bank";
				reg = <0x1448 0x18>;
				gpio-controller;
			};
		};
	};

	qe: qe@e0100000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "qe";
		compatible = "fsl,qe";
		ranges = <0x0 0xe0100000 0x00100000>;
		reg = <0xe0100000 0x480>;
		brg-frequency = <0>;
		bus-frequency = <396000000>;

		muram@10000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,qe-muram", "fsl,cpm-muram";
			ranges = <0x0 0x00010000 0x00004000>;

			data-only@0 {
				compatible = "fsl,qe-muram-data",
					     "fsl,cpm-muram-data";
				reg = <0x0 0x4000>;
			};
		};

		/* Piggy2 (UCC4, MDIO 0x00, RMII) */
		enet_piggy2: ucc@3200 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <4>;
			reg = <0x3200 0x200>;
			interrupts = <35>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "clk17";
			phy-handle = <&phy_piggy2>;
			phy-connection-type = "rmii";
			pio-handle = <&pio_ucc4>;
		};

		mdio: mdio@3320 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3320 0x18>;
			compatible = "fsl,ucc-mdio";

			/* Piggy2 (UCC4, MDIO 0x00, RMII) */
			phy_piggy2: ethernet-phy@00 {
				reg = <0x0>;
				device_type = "ethernet-phy";
			};
		};

		qeic: interrupt-controller@80 {
			interrupt-controller;
			compatible = "fsl,qe-ic";
			#address-cells = <0>;
			#interrupt-cells = <1>;
			reg = <0x80 0x80>;
			big-endian;
			interrupts = <32 8 33 8>;
			interrupt-parent = <&ipic>;
		};
		bootcount@0x13ff8 {
			device_type = "bootcount";
			compatible = "u-boot,bootcount";
			reg = <0x13ff8 0x08>;
		};

		spi0: spi@4c0 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x4c0 0x40>;
			interrupts = <2>;
			interrupt-parent = <&qeic>;
			mode = "qe";
			#address-cells = <1>;
			#size-cells = <0>;
			pio-handle = <&pio_spi>;
		};
	};

	localbus: localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8321-localbus", "fsl,pq2pro-localbus",
			     "simple-bus";
		reg = <0xe0005000 0xd8>;
	};
};

#include "km8321-uboot.dtsi"