clk: renesas: Synchronize Gen2 tables with Linux 5.0
Synchronize R-Car Gen2 clock tables with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index e8f57c3..b6be1bc 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* r8a7794 Clock Pulse Generator / Module Standby and Software Reset
*
@@ -6,10 +7,6 @@
* Based on clk-rcar-gen2.c
*
* Copyright (C) 2013 Ideas On Board SPRL
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
*/
#include <common.h>
@@ -54,7 +51,6 @@
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
- DEF_BASE("lb", R8A7794_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
@@ -68,6 +64,7 @@
DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1),
DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1),
+ DEF_FIXED("lb", R8A7794_CLK_LB, CLK_PLL1, 24, 1),
DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1),
@@ -120,6 +117,7 @@
DEF_MOD("cmt1", 329, R8A7794_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP),
+ DEF_MOD("rwdt", 402, R8A7794_CLK_R),
DEF_MOD("irqc", 407, R8A7794_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS),
DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP),