diff --git a/doc/README.dk20k200_std32 b/doc/README.dk20k200_std32
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+
+===============================================================================
+	C P U ,	  M E M O R Y ,	  I N / O U T	C O M P O N E N T S
+===============================================================================
+see also [1]-[4]
+
+CPU:	"standard_32"
+	32 bit NIOS for 33.333 MHz (nasys_clock_freq = 33333000)
+	256 Byte for register file (15 levels)
+	no instruction cache
+	no data cache
+	1 KByte On Chip ROM with GERMS boot monitor
+	no On Chip RAM
+	MSTEP multiplier
+	no Debug Core
+	no On Chip Instrumentation (OCI) enabled
+
+	U-Boot CFG:	CFG_NIOS_CPU_CLK	     = 50000000
+			CFG_NIOS_CPU_ICACHE	     = 0
+			CFG_NIOS_CPU_DCACHE	     = 0
+			CFG_NIOS_CPU_REG_NUMS	     = 256
+			CFG_NIOS_CPU_MUL	     = 0
+			CFG_NIOS_CPU_MSTEP	     = 1
+			CFG_NIOS_CPU_DBG_CORE	     = 0
+
+IRQ:	 Nr.  | used by
+	------+--------------------------------------------------------
+	 25   | TIMER0	  |  CFG_NIOS_CPU_TIMER0_IRQ = 25
+	 26   | UART0	  |  CFG_NIOS_CPU_UART0_IRQ  = 26
+	 27   | PIO2	  |  CFG_NIOS_CPU_PIO2_IRQ   = 27
+	 28   | UART1	  |  CFG_NIOS_CPU_UART1_IRQ  = 28    (debug)
+
+MEMORY:	  1 MByte Flash
+	256 KByte SRAM
+	(SDRAM with standard SODIMM only)
+
+Timer:	TIMER0: high priority programmable timer (IRQ25)
+
+	U-Boot CFG:	CFG_NIOS_CPU_TICK_TIMER	     = 0
+
+PIO:	 Nr.  | description
+	------+--------------------------------------------------------
+	 PIO0 | SEVENSEG:  16 outputs for user seven segment display
+	 PIO1 | LED:	    8 outputs for user LEDs
+	 PIO2 | BUTTON:	    4 inputs for user push buttons (IRQ27)
+	 PIO3 | LCD:	   11 in/outputs for ASCII LCD
+
+	U-Boot CFG:	CFG_NIOS_CPU_SEVENSEG_PIO    = 0
+			CFG_NIOS_CPU_LED_PIO	     = 1
+			CFG_NIOS_CPU_BUTTON_PIO	     = 2
+			CFG_NIOS_CPU_LCD_PIO	     = 3
+
+UART:	UART0: fixed baudrate of 115200, fixed protocol 8N2,
+	       without handshake RTS/CTS (IRQ26)
+	UART1: fixed baudrate of 115200, fixed protocol 8N1,
+	       without handshake RTS/CTS (IRQ28)
+
+
+===============================================================================
+	M E M O R Y   M A P
+===============================================================================
+
+- - - - - - - - - - -	external memory	  - - - - - - - - - - - - - - - - - - -
+
+  0x00200000 ---15------------8|7-------------0-
+	       |  sector 18		       | \
+    + 0x0f0000 |- - - - - - - - - - - - - - - -| |
+	       |	       :	       | |
+  Flash	       |-   -	-   -  :  -   -	  -   -| |
+	       |  sector 5     :	       | |
+    + 0x020000 |-   -	-   -  -  -   -	  -   -| |
+	       |  sector 4 (size = 0x10000)    | |
+    + 0x010000 |- - - - - - - - - - - - - - - -|  > CFG_NIOS_CPU_FLASH_SIZE
+	       |  sector 3 (size = 0x08000)    | |   = 0x00100000
+    + 0x008000 |- - - - - - - - - - - - - - - -| |
+	       |  sector 2 (size = 0x02000)    | |
+    + 0x006000 |- - - - - - - - - - - - - - - -| |
+	       |  sector 1 (size = 0x02000)    | |
+    + 0x004000 |- - - - - - - - - - - - - - - -| |
+	       |  sector 0 (size = 0x04000)    | /
+  0x00100000 ---15------------8|7-------------0-    CFG_NIOS_CPU_FLASH_BASE
+	       |			       |
+	       :	      gap	       :
+	       |			       |
+  0x00080000 ---32-----------16|15------------0-
+  0x00080000 --+32-----------16|15------------0+
+	       |	       .	       | \ \
+	       |	       .	       | | |
+	       |	       .	       | |  > CFG_NIOS_CPU_VEC_SIZE
+	       |	       .	       | | |   = 0x00000100
+	       |	       .	       | | /
+  0x0007ff00   |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE
+  0x0007ff00   |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK
+	       |	       .	       | | \
+	       |	       .	       | | |
+	       |	       .	       | |  > stack area
+	       |	       .	       | | |
+	       |	       .	       | | V
+	       |	       .	       | |
+  SRAM	       |	       .	       |  > CFG_NIOS_CPU_SRAM_SIZE
+	       |	       .	       | |   = 0x00040000
+	       |			       | /
+  0x00040000 ---32-----------16|15------------0-    CFG_NIOS_CPU_SRAM_BASE
+	       |			       |
+	       :	      gap	       :
+	       :			       :
+
+- - - - - - - - - - -	  on chip i/o	  - - - - - - - - - - - - - - - - - - -
+
+	       :			       :
+	       :	      gap	       :
+	       |			       |
+  0x00000400 ---32-----------16|15------------0-
+	       |		     (unused)  | \
+	+ 0x1c |- - - - - - - - - - - - - - - -| |
+	       |		     (unused)  | |
+	+ 0x18 |- - - - - - - - - - - - - - - -| |
+	       |		     (unused)  | |
+	+ 0x14 |- - - - - - - - - - - - - - - -| |
+  UART0	       |		     (unused)  |  > 0x00000020
+  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
+	       |  control (10 bit)	 (rw)  | |
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+	       |  status (10 bit)	 (rw)  | |
+	+ 0x08 |- - - - - - - - - - - - - - - -| |
+	       |  txdata (8 bit)	 (wo)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  rxdata (8 bit)	 (ro)  | /
+  0x000004c0 ---32-----------16|15------------0-    CFG_NIOS_CPU_UART1
+	       |			       |
+	       :	      gap	       :
+	       |			       |
+  0x00000490 ---32-----------16|15------------0-
+	       |		     (unused)  | \
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+  PIO3	       |		     (unused)  | |
+  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
+	       |  direction (11 bit)	 (rw)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  data (11 bit)		 (rw)  | /
+  0x00000480 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO3
+	       |  edgecapture (12 bit)	 (rw)  | \
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+  PIO2	       |  interruptmask (12 bit) (rw)  | |
+  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
+	       |		     (unused)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  data (12 bit)		 (ro)  | /
+  0x00000470 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO2
+	       |		     (unused)  | \
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+  PIO1	       |		     (unused)  | |
+  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
+	       |  direction (2 bit)	 (rw)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  data (2 bit)		 (rw)  | /
+  0x00000460 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO1
+	       |		     (unused)  | \
+	+ 0x1c |- - - - - - - - - - - - - - - -| |
+	       |		     (unused)  | |
+	+ 0x18 |- - - - - - - - - - - - - - - -| |
+	       |  snaph (16 bit)	 (rw)  | |
+	+ 0x14 |- - - - - - - - - - - - - - - -| |
+  TIMER0       |  snapl (16 bit)	 (rw)  | |
+  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
+	       |  periodh (16 bit)	 (rw)  | |
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+	       |  periodl (16 bit)	 (rw)  | |
+	+ 0x08 |- - - - - - - - - - - - - - - -| |
+	       |  control (4 bit)	 (rw)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  status (2 bit)	 (rw)  | /
+  0x00000440 ---32-----------16|15------------0-    CFG_NIOS_CPU_TIMER0
+	       |		     (unused)  | \
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+  PIO0	       |		     (unused)  | |
+  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
+	       |		     (unused)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  data (16 bit)		 (wo)  | /
+  0x00000420 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO0
+	       |		     (unused)  | \
+	+ 0x1c |- - - - - - - - - - - - - - - -| |
+	       |		     (unused)  | |
+	+ 0x18 |- - - - - - - - - - - - - - - -| |
+	       |		     (unused)  | |
+	+ 0x14 |- - - - - - - - - - - - - - - -| |
+  UART0	       |		     (unused)  |  > 0x00000020
+  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
+	       |  control (10 bit)	 (rw)  | |
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+	       |  status (10 bit)	 (rw)  | |
+	+ 0x08 |- - - - - - - - - - - - - - - -| |
+	       |  txdata (8 bit)	 (wo)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  rxdata (8 bit)	 (ro)  | /
+  0x00000400 ---32-----------16|15------------0-    CFG_NIOS_CPU_UART0
+
+- - - - - - - - - - -	on chip memory	  - - - - - - - - - - -
+
+  0x00000400 ---32-----------16|15------------0-
+	       |	       :	       | \
+	       |	       :	       | |
+  GERMS	       |	       :	       |  > na_boot_monitor_rom_size
+	       |	       :	       | |   = 0x00000400
+	       |	       :	       | /
+  0x00000000   |- - - - - - - - - - - - - - - -+- - nasys_reset_address
+  0x00000000 ---32-----------16|15------------0-    na_boot_monitor_rom
+
+
+===============================================================================
+	F L A S H   M E M O R Y	  A L L O C A T I O N
+===============================================================================
+
+  0x00200000 ---15------------8|7-------------0-
+	       |	       :	       | \
+  SAFE	       |	       :	       |  > 256 KByte
+  FPGA conf.   |	       :	       | /    (NOT usable by software)
+  0x001c0000 --+- - - - - - - -:- - - - - - - -+-
+	       |	       :	       | \
+  USER	       |	       :	       |  > 256 KByte
+  FPGA conf.   |	       :	       | /    (NOT usable by software)
+  0x00180000 --+- - - - - - - -:- - - - - - - -+-
+	       |	       :	       | \
+	       |	       :	       | |
+	       |	       :	       |  > 512 KByte free for use
+  0x00140000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
+	       |	       :	       | /
+  0x00100000 ---15------------8|7-------------0-
+
+
+===============================================================================
+	R E F E R E N C E S
+===============================================================================
+[1]	http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf
+[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
+[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
+[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
+
+
+===============================================================================
+Stephan Linz <linz@li-pro.net>