ram: stm32mp1: Add STM32MP13xx support
Add support for configuring DRAM controller on STM32MP13xx SoC.
The DRAM controller is basically identical to the DWC controller
on STM32MP15xx SoC, except the bus width is reduced from 32bit to
16bit and a few registers and bits are therefore not present.
Handle the difference by factoring these parts out. Use IS_ENABLE()
as much as possible to assure code which is not enabled on builds
for a single SoC gets compiled out. Handle the different offset of
RCC_DDRITFCR register and missing DDRC2 clock the same way.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h
index 861efff..3621e6c 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.h
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h
@@ -105,12 +105,14 @@
u32 pcfgqos1_0;
u32 pcfgwqos0_0;
u32 pcfgwqos1_0;
+#if IS_ENABLED(CONFIG_STM32MP15X)
u32 pcfgr_1;
u32 pcfgw_1;
u32 pcfgqos0_1;
u32 pcfgqos1_1;
u32 pcfgwqos0_1;
u32 pcfgwqos1_1;
+#endif
};
struct stm32mp1_ddrphy_reg {
@@ -123,8 +125,10 @@
u32 zq0cr1;
u32 dx0gcr;
u32 dx1gcr;
+#if IS_ENABLED(CONFIG_STM32MP15X)
u32 dx2gcr;
u32 dx3gcr;
+#endif
};
struct stm32mp1_ddrphy_timing {
@@ -181,4 +185,6 @@
enum stm32mp1_ddr_interact_step step,
const struct stm32mp1_ddr_config *config);
+bool is_stm32mp13_ddrc(const struct ddr_info *priv);
+
#endif