ColdFire: PCI and misc updates for MCF5445x
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Signed-off by: John Rigby <jrigby@freescale.com>
diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index ffb9a37..912753d 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -232,10 +232,10 @@
#define CFG_NUM_IRQS (128)
#ifdef CONFIG_PCI
-#define CFG_PCI_BAR0 CFG_SDRAM_BASE
-#define CFG_PCI_BAR4 CFG_SDRAM_BASE
-#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE)
-#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE)
+#define CFG_PCI_BAR0 (CFG_MBAR)
+#define CFG_PCI_BAR5 (CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR0 (CFG_MBAR)
+#define CFG_PCI_TBATR5 (CFG_SDRAM_BASE)
#endif
#endif /* CONFIG_M54455 */
diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h
index f3bd229..7fcf4ef 100644
--- a/include/asm-m68k/m5445x.h
+++ b/include/asm-m68k/m5445x.h
@@ -1204,13 +1204,13 @@
#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
-#define PCI_TCR1_B5E (0x00002000) /* */
-#define PCI_TCR1_B4E (0x00001000) /* */
-#define PCI_TCR1_B3E (0x00000800) /* */
-#define PCI_TCR1_B2E (0x00000400) /* */
-#define PCI_TCR1_B1E (0x00000200) /* */
-#define PCI_TCR1_B0E (0x00000100) /* */
-#define PCI_TCR1_CR (0x00000001) /* */
+#define PCI_TCR2_B5E (0x00002000) /* */
+#define PCI_TCR2_B4E (0x00001000) /* */
+#define PCI_TCR2_B3E (0x00000800) /* */
+#define PCI_TCR2_B2E (0x00000400) /* */
+#define PCI_TCR2_B1E (0x00000200) /* */
+#define PCI_TCR2_B0E (0x00000100) /* */
+#define PCI_TCR2_CR (0x00000001) /* */
#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20)
#define PCI_TBATR_EN (0x00000001) /* Enable */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 211f11d..581c794 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -176,6 +176,10 @@
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+#define CONFIG_SKIPPCI_HOSTBRIDGE
+
+#define CFG_PCI_CACHE_LINE_SIZE 4
#define CFG_PCI_MEM_BUS 0xA0000000
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
@@ -192,9 +196,7 @@
/* FPGA - Spartan 2 */
/* experiment
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_FPGA CFG_SPARTAN3
#define CONFIG_FPGA_COUNT 1
#define CFG_FPGA_PROG_FEEDBACK
#define CFG_FPGA_CHECK_CTRLC
@@ -286,9 +288,9 @@
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
# define CFG_ENV_SECT_SIZE 0x2000
#else
-# define CFG_FLASH_BASE CFG_FLASH0_BASE
-# define CFG_FLASH0_BASE CFG_CS1_BASE
-# define CFG_FLASH1_BASE CFG_CS0_BASE
+# define CFG_FLASH_BASE CFG_CS0_BASE
+# define CFG_FLASH0_BASE CFG_CS0_BASE
+# define CFG_FLASH1_BASE CFG_CS1_BASE
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
# define CFG_ENV_SECT_SIZE 0x20000
#endif