tree 261ba20afcda83bd9e50ea82f9981eac9b151752
parent d097bd9832a26f571ff8cf43a0835e31cd8d7d16
author York Sun <york.sun@nxp.com> 1463631079 -0700
committer York Sun <york.sun@nxp.com> 1464988326 -0700

drivers/ddr/fsl: Fix timing_cfg_2 register

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.

Signed-off-by: York Sun <york.sun@nxp.com>