| commit | 3a7713d1a12d51de8042be81d1daaa283d09761e | [log] [tgz] |
|---|---|---|
| author | Svyatoslav Ryhel <clamor95@gmail.com> | Mon Mar 24 21:24:45 2025 +0200 |
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | Sat Apr 12 09:42:35 2025 +0300 |
| tree | 5116e34ba4e04b77be20af42e566805569fdb6ca | |
| parent | 7e10c46c17c0058744698329bc6cc4cc77ed27e9 [diff] |
ARM: tegra: clock: take in account PLLD/D2 enable bit on clock_set_rate PLLD and PLLD2 clocks possess a unique enable bit within their miscellaneous register. Take this into account when using clock_set_rate function. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>