ARM: mvebu: a38x: restore support for setting timing
This restores support for configuring the timing mode based on the
ddr_topology. This was originally implemented in commit 90bcc3d38d2b
("driver/ddr: Add support for setting timing in hws_topology_map") but
was removed as part of the upstream sync.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 1f26d50..799c5ba 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -365,6 +365,7 @@
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
enum hws_ddr_freq freq = tm->interface_params[0].memory_freq;
+ enum mv_ddr_timing timing;
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
@@ -603,8 +604,12 @@
DUNIT_CTRL_HIGH_REG,
(init_cntr_prm->msys_init << 7), (1 << 7)));
+ timing = tm->interface_params[if_id].timing;
+
if (mode_2t != 0xff) {
t2t = mode_2t;
+ } else if (timing != MV_DDR_TIM_DEFAULT) {
+ t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
} else {
/* calculate number of CS (per interface) */
CHECK_STATUS(calc_cs_num
@@ -1268,6 +1273,7 @@
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
unsigned int tclk;
+ enum mv_ddr_timing timing = tm->interface_params[if_id].timing;
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("dev %d access %d IF %d freq %d\n", dev_num,
@@ -1410,6 +1416,8 @@
/* Calculate 2T mode */
if (mode_2t != 0xff) {
t2t = mode_2t;
+ } else if (timing != MV_DDR_TIM_DEFAULT) {
+ t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
} else {
/* Calculate number of CS per interface */
CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num));
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 2c589eb..8122249 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -64,6 +64,9 @@
/* operation temperature */
enum mv_ddr_temperature interface_temp;
+
+ /* 2T vs 1T mode (by default computed from number of CSs) */
+ enum mv_ddr_timing timing;
};
struct mv_ddr_topology_map {
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index ce672e9..2070bb3 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -674,11 +674,6 @@
dfs_low_freq = DFS_LOW_FREQ_VALUE;
calibration_update_control = 1;
-#ifdef CONFIG_ARMADA_38X
- /* For a38x only, change to 2T mode to resolve low freq instability */
- mode_2t = 1;
-#endif
-
ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq);
return MV_OK;
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
index eb017a1..7bef2d1 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
@@ -36,6 +36,12 @@
MV_DDR_TEMP_HIGH
};
+enum mv_ddr_timing {
+ MV_DDR_TIM_DEFAULT,
+ MV_DDR_TIM_1T,
+ MV_DDR_TIM_2T
+};
+
enum mv_ddr_timing_data {
MV_DDR_TCK_AVG_MIN, /* sdram min cycle time (t ck avg min) */
MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */