| commit | 60af21bcc3f257239c2e4b6c6e4db9c023ac7658 | [log] [tgz] |
|---|---|---|
| author | Tien Fong Chee <tien.fong.chee@intel.com> | Tue Feb 18 16:34:54 2025 +0800 |
| committer | Tom Rini <trini@konsulko.com> | Tue Feb 25 10:53:48 2025 -0600 |
| tree | 22fd31ba28e39ef170ff177d053413c876b6908b | |
| parent | e2e79dde57086274bab116e0051616c8511357ed [diff] |
arm: dts: agilex5: Add HPS cache coherency unit configuration settings These configuration settings are required to enable cache maintenance and access between initiators and targets. Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>