spi: cadence-qspi: Add disable STIG mode quikrs.
Adding quirk to disable STIG mode since cadence controller has
issue for read/write using the STIG mode. STIG mode is enabled
by default since 2023.04 for small read/write(<8bytes).
Updated STIG mode reading from dev_get_driver_data by assigning
to platdata struct before read quirks variable.
The STIG mode is disabled for normal read case and enabled
for QSPI Jedec ID read/write since it requires STIG read/write.
Porting from linux implementation
https://lore.kernel.org/all/20241204063338.296959-1-niravkumar
.l.rabara@intel.com/T/
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 731b652..80510f2 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -222,6 +222,7 @@
u32 tsd2d_ns;
u32 tchsh_ns;
u32 tslch_ns;
+ u32 quirks;
bool is_dma;
};
@@ -253,6 +254,7 @@
u32 tsd2d_ns;
u32 tchsh_ns;
u32 tslch_ns;
+ u32 quirks;
u8 edge_mode;
u8 dll_mode;
bool extra_dummy;
@@ -268,6 +270,11 @@
bool dtr;
};
+struct cqspi_driver_platdata {
+ u32 hwcaps_mask;
+ u32 quirks;
+};
+
/* Functions call declaration */
void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv);
void cadence_qspi_apb_controller_enable(void *reg_base_addr);