commit 397eba4861f593346e1535548d85a7af7870d356
author Adam Ford <aford173@gmail.com> Tue Aug 08 09:00:27 2017 -0500
committer Tom Rini <trini@konsulko.com> Fri Aug 11 11:34:10 2017 -0400
tree af00ce4243b7ec4ca6bd024573a0769f999d755d
parent fe9ef113f53be0fb7f0ebdfc4150ff3e69851c82

OMAP3: omap3logic: Fix DDR Pin Mux

The 512 MB DDR version of SOM's use CS0 and CS1.  CS1 is not correctly
setup in the pin muxing.  This causes erratic behavior on suspend/resume

This fix has been tested on both 256 and 512 MB DDR versions.

Signed-off-by: Adam Ford <aford173@gmail.com>

board/logicpd/omap3som/omap3logic.c

diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index 7990dd2..f8b9f68 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -320,7 +320,7 @@
 	MUX_VAL(CP(SDRC_DQS2), (IEN  | PTD | DIS | M0)); /*SDRC_DQS2*/
 	MUX_VAL(CP(SDRC_DQS3), (IEN  | PTD | DIS | M0)); /*SDRC_DQS3*/
 	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN  | M0)); /*SDRC_CKE0*/
-	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
+	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/
 
 	MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN  | M0)); /*GPMC_A1*/
 	MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN  | M0)); /*GPMC_A2*/