arm: rmobile: Add support Renesas R8A7740
Renesas R8A7740 is CPU with Cortex-A9.
This supports the basic register definition and GPIO.
Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile
index dd0aede..6554f36 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -30,6 +30,8 @@
COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o
+COBJS-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
+COBJS-$(CONFIG_R8A7740) += pfc-r8a7740.o
COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o
COBJS-$(CONFIG_TMU_TIMER) += $(TOPDIR)/arch/sh/lib/time.o
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c
new file mode 100644
index 0000000..f9b0ab8
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+
+u32 rmobile_get_cpu_type(void)
+{
+ u32 id;
+ u32 type;
+ struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
+
+ id = readl(hpb->cccr);
+ type = (id >> 8) & 0xFF;
+
+ return type;
+}
+
+u32 get_cpu_rev(void)
+{
+ u32 id;
+ u32 rev;
+ struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
+
+ id = readl(hpb->cccr);
+ rev = (id >> 4) & 0xF;
+
+ return rev;
+}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c
index 87287ce..0e2b82e 100644
--- a/arch/arm/cpu/armv7/rmobile/cpu_info.c
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c
@@ -68,6 +68,12 @@
rmobile_get_cpu_rev_integer(),
rmobile_get_cpu_rev_fraction());
break;
+ case 0x40:
+ printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n",
+ rmobile_get_cpu_rev_integer(),
+ rmobile_get_cpu_rev_fraction());
+ break;
+
default:
printf("CPU: Renesas Electronics CPU rev %d.%d\n",
rmobile_get_cpu_rev_integer(),
diff --git a/arch/arm/include/asm/arch-rmobile/irqs.h b/arch/arm/include/asm/arch-rmobile/irqs.h
new file mode 100644
index 0000000..dcb714f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/irqs.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_MACH_IRQS_H
+#define __ASM_MACH_IRQS_H
+
+#define NR_IRQS 1024
+
+/* GIC */
+#define gic_spi(nr) ((nr) + 32)
+
+/* INTCA */
+#define evt2irq(evt) (((evt) >> 5) - 16)
+#define irq2evt(irq) (((irq) + 16) << 5)
+
+/* INTCS */
+#define INTCS_VECT_BASE 0x2200
+#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
+#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
+
+#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740.h b/arch/arm/include/asm/arch-rmobile/r8a7740.h
new file mode 100644
index 0000000..8f17950
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/r8a7740.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_R8A7740_H
+#define __ASM_ARCH_R8A7740_H
+
+/*
+ * R8A7740 I/O Addresses
+ */
+
+#define MERAM_BASE 0xE5580000
+#define DDRP_BASE 0xC12A0000
+#define HPB_BASE 0xE6000000
+#define RWDT0_BASE 0xE6020000
+#define RWDT1_BASE 0xE6030000
+#define GPIO_BASE 0xE6050000
+#define CMT1_BASE 0xE6138000
+#define CPG_BASE 0xE6150000
+#define SYSC_BASE 0xE6180000
+#define SDHI0_BASE 0xE6850000
+#define SDHI1_BASE 0xE6860000
+#define MMCIF_BASE 0xE6BD0000
+#define SCIF5_BASE 0xE6CB0000
+#define SCIF6_BASE 0xE6CC0000
+#define DBSC_BASE 0xFE400000
+#define BSC_BASE 0xFEC10000
+#define I2C0_BASE 0xFFF20000
+#define I2C1_BASE 0xE6C20000
+#define TMU_BASE 0xFFF80000
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct r8a7740_rwdt {
+ u16 rwtcnt0; /* 0x00 */
+ u16 dummy0; /* 0x02 */
+ u16 rwtcsra0; /* 0x04 */
+ u16 dummy1; /* 0x06 */
+ u16 rwtcsrb0; /* 0x08 */
+ u16 dummy2; /* 0x0A */
+};
+
+/* HPB Semaphore Control Registers */
+struct r8a7740_hpb {
+ u32 hpbctrl0;
+ u32 hpbctrl1;
+ u32 hpbctrl2;
+ u32 cccr;
+ u32 dummy0; /* 0x20 */
+ u32 hpbctrl4;
+ u32 hpbctrl5;
+};
+
+/* CPG */
+struct r8a7740_cpg {
+ u32 frqcra;
+ u32 frqcrb;
+ u32 vclkcr1;
+ u32 vclkcr2;
+ u32 fmsickcr;
+ u32 fmsockcr;
+ u32 fsiackcr;
+ u32 dummy0; /* 0x1c */
+ u32 rtstbcr;
+ u32 systbcr;
+ u32 pllc01cr;
+ u32 pllc2cr;
+ u32 mstpsr0;
+ u32 dummy1; /* 0x34 */
+ u32 mstpsr1;
+ u32 mstpsr5;
+ u32 mstpsr2;
+ u32 dummy2; /* 0x44 */
+ u32 mstpsr3;
+ u32 mstpsr4;
+ u32 dummy3; /* 0x50 */
+ u32 astat;
+ u32 dummy4[4]; /* 0x58 .. 0x64 */
+ u32 ztrckcr;
+ u32 dummy5[5]; /* 0x6c .. 0x7c */
+ u32 subckcr;
+ u32 spuckcr;
+ u32 vouckcr;
+ u32 usbckcr;
+ u32 dummy6[3]; /* 0x90 .. 0x98 */
+ u32 stprckcr;
+ u32 srcr0;
+ u32 dummy7; /* 0xa4 */
+ u32 srcr1;
+ u32 dummy8; /* 0xac */
+ u32 srcr2;
+ u32 dummy9; /* 0xb4 */
+ u32 srcr3;
+ u32 srcr4;
+ u32 dummy10; /* 0xc0 */
+ u32 srcr5;
+ u32 pllc01stpcr;
+ u32 dummy11[5]; /* 0xcc .. 0xdc */
+ u32 frqcrc;
+ u32 frqcrd;
+ u32 dummy12[10]; /* 0xe8 .. 0x10c */
+ u32 rmstpcr0;
+ u32 rmstpcr1;
+ u32 rmstpcr2;
+ u32 rmstpcr3;
+ u32 rmstpcr4;
+ u32 rmstpcr5;
+ u32 dummy13[2]; /* 0x128 .. 0x12c */
+ u32 smstpcr0;
+ u32 smstpcr1;
+ u32 smstpcr2;
+ u32 smstpcr3;
+ u32 smstpcr4;
+ u32 smstpcr5;
+};
+
+/* BSC */
+struct r8a7740_bsc {
+ u32 cmncr;
+ u32 cs0bcr;
+ u32 cs2bcr;
+ u32 dummy0; /* 0x0c */
+ u32 cs4bcr;
+ u32 cs5abcr;
+ u32 cs5bbcr;
+ u32 cs6abcr;
+ u32 dummy1; /* 0x20 */
+ u32 cs0wcr;
+ u32 cs2wcr;
+ u32 dummy2; /* 0x2c */
+ u32 cs4wcr;
+ u32 cs5awcr;
+ u32 cs5bwcr;
+ u32 cs6awcr;
+ u32 dummy3[5]; /* 0x40 .. 0x50 */
+ u32 rbwtcnt;
+ u32 busycr;
+ u32 dummy4[5]; /* 0x5c .. 0x6c */
+ u32 bromtimcr;
+ u32 dummy5[7]; /* 0x74 .. 0x8c */
+ u32 bptcr00;
+ u32 bptcr01;
+ u32 bptcr02;
+ u32 bptcr03;
+ u32 bptcr04;
+ u32 bptcr05;
+ u32 bptcr06;
+ u32 bptcr07;
+ u32 bptcr08;
+ u32 bptcr09;
+ u32 bptcr10;
+ u32 bptcr11;
+ u32 bptcr12;
+ u32 bptcr13;
+ u32 bptcr14;
+ u32 bptcr15;
+ u32 bptcr16;
+ u32 bptcr17;
+ u32 bptcr18;
+ u32 bptcr19;
+ u32 bptcr20;
+ u32 bptcr21;
+ u32 bptcr22;
+ u32 bptcr23;
+ u32 bptcr24;
+ u32 bptcr25;
+ u32 bptcr26;
+ u32 bptcr27;
+ u32 bptcr28;
+ u32 bptcr29;
+ u32 bptcr30;
+ u32 bptcr31;
+ u32 bswcr;
+ u32 dummy6[68]; /* 0x114 .. 0x220 */
+ u32 cs0wcr2;
+ u32 cs2wcr2;
+ u32 dummy7; /* 0x22c */
+ u32 cs4wcr2;
+};
+
+#define CS0WCR2 0xFEC10224
+#define CS2WCR2 0xFEC10228
+#define CS4WCR2 0xFEC10230
+
+/* DDRP */
+struct r8a7740_ddrp {
+ u32 funcctrl;
+ u32 dllctrl;
+ u32 zqcalctrl;
+ u32 zqodtctrl;
+ u32 rdctrl;
+ u32 rdtmg;
+ u32 fifoinit;
+ u32 outctrl;
+ u32 dummy0[50]; /* 0x20 .. 0xe4 */
+ u32 dqcalofs1;
+ u32 dqcalofs2;
+ u32 dummy1[2]; /* 0xf0 .. 0xf4 */
+ u32 dqcalexp;
+};
+
+#define DDRPNCNT 0xE605803C
+#define DDRVREFCNT 0xE61500EC
+
+/* DBSC */
+struct r8a7740_dbsc {
+ u32 dummy0;
+ u32 dbsvcr;
+ u32 dbstate0;
+ u32 dbstate1;
+ u32 dbacen;
+ u32 dbrfen;
+ u32 dbcmd;
+ u32 dbwait;
+ u32 dbkind;
+ u32 dbconf0;
+ u32 dummy1[2]; /* 0x28 .. 0x2c */
+ u32 dbphytype;
+ u32 dummy2[3]; /* 0x34 .. 0x3c */
+ u32 dbtr0;
+ u32 dbtr1;
+ u32 dbtr2;
+ u32 dummy3; /* 0x4c */
+ u32 dbtr3;
+ u32 dbtr4;
+ u32 dbtr5;
+ u32 dbtr6;
+ u32 dbtr7;
+ u32 dbtr8;
+ u32 dbtr9;
+ u32 dbtr10;
+ u32 dbtr11;
+ u32 dbtr12;
+ u32 dbtr13;
+ u32 dbtr14;
+ u32 dbtr15;
+ u32 dbtr16;
+ u32 dbtr17;
+ u32 dbtr18;
+ u32 dbtr19;
+ u32 dummy4[7]; /* 0x94 .. 0xac */
+ u32 dbbl;
+ u32 dummy5[3]; /* 0xb4 .. 0xbc */
+ u32 dbadj0;
+ u32 dbadj1;
+ u32 dbadj2;
+ u32 dummy6[5]; /* 0xcc .. 0xdc */
+ u32 dbrfcnf0;
+ u32 dbrfcnf1;
+ u32 dbrfcnf2;
+ u32 dbrfcnf3;
+ u32 dummy7; /* 0xf0 */
+ u32 dbcalcnf;
+ u32 dbcaltr;
+ u32 dummy8; /* 0xfc */;
+ u32 dbrnk0;
+ u32 dummy9[31]; /* 0x104 .. 0x17C */
+ u32 dbpdncnf;
+ u32 dummy10[7]; /* 0x184 .. 0x19C */
+ u32 dbmrrdr;
+ u32 dummy11[39]; /* 0x1A4 .. 0x23C */
+ u32 dbdfistat;
+ u32 dbdficnt;
+ u32 dummy12[46]; /* 0x248 .. 0x2FC */
+ u32 dbbs0cnt0;
+ u32 dbbs0cnt1;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_R8A7740_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h
index a3468e9..ac17561 100644
--- a/arch/arm/include/asm/arch-rmobile/rmobile.h
+++ b/arch/arm/include/asm/arch-rmobile/rmobile.h
@@ -4,6 +4,8 @@
#if defined(CONFIG_RMOBILE)
#if defined(CONFIG_SH73A0)
#include <asm/arch/sh73a0.h>
+#elif defined(CONFIG_R8A7740)
+#include <asm/arch/r8a7740.h>
#else
#error "SOC Name not defined"
#endif