tree 1690d31ee59b2bbc8e6d5db326aac3c06bc43a6b
parent ed41367f45e6048ed27fec121d51cd123d36226b
author Roy Zang <tie-fei.zang@freescale.com> 1294380407 -0600
committer Kumar Gala <galak@kernel.crashing.org> 1294990342 -0600

fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)

The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.

Clear these bits out when we read HOSTCAPBLT.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>