net: gmac_rockchip: Add RMII support for rk3288
Add RMII-specific handling to rk3288_gmac_fix_mac_speed() so that it
properly sets the RMII clock (2.5 MHz vs. 25 MHz) and speed bits
(10 Mbps vs. 100 Mbps). Also define a new rk3288_gmac_set_to_rmii()
function to set the PHY interface field and RMII_MODE bit.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 8cfeeff..c8cfe74 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -151,26 +151,51 @@
static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
+ struct dw_eth_pdata *dw_pdata = dev_get_plat(priv->dev);
+ struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
struct rk3288_grf *grf;
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
int clk;
- switch (priv->phydev->speed) {
- case 10:
- clk = RK3288_GMAC_CLK_SEL_2_5M;
- break;
- case 100:
- clk = RK3288_GMAC_CLK_SEL_25M;
- break;
- case 1000:
- clk = RK3288_GMAC_CLK_SEL_125M;
- break;
- default:
- debug("Unknown phy speed: %d\n", priv->phydev->speed);
- return -EINVAL;
- }
+ if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
+ switch (priv->phydev->speed) {
+ case 10:
+ rk_clrsetreg(&grf->soc_con1,
+ RK3288_RMII_CLK_SEL_MASK |
+ RK3288_GMAC_SPEED_MASK,
+ RK3288_RMII_CLK_SEL_2_5M |
+ RK3288_GMAC_SPEED_10M);
+ break;
+ case 100:
+ rk_clrsetreg(&grf->soc_con1,
+ RK3288_RMII_CLK_SEL_MASK |
+ RK3288_GMAC_SPEED_MASK,
+ RK3288_RMII_CLK_SEL_25M |
+ RK3288_GMAC_SPEED_100M);
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+ } else {
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3288_GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = RK3288_GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = RK3288_GMAC_CLK_SEL_125M;
+ break;
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
+ }
return 0;
}
@@ -401,6 +426,17 @@
pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rk3288_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
+{
+ struct rk3288_grf *grf;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ rk_clrsetreg(&grf->soc_con1,
+ RK3288_GMAC_PHY_INTF_SEL_MASK | RK3288_RMII_MODE_MASK,
+ RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_RMII_MODE);
+}
+
static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk3288_grf *grf;
@@ -703,6 +739,7 @@
const struct rk_gmac_ops rk3288_gmac_ops = {
.fix_mac_speed = rk3288_gmac_fix_mac_speed,
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
+ .set_to_rmii = rk3288_gmac_set_to_rmii,
};
const struct rk_gmac_ops rk3308_gmac_ops = {