tree 2bca892c4f617a13727cfec6d6389a7e2b9e83ec
parent 3dacc678386a936ff9a1be8b95ad57631b8641f4
author Axel Lin <axel.lin@ingics.com> 1420502905 +0800
committer Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> 1420539747 +0530

spi: designware_spi: Fix detecting FIFO depth

Current code tries to find the highest valid fifo depth by checking the value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws->fifo_len setting because it assumes the latest
   register write fails so the latest valid value should be fifo - 1.
2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary
   to test fifo == 257. In the case fifo is 257, it means the latest valid
   setting is fifo = 256. So after the for loop iteration, we should check
   fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails.
This patch fixes above issues.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>