usb: 64-bit architectures support for xHCI
This commit allows xHCI to use both 64 and 32 bit memory
physical addresses depending on architecture it's being built for.
Also it makes use of readq()/writeq() on 64-bit systems
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index b5aade9..f3759d4 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -122,8 +122,8 @@
next->link.control |= cpu_to_le32(chain);
next->link.control ^= cpu_to_le32(TRB_CYCLE);
- xhci_flush_cache((uint32_t)next,
- sizeof(union xhci_trb));
+ xhci_flush_cache((uintptr_t)next,
+ sizeof(union xhci_trb));
}
/* Toggle the cycle bit after the last ring segment. */
if (last_trb_on_last_seg(ctrl, ring,
@@ -191,7 +191,7 @@
for (i = 0; i < 4; i++)
trb->field[i] = cpu_to_le32(trb_fields[i]);
- xhci_flush_cache((uint32_t)trb, sizeof(struct xhci_generic_trb));
+ xhci_flush_cache((uintptr_t)trb, sizeof(struct xhci_generic_trb));
inc_enq(ctrl, ring, more_trbs_coming);
@@ -244,7 +244,7 @@
next->link.control ^= cpu_to_le32(TRB_CYCLE);
- xhci_flush_cache((uint32_t)next, sizeof(union xhci_trb));
+ xhci_flush_cache((uintptr_t)next, sizeof(union xhci_trb));
/* Toggle the cycle bit after the last ring segment. */
if (last_trb_on_last_seg(ctrl, ep_ring,
@@ -364,7 +364,7 @@
else
start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
- xhci_flush_cache((uint32_t)start_trb, sizeof(struct xhci_generic_trb));
+ xhci_flush_cache((uintptr_t)start_trb, sizeof(struct xhci_generic_trb));
/* Ringing EP doorbell here */
xhci_writel(&ctrl->dba->doorbell[udev->slot_id],
@@ -403,8 +403,8 @@
{
union xhci_trb *event;
- xhci_inval_cache((uint32_t)ctrl->event_ring->dequeue,
- sizeof(union xhci_trb));
+ xhci_inval_cache((uintptr_t)ctrl->event_ring->dequeue,
+ sizeof(union xhci_trb));
event = ctrl->event_ring->dequeue;
@@ -576,8 +576,8 @@
ep_index = usb_pipe_ep_index(pipe);
virt_dev = ctrl->devs[slot_id];
- xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes,
- virt_dev->out_ctx->size);
+ xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
+ virt_dev->out_ctx->size);
ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index);
@@ -644,7 +644,7 @@
first_trb = true;
/* flush the buffer before use */
- xhci_flush_cache((uint32_t)buffer, length);
+ xhci_flush_cache((uintptr_t)buffer, length);
/* Queue the first TRB, even if it's zero-length */
do {
@@ -722,7 +722,7 @@
record_transfer_result(udev, event, length);
xhci_acknowledge_event(ctrl);
- xhci_inval_cache((uint32_t)buffer, length);
+ xhci_inval_cache((uintptr_t)buffer, length);
return (udev->status != USB_ST_NOT_PROC) ? 0 : -1;
}
@@ -776,8 +776,8 @@
return ret;
}
- xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes,
- virt_dev->out_ctx->size);
+ xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
+ virt_dev->out_ctx->size);
struct xhci_ep_ctx *ep_ctx = NULL;
ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index);
@@ -874,7 +874,7 @@
trb_fields[2] = length_field;
trb_fields[3] = field | ep_ring->cycle_state;
- xhci_flush_cache((uint32_t)buffer, length);
+ xhci_flush_cache((uintptr_t)buffer, length);
queue_trb(ctrl, ep_ring, true, trb_fields);
}
@@ -915,7 +915,7 @@
/* Invalidate buffer to make it available to usb-core */
if (length > 0)
- xhci_inval_cache((uint32_t)buffer, length);
+ xhci_inval_cache((uintptr_t)buffer, length);
if (GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len))
== COMP_SHORT_TX) {