tree d3125ad2d838363ae8b4eb617a38620f19c6e12c
parent 7e0edbd874be10824538d055e9ee7604221435cf
author York Sun <yorksun@freescale.com> 1349682256 +0000
committer Andy Fleming <afleming@freescale.com> 1350934280 -0500

powerpc/corenet2: fix mismatch DDR sync bit from RCW

Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>