* Patch by Nicolas Lacressonniere, 11 Jun 2003:
Modifications for Atmel AT91RM9200DK ARM920T based development kit
- Add Atmel DataFlash support for reading and writing.
- Add possibility to boot a Linux from DataFlash with BOOTM command.
- Add Flash detection on Atmel AT91RM9200DK
(between Atmel AT49BV1614 and AT49BV1614A flashes)
- Replace old Ethernet PHY layer functions
- Change link address
* Patch by Frank Smith, 9 Jun 2003:
use CRIT_EXCEPTION for machine check on 4xx
* Patch by Detlev Zundel, 13 Jun 2003:
added implementation of the "carinfo" command in cmd_immap.c
diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
index 8f93c12..c0e5211 100644
--- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h
+++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
@@ -1,15 +1,27 @@
-/* ---------------------------------------------------------------------------- */
-/* ATMEL Microcontroller Software Support - ROUSSET - */
-/* ---------------------------------------------------------------------------- */
-/* The software is delivered "AS IS" without warranty or condition of any */
-/* kind, either express, implied or statutory. This includes without */
-/* limitation any warranty or condition with respect to merchantability or */
-/* fitness for any particular purpose, or against the infringements of */
-/* intellectual property rights of others. */
-/* ---------------------------------------------------------------------------- */
-/* File Name : AT91RM9200.h */
-/* Object : AT91RM9200 definitions */
-/* Generated : AT91 SW Application Group 10/29/2002 (16:10:51) */
+/*
+ * (C) Copyright 2003
+ * AT91RM9200 definitions
+ * Author : ATMEL AT91 application group
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
#ifndef AT91RM9200_H
#define AT91RM9200_H
@@ -32,6 +44,21 @@
AT91_REG TC_IMR; /* Interrupt Mask Register */
} AT91S_TC, *AT91PS_TC;
+#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
+#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
+#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
+#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
+#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
+#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
+#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
+#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
+
/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Usart */
/* ***************************************************************************** */
@@ -137,6 +164,32 @@
AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
} AT91S_DBGU, *AT91PS_DBGU;
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
+
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */
+
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
@@ -146,6 +199,28 @@
} AT91S_SMC2, *AT91PS_SMC2;
/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Power Management Controler */
+/* ******************************************************************************/
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; /* System Clock Enable Register */
+ AT91_REG PMC_SCDR; /* System Clock Disable Register */
+ AT91_REG PMC_SCSR; /* System Clock Status Register */
+ AT91_REG Reserved0[1]; /* */
+ AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
+ AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
+ AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
+ AT91_REG Reserved1[5]; /* */
+ AT91_REG PMC_MCKR; /* Master Clock Register */
+ AT91_REG Reserved2[3]; /* */
+ AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */
+ AT91_REG PMC_IER; /* Interrupt Enable Register */
+ AT91_REG PMC_IDR; /* Interrupt Disable Register */
+ AT91_REG PMC_SR; /* Status Register */
+ AT91_REG PMC_IMR; /* Interrupt Mask Register */
+} AT91S_PMC, *AT91PS_PMC;
+
+
+/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Ethernet MAC */
/* ***************************************************************************** */
typedef struct _AT91S_EMAC {
@@ -194,35 +269,185 @@
AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */
} AT91S_EMAC, *AT91PS_EMAC;
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
+/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
+#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */
+#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */
+#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */
+#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */
+/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */
+#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */
+/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */
+/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
+#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */
+#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */
+#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */
+#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */
+#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */
+#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */
+#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */
+#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */
+#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */
+#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */
+#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */
+#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */
+#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */
+#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */
+#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */
+#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; /* Control Register */
+ AT91_REG SPI_MR; /* Mode Register */
+ AT91_REG SPI_RDR; /* Receive Data Register */
+ AT91_REG SPI_TDR; /* Transmit Data Register */
+ AT91_REG SPI_SR; /* Status Register */
+ AT91_REG SPI_IER; /* Interrupt Enable Register */
+ AT91_REG SPI_IDR; /* Interrupt Disable Register */
+ AT91_REG SPI_IMR; /* Interrupt Mask Register */
+ AT91_REG Reserved0[4]; /* */
+ AT91_REG SPI_CSR[4]; /* Chip Select Register */
+ AT91_REG Reserved1[48]; /* */
+ AT91_REG SPI_RPR; /* Receive Pointer Register */
+ AT91_REG SPI_RCR; /* Receive Counter Register */
+ AT91_REG SPI_TPR; /* Transmit Pointer Register */
+ AT91_REG SPI_TCR; /* Transmit Counter Register */
+ AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
+ AT91_REG SPI_RNCR; /* Receive Next Counter Register */
+ AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
+ AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
+ AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
+ AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
+} AT91S_SPI, *AT91PS_SPI;
+
+/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */
+/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */
+#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
+/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */
+#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
+/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; /* Receive Pointer Register */
+ AT91_REG PDC_RCR; /* Receive Counter Register */
+ AT91_REG PDC_TPR; /* Transmit Pointer Register */
+ AT91_REG PDC_TCR; /* Transmit Counter Register */
+ AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
+ AT91_REG PDC_RNCR; /* Receive Next Counter Register */
+ AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
+ AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
+ AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
+ AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
+} AT91S_PDC, *AT91PS_PDC;
-#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */
-#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */
-#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
-#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
+/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */
+/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
+/* ========== Register definition ==================================== */
+#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */
#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */
+
#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */
#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */
#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */
@@ -233,6 +458,7 @@
#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */
#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */
#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */
+#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */
#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */
#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */
@@ -242,38 +468,25 @@
#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */
#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */
-#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
-#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
-#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
-#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
-#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
-#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
-#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
-#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
-#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
-#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
-#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */
+#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */
+
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */
+#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */
+#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */
+#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */
+#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */
+#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */
+#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */
+#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */
-#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */
-#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */
-#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */
-#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */
-#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */
-#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
-#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 0) /* (EMAC) */
-#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */
+
#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */
#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */
#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */
@@ -294,6 +507,8 @@
#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
+
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
@@ -323,7 +538,6 @@
#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */
#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */
-#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
@@ -335,8 +549,12 @@
#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */
#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */
+#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
@@ -349,4 +567,5 @@
#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */
#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */
#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */
+
#endif
diff --git a/include/at91rm9200_net.h b/include/at91rm9200_net.h
new file mode 100644
index 0000000..e41fe3c
--- /dev/null
+++ b/include/at91rm9200_net.h
@@ -0,0 +1,59 @@
+/*
+ * Ethernet: An implementation of the Ethernet Device Driver suite for the
+ * uClinux 2.0.38 operating system. This Driver has been developed
+ * for AT75C220 board.
+ *
+ * NOTE: The driver is implemented for one MAC
+ *
+ * Version: @(#)at91rm9200_net.h 1.0.0 01/10/2001
+ *
+ * Authors: Lineo Inc <www.lineo.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_ETHERNET
+#define AT91RM9200_ETHERNET
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include "dm9161.h"
+
+#define FALSE 0
+#define TRUE 1
+
+
+#define ETHERNET_ADDRESS_SIZE 6
+
+typedef unsigned char UCHAR;
+
+/* Interface to drive the physical layer */
+typedef struct _AT91S_PhyOps
+{
+ unsigned char (*Init)(AT91S_EMAC *pmac);
+ unsigned int (*IsPhyConnected)(AT91S_EMAC *pmac);
+ unsigned char (*GetLinkSpeed)(AT91S_EMAC *pmac);
+ unsigned char (*AutoNegotiate)(AT91S_EMAC *pmac, int *);
+
+} AT91S_PhyOps,*AT91PS_PhyOps;
+
+
+#define EMAC_DESC_DONE 0x00000001 /* ownership bit */
+#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */
+
+/****************** function prototypes **********************/
+
+/* MII functions */
+static void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac);
+static void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
+static UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
+static UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
+void at91rm92000_GetPhyInterface(void );
+
+#endif /* AT91RM9200_ETHERNET */
+
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 6315f0a..e382977 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -28,12 +28,14 @@
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
+/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
-#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
+#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
+
/*
* Size of malloc() pool
*/
@@ -42,25 +44,24 @@
/*
* Hardware drivers
*/
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL3 1 /* we use SERIAL 3 */
#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
+#define CONFIG_BOOTDELAY 3
+/* #define CONFIG_ENV_OVERWRITE 1 */
+
#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_NAND )
-/* CFG_CMD_EEPROM | \ might consider these
- CFG_CMD_I2C | \
- CFG_CMD_USB | \
- CFG_CMD_MII | \
- CFG_CMD_SDRAM | \ */
+ ((CONFIG_CMD_DFL | \
+ CFG_CMD_DHCP ) & \
+ ~(CFG_CMD_BDI | \
+ CFG_CMD_IMI | \
+ CFG_CMD_AUTOSCRIPT | \
+ CFG_CMD_FPGA | \
+ CFG_CMD_MISC | \
+ CFG_CMD_LOADS ))
+
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@@ -101,6 +102,14 @@
#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT 20
+
+#define CONFIG_HAS_DATAFLASH 1
+#define CFG_SPI_WRITE_TOUT CFG_HZ
+#define CFG_MAX_DATAFLASH_BANKS 2
+#define CFG_MAX_DATAFLASH_PAGES 16384
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
+#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
#define PHYS_FLASH_1 0x10000000
#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
@@ -110,10 +119,14 @@
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000)
-#define CFG_ENV_SIZE 0x2000
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* 0x10000 */
+#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
#define CFG_LOAD_ADDR 0x21000000 /* default load address */
+#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
+#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
+#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
+
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CFG_PROMPT "Uboot> " /* Monitor Command Prompt */
diff --git a/include/dataflash.h b/include/dataflash.h
new file mode 100644
index 0000000..cc4badf
--- /dev/null
+++ b/include/dataflash.h
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2003
+ * Data Flash Atmel Description File
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* File Name : dataflash.h */
+/* Object : Data Flash Atmel Description File */
+/* Translator : */
+/* */
+/* 1.0 03/04/01 HI : Creation */
+/* 1.2 20/10/02 FB : Adapatation Service and Lib v3 */
+/*----------------------------------------------------------------------*/
+
+#ifndef _DataFlash_h
+#define _DataFlash_h
+
+
+#include <asm/arch/hardware.h>
+#include "config.h"
+
+
+typedef struct {
+ unsigned long base; /* logical base address for a bank */
+ unsigned long size; /* total bank size */
+ unsigned long page_count;
+ unsigned long page_size;
+ unsigned long id; /* device id */
+ unsigned char protect[CFG_MAX_DATAFLASH_PAGES]; /* page protection status */
+} dataflash_info_t;
+
+
+typedef unsigned int AT91S_DataFlashStatus;
+
+/*----------------------------------------------------------------------*/
+/* DataFlash Structures */
+/*----------------------------------------------------------------------*/
+
+/*---------------------------------------------*/
+/* DataFlash Descriptor Structure Definition */
+/*---------------------------------------------*/
+typedef struct _AT91S_DataflashDesc {
+ unsigned char *tx_cmd_pt;
+ unsigned int tx_cmd_size;
+ unsigned char *rx_cmd_pt;
+ unsigned int rx_cmd_size;
+ unsigned char *tx_data_pt;
+ unsigned int tx_data_size;
+ unsigned char *rx_data_pt;
+ unsigned int rx_data_size;
+ volatile unsigned char state;
+ volatile unsigned char DataFlash_state;
+ unsigned char command[8];
+} AT91S_DataflashDesc, *AT91PS_DataflashDesc;
+
+/*---------------------------------------------*/
+/* DataFlash device definition structure */
+/*---------------------------------------------*/
+typedef struct _AT91S_Dataflash {
+ int pages_number; /* dataflash page number */
+ int pages_size; /* dataflash page size */
+ int page_offset; /* page offset in command */
+ int byte_mask; /* byte mask in command */
+ int cs;
+} AT91S_DataflashFeatures, *AT91PS_DataflashFeatures;
+
+/*---------------------------------------------*/
+/* DataFlash Structure Definition */
+/*---------------------------------------------*/
+typedef struct _AT91S_DataFlash {
+ AT91PS_DataflashDesc pDataFlashDesc; /* dataflash descriptor */
+ AT91PS_DataflashFeatures pDevice; /* Pointer on a dataflash features array */
+} AT91S_DataFlash, *AT91PS_DataFlash;
+
+
+
+typedef struct _AT91S_DATAFLASH_INFO {
+
+ AT91S_DataflashDesc Desc;
+ AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */
+ unsigned long logical_address;
+ unsigned int id; /* device id */
+ unsigned char protect[CFG_MAX_DATAFLASH_PAGES]; /* page protection status */
+} AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO;
+
+
+/*-------------------------------------------------------------------------------------------------*/
+
+#define AT45DB161 0x2c
+#define AT45DB321 0x34
+#define AT45DB642 0x3c
+
+#define AT91C_DATAFLASH_TIMEOUT 10000 /* For AT91F_DataFlashWaitReady */
+
+/* DataFlash return value */
+#define DATAFLASH_BUSY 0x00
+#define DATAFLASH_OK 0x01
+#define DATAFLASH_ERROR 0x02
+#define DATAFLASH_MEMORY_OVERFLOW 0x03
+#define DATAFLASH_BAD_COMMAND 0x04
+#define DATAFLASH_BAD_ADDRESS 0x05
+
+
+/* Driver State */
+#define IDLE 0x0
+#define BUSY 0x1
+#define ERROR 0x2
+
+/* DataFlash Driver State */
+#define GET_STATUS 0x0F
+
+/*-------------------------------------------------------------------------------------------------*/
+/* Command Definition */
+/*-------------------------------------------------------------------------------------------------*/
+
+/* READ COMMANDS */
+#define DB_CONTINUOUS_ARRAY_READ 0xE8 /* Continuous array read */
+#define DB_BURST_ARRAY_READ 0xE8 /* Burst array read */
+#define DB_PAGE_READ 0xD2 /* Main memory page read */
+#define DB_BUF1_READ 0xD4 /* Buffer 1 read */
+#define DB_BUF2_READ 0xD6 /* Buffer 2 read */
+#define DB_STATUS 0xD7 /* Status Register */
+
+/* PROGRAM and ERASE COMMANDS */
+#define DB_BUF1_WRITE 0x84 /* Buffer 1 write */
+#define DB_BUF2_WRITE 0x87 /* Buffer 2 write */
+#define DB_BUF1_PAGE_ERASE_PGM 0x83 /* Buffer 1 to main memory page program with built-In erase */
+#define DB_BUF1_PAGE_ERASE_FASTPGM 0x93 /* Buffer 1 to main memory page program with built-In erase, Fast program */
+#define DB_BUF2_PAGE_ERASE_PGM 0x86 /* Buffer 2 to main memory page program with built-In erase */
+#define DB_BUF2_PAGE_ERASE_FASTPGM 0x96 /* Buffer 1 to main memory page program with built-In erase, Fast program */
+#define DB_BUF1_PAGE_PGM 0x88 /* Buffer 1 to main memory page program without built-In erase */
+#define DB_BUF1_PAGE_FASTPGM 0x98 /* Buffer 1 to main memory page program without built-In erase, Fast program */
+#define DB_BUF2_PAGE_PGM 0x89 /* Buffer 2 to main memory page program without built-In erase */
+#define DB_BUF2_PAGE_FASTPGM 0x99 /* Buffer 1 to main memory page program without built-In erase, Fast program */
+#define DB_PAGE_ERASE 0x81 /* Page Erase */
+#define DB_BLOCK_ERASE 0x50 /* Block Erase */
+#define DB_PAGE_PGM_BUF1 0x82 /* Main memory page through buffer 1 */
+#define DB_PAGE_FASTPGM_BUF1 0x92 /* Main memory page through buffer 1, Fast program */
+#define DB_PAGE_PGM_BUF2 0x85 /* Main memory page through buffer 2 */
+#define DB_PAGE_FastPGM_BUF2 0x95 /* Main memory page through buffer 2, Fast program */
+
+/* ADDITIONAL COMMANDS */
+#define DB_PAGE_2_BUF1_TRF 0x53 /* Main memory page to buffer 1 transfert */
+#define DB_PAGE_2_BUF2_TRF 0x55 /* Main memory page to buffer 2 transfert */
+#define DB_PAGE_2_BUF1_CMP 0x60 /* Main memory page to buffer 1 compare */
+#define DB_PAGE_2_BUF2_CMP 0x61 /* Main memory page to buffer 2 compare */
+#define DB_AUTO_PAGE_PGM_BUF1 0x58 /* Auto page rewrite throught buffer 1 */
+#define DB_AUTO_PAGE_PGM_BUF2 0x59 /* Auto page rewrite throught buffer 2 */
+
+/*-------------------------------------------------------------------------------------------------*/
+
+extern int addr_dataflash (unsigned long addr);
+extern int read_dataflash (unsigned long addr, unsigned long size, char *result);
+extern int write_dataflash (unsigned long addr, unsigned long dest, unsigned long size);
+extern void dataflash_print_info (void);
+extern void dataflash_perror (int err);
+
+#endif
diff --git a/include/dm9161.h b/include/dm9161.h
new file mode 100644
index 0000000..6299921
--- /dev/null
+++ b/include/dm9161.h
@@ -0,0 +1,130 @@
+/*
+ * NOTE: DAVICOM ethernet Physical layer
+ *
+ * Version: @(#)DM9161.h 1.0.0 01/10/2001
+ *
+ * Authors: ATMEL Rousset
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+
+// DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161
+
+#define DM9161_BMCR 0 // Basic Mode Control Register
+#define DM9161_BMSR 1 // Basic Mode Status Register
+#define DM9161_PHYID1 2 // PHY Idendifier Register 1
+#define DM9161_PHYID2 3 // PHY Idendifier Register 2
+#define DM9161_ANAR 4 // Auto_Negotiation Advertisement Register
+#define DM9161_ANLPAR 5 // Auto_negotiation Link Partner Ability Register
+#define DM9161_ANER 6 // Auto-negotiation Expansion Register
+#define DM9161_DSCR 16 // Specified Configuration Register
+#define DM9161_DSCSR 17 // Specified Configuration and Status Register
+#define DM9161_10BTCSR 18 // 10BASE-T Configuration and Satus Register
+#define DM9161_MDINTR 21 // Specified Interrupt Register
+#define DM9161_RECR 22 // Specified Receive Error Counter Register
+#define DM9161_DISCR 23 // Specified Disconnect Counter Register
+#define DM9161_RLSR 24 // Hardware Reset Latch State Register
+
+
+// --Bit definitions: DM9161_BMCR
+#define DM9161_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
+#define DM9161_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
+#define DM9161_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps
+#define DM9161_AUTONEG (1 << 12)
+#define DM9161_POWER_DOWN (1 << 11)
+#define DM9161_ISOLATE (1 << 10)
+#define DM9161_RESTART_AUTONEG (1 << 9)
+#define DM9161_DUPLEX_MODE (1 << 8)
+#define DM9161_COLLISION_TEST (1 << 7)
+
+//--Bit definitions: DM9161_BMSR
+#define DM9161_100BASE_T4 (1 << 15)
+#define DM9161_100BASE_TX_FD (1 << 14)
+#define DM9161_100BASE_T4_HD (1 << 13)
+#define DM9161_10BASE_T_FD (1 << 12)
+#define DM9161_10BASE_T_HD (1 << 11)
+#define DM9161_MF_PREAMB_SUPPR (1 << 6)
+#define DM9161_AUTONEG_COMP (1 << 5)
+#define DM9161_REMOTE_FAULT (1 << 4)
+#define DM9161_AUTONEG_ABILITY (1 << 3)
+#define DM9161_LINK_STATUS (1 << 2)
+#define DM9161_JABBER_DETECT (1 << 1)
+#define DM9161_EXTEND_CAPAB (1 << 0)
+
+//--definitions: DM9161_PHYID1
+#define DM9161_PHYID1_OUI 0x606E
+#define DM9161_LSB_MASK 0x3F
+
+//--Bit definitions: DM9161_ANAR, DM9161_ANLPAR
+#define DM9161_NP (1 << 15)
+#define DM9161_ACK (1 << 14)
+#define DM9161_RF (1 << 13)
+#define DM9161_FCS (1 << 10)
+#define DM9161_T4 (1 << 9)
+#define DM9161_TX_FDX (1 << 8)
+#define DM9161_TX_HDX (1 << 7)
+#define DM9161_10_FDX (1 << 6)
+#define DM9161_10_HDX (1 << 5)
+#define DM9161_AN_IEEE_802_3 0x0001
+
+//--Bit definitions: DM9161_ANER
+#define DM9161_PDF (1 << 4)
+#define DM9161_LP_NP_ABLE (1 << 3)
+#define DM9161_NP_ABLE (1 << 2)
+#define DM9161_PAGE_RX (1 << 1)
+#define DM9161_LP_AN_ABLE (1 << 0)
+
+//--Bit definitions: DM9161_DSCR
+#define DM9161_BP4B5B (1 << 15)
+#define DM9161_BP_SCR (1 << 14)
+#define DM9161_BP_ALIGN (1 << 13)
+#define DM9161_BP_ADPOK (1 << 12)
+#define DM9161_REPEATER (1 << 11)
+#define DM9161_TX (1 << 10)
+#define DM9161_RMII_ENABLE (1 << 8)
+#define DM9161_F_LINK_100 (1 << 7)
+#define DM9161_SPLED_CTL (1 << 6)
+#define DM9161_COLLED_CTL (1 << 5)
+#define DM9161_RPDCTR_EN (1 << 4)
+#define DM9161_SM_RST (1 << 3)
+#define DM9161_MFP SC (1 << 2)
+#define DM9161_SLEEP (1 << 1)
+#define DM9161_RLOUT (1 << 0)
+
+//--Bit definitions: DM9161_DSCSR
+#define DM9161_100FDX (1 << 15)
+#define DM9161_100HDX (1 << 14)
+#define DM9161_10FDX (1 << 13)
+#define DM9161_10HDX (1 << 12)
+
+//--Bit definitions: DM9161_10BTCSR
+#define DM9161_LP_EN (1 << 14)
+#define DM9161_HBE (1 << 13)
+#define DM9161_SQUELCH (1 << 12)
+#define DM9161_JABEN (1 << 11)
+#define DM9161_10BT_SER (1 << 10)
+#define DM9161_POLR (1 << 0)
+
+
+//--Bit definitions: DM9161_MDINTR
+#define DM9161_INTR_PEND (1 << 15)
+#define DM9161_FDX_MASK (1 << 11)
+#define DM9161_SPD_MASK (1 << 10)
+#define DM9161_LINK_MASK (1 << 9)
+#define DM9161_INTR_MASK (1 << 8)
+#define DM9161_FDX_CHANGE (1 << 4)
+#define DM9161_SPD_CHANGE (1 << 3)
+#define DM9161_LINK_CHANGE (1 << 2)
+#define DM9161_INTR_STATUS (1 << 0)
+
+
+/****************** function prototypes **********************/
+static unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac);
+static unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac);
+static unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
+static unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac);
diff --git a/include/flash.h b/include/flash.h
index 882652d..e594788 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -33,15 +33,15 @@
ulong size; /* total bank size in bytes */
ushort sector_count; /* number of erase units */
ulong flash_id; /* combined device & manufacturer code */
- ulong start[CFG_MAX_FLASH_SECT]; /* physical sector start addresses */
+ ulong start[CFG_MAX_FLASH_SECT]; /* physical sector start addresses */
uchar protect[CFG_MAX_FLASH_SECT]; /* sector protection status */
#ifdef CFG_FLASH_CFI
uchar portwidth; /* the width of the port */
uchar chipwidth; /* the width of the chip */
- ushort buffer_size; /* # of bytes in write buffer */
+ ushort buffer_size; /* # of bytes in write buffer */
ulong erase_blk_tout; /* maximum block erase timeout */
ulong write_tout; /* maximum write timeout */
- ulong buffer_write_tout; /* maximum buffer write timeout */
+ ulong buffer_write_tout; /* maximum buffer write timeout */
#endif
} flash_info_t;
@@ -103,20 +103,20 @@
* Device IDs
*/
-#define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */
+#define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */
#define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */
-#define ATM_MANUFACT 0x001F001F /* ATMEL */
-#define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */
-#define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */
-#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */
+#define ATM_MANUFACT 0x001F001F /* ATMEL */
+#define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */
+#define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */
+#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */
#define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */
-#define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */
+#define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */
#define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */
#define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */
/* Micron Technologies (INTEL compat.) */
#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
-#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */
+#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */
#define AMD_ID_LV040B 0x4F /* 29LV040B ID */
/* 4 Mbit, 512K x 8, */
@@ -125,7 +125,7 @@
#define AMD_ID_F040B 0xA4 /* 29F040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
-#define STM_ID_M29W040B 0xE3 /* M29W040B ID */
+#define STM_ID_M29W040B 0xE3 /* M29W040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
#define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */
@@ -137,49 +137,50 @@
#define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */
#define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */
-#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
+#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
#define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4M x 8 ) */
#define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */
-#define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */
+#define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */
#define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */
-#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
+#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
-#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */
+#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */
#define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */
-#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */
+#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */
#define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */
-#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */
+#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */
#define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */
#define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */
#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
-#define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */
-#define AMD_ID_LV128U_2 0x22122212 /* 2d ID word for AM29LV128M at 0x38 */
-#define AMD_ID_LV128U_3 0x22002200 /* 3d ID word for AM29LV128M at 0x3c */
+#define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */
+#define AMD_ID_LV128U_2 0x22122212 /* 2d ID word for AM29LV128M at 0x38 */
+#define AMD_ID_LV128U_3 0x22002200 /* 3d ID word for AM29LV128M at 0x3c */
#define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */
-#define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */
+#define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */
+#define ATM_ID_BV1614A 0x000000C8 /* 49BV1614A ID */
-#define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */
-#define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */
+#define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */
+#define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */
-#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
-#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
-#define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */
-#define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */
+#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
+#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
+#define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */
+#define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */
-#define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */
+#define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */
/* 8 64K x 8 uniform sectors */
-#define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */
-#define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */
-#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */
+#define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */
+#define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */
+#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */
#define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */
#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
@@ -202,7 +203,7 @@
#define INTEL_ID_28F640C3T 0x88CC88CC /* 64M = 4M x 16 top boot sector */
#define INTEL_ID_28F640C3B 0x88CD88CD /* 64M = 4M x 16 bottom boot sector */
-#define INTEL_ID_28F128J3 0x89189818 /* 16M = 8M x 16 x 128 */
+#define INTEL_ID_28F128J3 0x89189818 /* 16M = 8M x 16 x 128 */
#define INTEL_ID_28F640J5 0x00150015 /* 64M = 128K x 64 */
#define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */
#define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */
@@ -217,8 +218,8 @@
#define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */
/* LH28F008SCR-L85 1Mx8, 16 64k blocks */
-#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */
-#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */
+#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */
+#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */
/*-----------------------------------------------------------------------
* Internal FLASH identification codes
@@ -226,25 +227,25 @@
* Be careful when adding new type! Odd numbers are "bottom boot sector" types!
*/
-#define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B */
- /* Bright Micro BM29F040 */
- /* Fujitsu MBM29F040A */
- /* STM M29W040B */
- /* SGS Thomson M29F040B */
- /* 8 64K x 8 uniform sectors */
+#define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B */
+ /* Bright Micro BM29F040 */
+ /* Fujitsu MBM29F040A */
+ /* STM M29W040B */
+ /* SGS Thomson M29F040B */
+ /* 8 64K x 8 uniform sectors */
#define FLASH_AM400T 0x0002 /* AMD AM29LV400 */
#define FLASH_AM400B 0x0003
#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */
#define FLASH_AM800B 0x0005
#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */
#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */
-#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */
+#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */
#define FLASH_AM160B 0x0007
#define FLASH_AM320T 0x0008 /* AMD AM29LV320 */
#define FLASH_AM320B 0x0009
-#define FLASH_AM080 0x000A /* AMD Am29F080B */
- /* 16 64K x 8 uniform sectors */
+#define FLASH_AM080 0x000A /* AMD Am29F080B */
+ /* 16 64K x 8 uniform sectors */
#define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */
#define FLASH_AMDL322B 0x0011
@@ -262,8 +263,8 @@
#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */
-#define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */
-#define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/
+#define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */
+#define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/
#define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/
#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */
#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
@@ -287,26 +288,26 @@
#define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */
#define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */
#define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */
-#define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */
+#define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */
#define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */
#define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */
#define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */
#define FLASH_AM640U 0x0090 /* AMD Am29LV640U ( 64M = 4M x 16 ) */
#define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */
-#define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
-#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */
+#define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
+#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */
-#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */
+#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */
-#define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */
-#define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */
-#define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */
-#define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */
-#define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */
-#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */
-#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */
-#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */
-#define FLASH_AMLV128U 0x00A2 /* AMD 29LV128M ( 128M = 8M x 16 ) */
+#define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */
+#define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */
+#define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */
+#define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */
+#define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */
+#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */
+#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */
+#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */
+#define FLASH_AMLV128U 0x00A2 /* AMD 29LV128M ( 128M = 8M x 16 ) */
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
@@ -318,14 +319,14 @@
#define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */
#define FLASH_MAN_MX 0x00030000 /* MXIC */
#define FLASH_MAN_STM 0x00040000
-#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */
+#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */
#define FLASH_MAN_SST 0x00100000
-#define FLASH_MAN_INTEL 0x00300000
+#define FLASH_MAN_INTEL 0x00300000
#define FLASH_MAN_MT 0x00400000
-#define FLASH_MAN_SHARP 0x00500000
+#define FLASH_MAN_SHARP 0x00500000
-#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
+#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */
#define FLASH_AMD_COMP 0x000FFFFF /* Up to this ID, FLASH is compatible */