Merge tag 'xilinx-for-v2025.04-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.04-rc1 v2
Versal:
- Enable dfu support for SPI with multiboot
ZynqMP:
- Align multiboot reg description
- DT syncups
- Wire missing DTs in defconfig
- Kria: Remove usb hub initialization via commands
- Kria: Update DP reset in psu_init
AMD/Xilinx:
- Enable SPI_STACKED_PARALLEL configs
SPI/ZYNQMP_GQSPI:
- Update debug message to use log_debug()
RTC:
- Enable ZYNQMP_RTC for Versal SOCs
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 60d1b1a..385fed8 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -10,39 +10,44 @@
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
- pss_ref_clk: pss_ref_clk {
+ pss_ref_clk: pss-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>;
+ clock-output-names = "pss_ref_clk";
};
- video_clk: video_clk {
+ video_clk: video-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
+ clock-output-names = "video_clk";
};
- pss_alt_ref_clk: pss_alt_ref_clk {
+ pss_alt_ref_clk: pss-alt-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
+ clock-output-names = "pss_alt_ref_clk";
};
- gt_crx_ref_clk: gt_crx_ref_clk {
+ gt_crx_ref_clk: gt-crx-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <108000000>;
+ clock-output-names = "gt_crx_ref_clk";
};
- aux_ref_clk: aux_ref_clk {
+ aux_ref_clk: aux-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
+ clock-output-names = "aux_ref_clk";
};
};
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index 4e0587f..6e2d954 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -494,6 +494,7 @@
/* Use for storing information about SC board */
eeprom: eeprom@54 { /* u34 - m24128 16kB */
compatible = "st,24c128", "atmel,24c128";
+ label = "eeprom_cc";
reg = <0x54>; /* 0x5c too */
};
si570_ref_clk: clock-generator@5d { /* u32 */
@@ -509,6 +510,7 @@
/* and connector J212D */
eeprom_ebm: eeprom@52 { /* x-ebm module */
compatible = "st,24c128", "atmel,24c128";
+ label = "eeprom_ebm";
reg = <0x52>;
};
};
@@ -520,6 +522,7 @@
/* expected eeprom 0x50 FMC cards */
eeprom_fmc1: eeprom@50 {
compatible = "st,24c128", "atmel,24c128";
+ label = "eeprom_fmc1";
reg = <0x50>;
};
};
@@ -531,6 +534,7 @@
/* expected eeprom 0x50 FMC cards */
eeprom_fmc2: eeprom@50 {
compatible = "st,24c128", "atmel,24c128";
+ label = "eeprom_fmc2";
reg = <0x50>;
};
};
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
index c4f7058..6f58560 100644
--- a/arch/arm/dts/zynqmp-sc-revB.dts
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -175,6 +175,7 @@
/* Use for storing information about SC board */
eeprom: eeprom@54 { /* u34 - m24128 16kB */
compatible = "st,24c128", "atmel,24c128";
+ label = "eeprom_cc";
reg = <0x54>; /* & 0x5c */
bootph-all;
};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 620f518..70acd3e 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -90,20 +90,6 @@
};
};
- ams {
- compatible = "iio-hwmon";
- io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
- <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
- <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
- <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
- <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
- <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
- <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
- <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
- <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
- <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
- };
-
pwm-fan {
compatible = "pwm-fan";
status = "okay";
@@ -111,6 +97,10 @@
};
};
+&ams {
+ status = "okay";
+};
+
&modepin_gpio {
label = "modepin";
};
@@ -369,10 +359,6 @@
"", "", "", ""; /* 170 - 173 */
};
-&xilinx_ams {
- status = "okay";
-};
-
&ams_ps {
status = "okay";
};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index c905136..3542844 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -593,10 +593,6 @@
status = "okay";
};
-&xilinx_ams {
- status = "okay";
-};
-
&ams_ps {
status = "okay";
};
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index dd63d22..955810a 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -1065,10 +1065,6 @@
status = "okay";
};
-&xilinx_ams {
- status = "okay";
-};
-
&ams_ps {
status = "okay";
};
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index 31effbf..64d8222 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -527,10 +527,6 @@
status = "okay";
};
-&xilinx_ams {
- status = "okay";
-};
-
&ams_ps {
status = "okay";
};
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 999b243..3e883d7 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -539,10 +539,6 @@
status = "okay";
};
-&xilinx_ams {
- status = "okay";
-};
-
&ams_ps {
status = "okay";
};
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 70ca5e6..0e0436e 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -18,6 +18,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "xlnx,zynqmp";
@@ -36,6 +37,7 @@
#size-cells = <0>;
cpu0: cpu@0 {
+ #cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
@@ -46,6 +48,7 @@
};
cpu1: cpu@1 {
+ #cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
@@ -56,6 +59,7 @@
};
cpu2: cpu@2 {
+ #cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
@@ -66,6 +70,7 @@
};
cpu3: cpu@3 {
+ #cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
@@ -388,6 +393,102 @@
};
};
+ ams: ams {
+ compatible = "iio-hwmon";
+ status = "disabled";
+ io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
+ <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
+ <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
+ <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
+ <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
+ <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
+ <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
+ <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
+ <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
+ <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
+ };
+
+
+ tsens_apu: thermal-sensor-apu {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&xilinx_ams 7>;
+ io-channel-names = "sensor-channel";
+ };
+
+ tsens_rpu: thermal-sensor-rpu {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&xilinx_ams 8>;
+ io-channel-names = "sensor-channel";
+ };
+
+ tsens_pl: thermal-sensor-pl {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&xilinx_ams 20>;
+ io-channel-names = "sensor-channel";
+ };
+
+ thermal-zones {
+ apu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tsens_apu>;
+
+ trips {
+ apu_passive: passive {
+ temperature = <93000>;
+ hysteresis = <3500>;
+ type = "passive";
+ };
+
+ apu_critical: critical {
+ temperature = <96500>;
+ hysteresis = <3500>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&apu_passive>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ rpu-thermal {
+ polling-delay = <10000>;
+ thermal-sensors = <&tsens_rpu>;
+
+ trips {
+ critical {
+ temperature = <96500>;
+ hysteresis = <3500>;
+ type = "critical";
+ };
+ };
+ };
+
+ pl-thermal {
+ polling-delay = <10000>;
+ thermal-sensors = <&tsens_pl>;
+
+ trips {
+ critical {
+ temperature = <96500>;
+ hysteresis = <3500>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
amba: axi {
compatible = "simple-bus";
bootph-all;
@@ -1153,7 +1254,6 @@
xilinx_ams: ams@ffa50000 {
compatible = "xlnx,zynqmp-ams";
- status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xffa50000 0x0 0x800>;
diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c
index 8ee25e4..3aa2185 100644
--- a/arch/arm/mach-zynqmp/zynqmp.c
+++ b/arch/arm/mach-zynqmp/zynqmp.c
@@ -349,7 +349,7 @@
multiboot = hextoul(argv[2], NULL);
- ret = zynqmp_mmio_write(0xFFCA0010, 0xfff, multiboot);
+ ret = zynqmp_mmio_write((ulong)&csu_base->multi_boot, 0xfff, multiboot);
if (ret != 0) {
printf("Failed: mmio write\n");
return ret;
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index fd5c6ce..b4483d0 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -6,6 +6,7 @@
#include <command.h>
#include <cpu_func.h>
+#include <dfu.h>
#include <env.h>
#include <fdtdec.h>
#include <init.h>
@@ -14,6 +15,7 @@
#include <malloc.h>
#include <memalign.h>
#include <mmc.h>
+#include <mtd.h>
#include <time.h>
#include <asm/cache.h>
#include <asm/global_data.h>
@@ -35,9 +37,36 @@
};
#endif
+static u8 versal_get_bootmode(void)
+{
+ u8 bootmode;
+ u32 reg = 0;
+
+ reg = readl(&crp_base->boot_mode_usr);
+
+ if (reg >> BOOT_MODE_ALT_SHIFT)
+ reg >>= BOOT_MODE_ALT_SHIFT;
+
+ bootmode = reg & BOOT_MODES_MASK;
+
+ return bootmode;
+}
+
+static u32 versal_multi_boot(void)
+{
+ u8 bootmode = versal_get_bootmode();
+
+ /* Mostly workaround for QEMU CI pipeline */
+ if (bootmode == JTAG_MODE)
+ return 0;
+
+ return readl(0xF1110004);
+}
+
int board_init(void)
{
printf("EL Level:\tEL%d\n", current_el());
+ printf("Multiboot:\t%d\n", versal_multi_boot());
#if defined(CONFIG_FPGA_VERSALPL)
fpga_init();
@@ -113,21 +142,6 @@
return ret;
}
-static u8 versal_get_bootmode(void)
-{
- u8 bootmode;
- u32 reg = 0;
-
- reg = readl(&crp_base->boot_mode_usr);
-
- if (reg >> BOOT_MODE_ALT_SHIFT)
- reg >>= BOOT_MODE_ALT_SHIFT;
-
- bootmode = reg & BOOT_MODES_MASK;
-
- return bootmode;
-}
-
static int boot_targets_setup(void)
{
u8 bootmode;
@@ -346,9 +360,35 @@
#define DFU_ALT_BUF_LEN SZ_1K
+static void mtd_found_part(u32 *base, u32 *size)
+{
+ struct mtd_info *part, *mtd;
+
+ mtd_probe_devices();
+
+ mtd = get_mtd_device_nm("nor0");
+ if (!IS_ERR_OR_NULL(mtd)) {
+ list_for_each_entry(part, &mtd->partitions, node) {
+ debug("0x%012llx-0x%012llx : \"%s\"\n",
+ part->offset, part->offset + part->size,
+ part->name);
+
+ if (*base >= part->offset &&
+ *base < part->offset + part->size) {
+ debug("Found my partition: %d/%s\n",
+ part->index, part->name);
+ *base = part->offset;
+ *size = part->size;
+ break;
+ }
+ }
+ }
+}
+
void set_dfu_alt_info(char *interface, char *devstr)
{
int bootseq = 0, len = 0;
+ u32 multiboot = versal_multi_boot();
u32 bootmode = versal_get_bootmode();
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
@@ -358,6 +398,8 @@
memset(buf, 0, sizeof(buf));
+ multiboot = env_get_hex("multiboot", multiboot);
+
switch (bootmode) {
case EMMC_MODE:
case SD_MODE:
@@ -368,9 +410,28 @@
len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot",
bootseq);
+ if (multiboot)
+ len += snprintf(buf + len, DFU_ALT_BUF_LEN,
+ "%04d", multiboot);
+
len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1",
bootseq);
break;
+ case QSPI_MODE_24BIT:
+ case QSPI_MODE_32BIT:
+ case OSPI_MODE:
+ {
+ u32 base = multiboot * SZ_32K;
+ u32 size = 0x1500000;
+ u32 limit = size;
+
+ mtd_found_part(&base, &limit);
+
+ len += snprintf(buf + len, DFU_ALT_BUF_LEN,
+ "sf 0:0=boot.bin raw 0x%x 0x%x",
+ base, limit);
+ }
+ break;
default:
return;
}
diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
index e559880..f8d7c84 100644
--- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
@@ -465,7 +465,7 @@
static unsigned long psu_peripherals_init_data(void)
{
- psu_mask_write(0xFD1A0100, 0x0000807CU, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env
index ff3a092..b0c2ac6 100644
--- a/board/xilinx/zynqmp/zynqmp_kria.env
+++ b/board/xilinx/zynqmp/zynqmp_kria.env
@@ -62,14 +62,8 @@
bootmenu_1=SD Boot=run som_cc_boot
bootmenu_delay=5
-usb_hub_init=mw 1000 0056 && sleep 1 && i2c write 1000 2d aa 2 -s
-
-# usb hub init
-kv260_setup=i2c dev 1 && run usb_hub_init
-# usb hub init
-kr260_setup=i2c dev 1 && run usb_hub_init; i2c dev 2 && run usb_hub_init;
-# usb hub init with enabling PM nodes for ...
-kd240_setup=i2c dev 1 && run usb_hub_init;zynqmp pmufw node 33; zynqmp pmufw node 47
+# Enabling PM nodes for uart0 and can0
+kd240_setup=zynqmp pmufw node 33; zynqmp pmufw node 47
tpm_setup=tpm autostart;
tpm_reset=echo "!!! For TPM reset a full power cycle or pressing the POR_B button is required !!!";
@@ -79,7 +73,7 @@
board_setup=\
rtc dev 0; \
zynqmp mmio_write 0xFFCA0010 0xfff 0; \
-if test ${card1_name} = SCK-KV-G; then run kv260_setup; run tpm_kv260; fi;\
-if test ${card1_name} = SCK-KR-G; then run kr260_setup; run tpm_reset; fi;\
+if test ${card1_name} = SCK-KV-G; then run tpm_kv260; fi;\
+if test ${card1_name} = SCK-KR-G; then run tpm_reset; fi;\
if test ${card1_name} = SCK-KD-G; then run kd240_setup; run tpm_kd240; fi;\
run tpm_setup
diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig
index eb63f06..2750fa2 100644
--- a/configs/amd_versal2_mini_qspi_defconfig
+++ b/configs/amd_versal2_mini_qspi_defconfig
@@ -74,5 +74,6 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index 4d23b35..529815a 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -78,4 +78,5 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig
index 8453be5..818c62c 100644
--- a/configs/xilinx_versal_net_mini_qspi_defconfig
+++ b/configs/xilinx_versal_net_mini_qspi_defconfig
@@ -76,4 +76,5 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index c8f166c..fb757c1 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -83,6 +83,7 @@
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000
CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_FPGA_XILINX=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index 8fb66f7..a68bd52 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -197,6 +197,7 @@
CONFIG_SPI=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_POWEROFF=y
CONFIG_SYSRESET_PSCI=y
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index 9d78541..7667e67 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -93,6 +93,7 @@
CONFIG_ARM_DCC=y
CONFIG_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
# CONFIG_BINMAN_FDT is not set
CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb"
CONFIG_PANIC_HANG=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 09f487a..b13079c 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -110,7 +110,7 @@
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_BOARD=y
-CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-e-a2197-00-revB zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA"
+CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-dlc21-revA zynqmp-e-a2197-00-revA zynqmp-e-a2197-00-revB zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-vpk120-revA zynqmp-vp-x-a2785-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.0 zynqmp-zcu102-rev1.1 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-rev1.0 zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-zcu670-revA zynqmp-zcu670-revB"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index cd84df1..6a5e1dd 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -92,6 +92,7 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_ARM_DCC=y
CONFIG_ZYNQ_QSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 9c2d139..6467f20 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -294,7 +294,7 @@
config RTC_ZYNQMP
bool "Enable ZynqMP RTC driver"
- depends on ARCH_ZYNQMP
+ depends on DM_RTC && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2)
help
Say "yes" here to support the on chip real time clock
present on Xilinx ZynqMP SoC.
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 4251bf2..2a095d0 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -255,7 +255,7 @@
GQSPI_GFIFO_CS_LOWER |
GQSPI_GFIFO_CS_UPPER;
else
- debug("Wrong Bus selection:0x%x\n", priv->bus);
+ log_debug("Wrong Bus selection:0x%x\n", priv->bus);
} else {
if (priv->u_page)
gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |