diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
index 307c2e2..9611d61 100644
--- a/include/configs/Sandpoint8245.h
+++ b/include/configs/Sandpoint8245.h
@@ -224,8 +224,12 @@
 
 #define CFG_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		1843200
-
+#if (CONFIG_CONS_INDEX > 2)
+#define CFG_NS16550_CLK         CONFIG_DRAM_SPEED*1000000
+#else
+#define CFG_NS16550_CLK         1843200
+#endif
+                                                                                
 #define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
 #define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)
 #define CFG_NS16550_COM3	(CFG_EUMB_ADDR + 0x4500)
diff --git a/include/configs/lpd7a400-10.h b/include/configs/lpd7a400-10.h
index ecf2b5f..3722fd2 100644
--- a/include/configs/lpd7a400-10.h
+++ b/include/configs/lpd7a400-10.h
@@ -27,8 +27,8 @@
 
 
 #define CONFIG_ARM920T		1	/* arm920t core */
-#define CONFIG_LH7A40X		1	/* Sharp LH7A400 SoC */
-#define CONFIG_LH7A400		1
+#define CONFIG_LH7A40X		1	/* Sharp LH7A40x SoC family */
+#define CONFIG_LH7A400		1   /* Sharp LH7A400 S0C */
 
 /* The system clock PLL input frequency */
 #define CONFIG_SYS_CLK_FREQ		14745600   /* System Clock PLL Input (Hz) */
diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h
index 3e91536..808fe1c 100644
--- a/include/configs/lpd7a400.h
+++ b/include/configs/lpd7a400.h
@@ -21,6 +21,8 @@
 #ifndef __LPD7A400_H_
 #define __LPD7A400_H_
 
+#define CONFIG_LPD7A400		/* Logic LH7A400 SDK */
+
 /*
  * If we are developing, we might want to start armboot from ram
  * so we MUST NOT initialize critical regs like mem-timing ...
@@ -29,15 +31,11 @@
 
 #undef CONFIG_USE_IRQ
 
-#define MACH_TYPE_LPD7A400	389
-
 /*
  * This board uses the logic LH7A400-10 card engine
  */
 #include <configs/lpd7a400-10.h>
 
-#define CONFIG_LPD7A400		/* Logic LH7A400 SDK */
-
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS	1
 #define CONFIG_INITRD_TAG		1
diff --git a/include/configs/lpd7a404-10.h b/include/configs/lpd7a404-10.h
new file mode 100644
index 0000000..a8af950
--- /dev/null
+++ b/include/configs/lpd7a404-10.h
@@ -0,0 +1,80 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Logic LH7A400-10 card engine
+ */
+
+#ifndef __LPD7A404_10_H
+#define __LPD7A404_10_H
+
+
+#define CONFIG_ARM920T		1	/* arm920t core */
+#define CONFIG_LH7A40X		1	/* Sharp LH7A40x SoC family */
+#define CONFIG_LH7A404		1   /* Sharp LH7A404 SoC */
+
+/* The system clock PLL input frequency */
+#define CONFIG_SYS_CLK_FREQ		14745600   /* System Clock PLL Input (Hz) */
+
+/* ticks per second */
+#define CFG_HZ	(508469)
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+
+#define CFG_FLASH_BASE		0x00000000 /* Flash Bank #1 */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+
+/*----------------------------------------------------------------------
+ * Using SMC91C111 LAN chip
+ *
+ * Default IO base of chip is 0x300, Card Engine has this address lines
+ * (LAN chip) tied to Vcc, so we just care about the chip select
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE	(0x70000000)
+#undef CONFIG_SMC_USE_32_BIT
+#define CONFIG_SMC_USE_IOFUNCS
+
+#endif  /* __LPD7A404_10_H */
diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h
new file mode 100644
index 0000000..de465ea
--- /dev/null
+++ b/include/configs/lpd7a404.h
@@ -0,0 +1,112 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __LPD7A404_H_
+#define __LPD7A404_H_
+
+#define CONFIG_LPD7A404		/* Logic LH7A400 SDK */
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL	/* undef for developing */
+
+#undef CONFIG_USE_IRQ
+
+/*
+ * This board uses the logic LH7A404-10 card engine
+ */
+#include <configs/lpd7a404-10.h>
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONSOLE_UART2	/* UART2 LH7A40x for console */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_IPADDR		192.168.1.100
+#define CONFIG_NETMASK		255.255.1.0
+#define CONFIG_SERVERIP		192.168.1.1
+
+#define	CONFIG_TIMESTAMP	1	/* Print timestamp info for images */
+
+#ifndef USE_920T_MMU
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE))
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE)
+#endif
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"LPD7A404> "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0300000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0500000	/* 2 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0xc0f00000	/* default load address	*/
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* size and location of u-boot in flash */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256<<10)
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0xFC0000)
+#define CFG_ENV_SIZE		0x40000
+
+#endif  /* __LPD7A404_H_ */