Merge branch 'u-boot-nand-20241012' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
This merge request add support for BCMBCA raw nand driver for bcm96846
board that switch using OF_UPSTREAM and allow use onfi ecc params when
they are available in the atmel nand controller
The patches pass the pipeline CI:
https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/22638
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 65176c8..123e121 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -721,13 +721,6 @@
sun50i-h6-pine-h64-model-b.dtb \
sun50i-h6-tanix-tx6.dtb \
sun50i-h6-tanix-tx6-mini.dtb
-dtb-$(CONFIG_MACH_SUN50I_H616) += \
- sun50i-h313-tanix-tx1.dtb \
- sun50i-h616-orangepi-zero2.dtb \
- sun50i-h618-orangepi-zero2w.dtb \
- sun50i-h618-orangepi-zero3.dtb \
- sun50i-h618-transpeed-8k618-t.dtb \
- sun50i-h616-x96-mate.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
sun50i-a64-bananapi-m64.dtb \
@@ -967,7 +960,6 @@
imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \
- imx8mp-debix-model-a.dtb \
imx8mp-dhcom-drc02.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
diff --git a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
index 33bd89a..d5bd9f5 100644
--- a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
@@ -20,6 +20,14 @@
};
};
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
+ bootph-pre-ram;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+ bootph-pre-ram;
+};
+
&crypto {
bootph-pre-ram;
};
@@ -88,14 +96,6 @@
bootph-pre-ram;
};
-&pmic {
- bootph-pre-ram;
-
- regulators {
- bootph-pre-ram;
- };
-};
-
®_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
diff --git a/arch/arm/dts/imx8mp-debix-model-a.dts b/arch/arm/dts/imx8mp-debix-model-a.dts
deleted file mode 100644
index 58dae61..0000000
--- a/arch/arm/dts/imx8mp-debix-model-a.dts
+++ /dev/null
@@ -1,507 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 NXP
- * Copyright 2022 Ideas on Board Oy
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/usb/pd.h>
-
-#include "imx8mp.dtsi"
-
-/ {
- model = "Polyhex Debix Model A i.MX8MPlus board";
- compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart2;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_led>;
-
- led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2>;
-};
-
-&eqos {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- phy-connection-type = "rgmii-id";
- phy-handle = <ðphy0>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 { /* RTL8211E */
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
- reset-assert-us = <20>;
- reset-deassert-us = <200000>;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic: pmic@25 {
- compatible = "nxp,pca9450c";
- reg = <0x25>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
-
- regulators {
- buck1: BUCK1 {
- regulator-name = "BUCK1";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- };
-
- buck2: BUCK2 {
- regulator-name = "BUCK2";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- };
-
- buck4: BUCK4{
- regulator-name = "BUCK4";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5: BUCK5{
- regulator-name = "BUCK5";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6: BUCK6 {
- regulator-name = "BUCK6";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1: LDO1 {
- regulator-name = "LDO1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2: LDO2 {
- regulator-name = "LDO2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3: LDO3 {
- regulator-name = "LDO3";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4: LDO4 {
- regulator-name = "LDO4";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo5: LDO5 {
- regulator-name = "LDO5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- interrupt-parent = <&gpio2>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rtc_int>;
- };
-};
-
-&i2c6 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c6>;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-&uart2 {
- /* console */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-/* SD Card */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- bus-width = <4>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
- MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f
- MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f
- MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
- MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
- MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f
- MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f
- MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19
- >;
- };
-
- pinctrl_gpio_led: gpioledgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
- MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c6: i2c6grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3
- MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
- >;
- };
-
- pinctrl_pmic: pmicirqgrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
- >;
- };
-
- pinctrl_rtc_int: rtcintgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
- MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
- MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
- >;
- };
-};
-
diff --git a/arch/arm/dts/sun50i-h313-tanix-tx1.dts b/arch/arm/dts/sun50i-h313-tanix-tx1.dts
deleted file mode 100644
index bb2cde5..0000000
--- a/arch/arm/dts/sun50i-h313-tanix-tx1.dts
+++ /dev/null
@@ -1,183 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2024 Arm Ltd.
- */
-
-/dts-v1/;
-
-#include "sun50i-h616.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Tanix TX1";
- compatible = "oranth,tanix-tx1", "allwinner,sun50i-h616";
-
- aliases {
- serial0 = &uart0;
- ethernet0 = &sdio_wifi;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key {
- label = "hidden";
- linux,code = <BTN_0>;
- gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 */
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
- default-state = "on";
- };
- };
-
- wifi_pwrseq: pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rtc CLK_OSC32K_FANOUT>;
- clock-names = "ext_clock";
- pinctrl-0 = <&x32clk_fanout_pin>;
- pinctrl-names = "default";
- reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
- };
-
- reg_vcc5v: vcc5v {
- /* board wide 5V supply directly from the DC input */
- compatible = "regulator-fixed";
- regulator-name = "vcc-5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ir {
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_dldo1>;
- vqmmc-supply = <®_aldo1>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- sdio_wifi: wifi@1 {
- reg = <1>;
- };
-};
-
-&mmc2 {
- vmmc-supply = <®_dldo1>;
- vqmmc-supply = <®_aldo1>;
- bus-width = <8>;
- non-removable;
- max-frequency = <100000000>;
- cap-mmc-hw-reset;
- mmc-ddr-1_8v;
- status = "okay";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&pio {
- vcc-pc-supply = <®_aldo1>;
- vcc-pf-supply = <®_dldo1>;
- vcc-pg-supply = <®_aldo1>;
- vcc-ph-supply = <®_dldo1>;
- vcc-pi-supply = <®_dldo1>;
-};
-
-&r_i2c {
- status = "okay";
-
- axp313: pmic@36 {
- compatible = "x-powers,axp313a";
- reg = <0x36>;
- #interrupt-cells = <1>;
- interrupt-controller;
-
- vin1-supply = <®_vcc5v>;
- vin2-supply = <®_vcc5v>;
- vin3-supply = <®_vcc5v>;
-
- regulators {
- /* Supplies VCC-PLL, so needs to be always on. */
- reg_aldo1: aldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8";
- };
-
- /* Supplies VCC-IO, so needs to be always on. */
- reg_dldo1: dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3";
- };
-
- reg_dcdc1: dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <990000>;
- regulator-name = "vdd-gpu-sys";
- };
-
- reg_dcdc2: dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1120000>;
- regulator-name = "vdd-cpu";
- };
-
- reg_dcdc3: dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-name = "vdd-dram";
- };
- };
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_ph_pins>;
- status = "okay";
-};
-
-&usbotg {
- dr_mode = "host"; /* USB A type receptable */
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts b/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts
deleted file mode 100644
index 4bfb526..0000000
--- a/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts
+++ /dev/null
@@ -1,35 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>.
- */
-
-/dts-v1/;
-
-#include "sun50i-h616-bigtreetech-cb1.dtsi"
-
-/ {
- model = "BigTreeTech CB1";
- compatible = "bigtreetech,cb1-manta", "bigtreetech,cb1", "allwinner,sun50i-h616";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_ph_pins>;
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi
deleted file mode 100644
index d12b01c..0000000
--- a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi
+++ /dev/null
@@ -1,143 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>.
- */
-
-/dts-v1/;
-
-#include "sun50i-h616.dtsi"
-#include "sun50i-h616-cpu-opp.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- aliases {
- ethernet0 = &rtl8189ftv;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
- };
- };
-
- reg_vcc5v: regulator-vcc5v {
- /* board wide 5V supply from carrier boards */
- compatible = "regulator-fixed";
- regulator-name = "vcc-5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- reg_vcc33_wifi: vcc33-wifi {
- compatible = "regulator-fixed";
- regulator-name = "vcc33-wifi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- vin-supply = <®_vcc5v>;
- };
-
- reg_vcc_wifi_io: vcc-wifi-io {
- compatible = "regulator-fixed";
- regulator-name = "vcc-wifi-io";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- vin-supply = <®_vcc33_wifi>;
- };
-
- wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rtc 1>;
- clock-names = "ext_clock";
- reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
- post-power-on-delay-ms = <200>;
- };
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&mmc0 {
- vmmc-supply = <®_dldo1>;
- /* Card detection pin is not connected */
- broken-cd;
- bus-width = <4>;
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc33_wifi>;
- vqmmc-supply = <®_vcc_wifi_io>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- mmc-ddr-1_8v;
- status = "okay";
-
- rtl8189ftv: wifi@1 {
- reg = <1>;
- };
-};
-
-&r_i2c {
- status = "okay";
-
- axp313a: pmic@36 {
- compatible = "x-powers,axp313a";
- reg = <0x36>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- regulators {
- reg_dcdc1: dcdc1 {
- regulator-name = "vdd-gpu-sys";
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <990000>;
- regulator-always-on;
- };
-
- reg_dcdc2: dcdc2 {
- regulator-name = "vdd-cpu";
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1100000>;
- regulator-ramp-delay = <200>;
- regulator-always-on;
- };
-
- reg_dcdc3: dcdc3 {
- regulator-name = "vcc-dram";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- };
-
- reg_aldo1: aldo1 {
- regulator-name = "vcc-1v8-pll";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- reg_dldo1: dldo1 {
- regulator-name = "vcc-3v3-io";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
-};
-
-&usbphy {
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts b/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts
deleted file mode 100644
index ff84a37..0000000
--- a/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2023 Martin Botka <martin@biqu3d.com>.
- */
-
-/dts-v1/;
-
-#include "sun50i-h616-bigtreetech-cb1.dtsi"
-
-/ {
- model = "BigTreeTech Pi";
- compatible = "bigtreetech,pi", "allwinner,sun50i-h616";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&ir {
- status = "okay";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_ph_pins>;
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h616-cpu-opp.dtsi b/arch/arm/dts/sun50i-h616-cpu-opp.dtsi
deleted file mode 100644
index aca22a7..0000000
--- a/arch/arm/dts/sun50i-h616-cpu-opp.dtsi
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2023 Martin Botka <martin@somainline.org>
-
-/ {
- cpu_opp_table: opp-table-cpu {
- compatible = "allwinner,sun50i-h616-operating-points";
- nvmem-cells = <&cpu_speed_grade>;
- opp-shared;
-
- opp-480000000 {
- opp-hz = /bits/ 64 <480000000>;
- opp-microvolt = <900000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x1f>;
- };
-
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <900000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x12>;
- };
-
- opp-720000000 {
- opp-hz = /bits/ 64 <720000000>;
- opp-microvolt = <900000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x0d>;
- };
-
- opp-792000000 {
- opp-hz = /bits/ 64 <792000000>;
- opp-microvolt-speed1 = <900000>;
- opp-microvolt-speed4 = <940000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x12>;
- };
-
- opp-936000000 {
- opp-hz = /bits/ 64 <936000000>;
- opp-microvolt = <900000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x0d>;
- };
-
- opp-1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt-speed0 = <950000>;
- opp-microvolt-speed1 = <940000>;
- opp-microvolt-speed2 = <950000>;
- opp-microvolt-speed3 = <950000>;
- opp-microvolt-speed4 = <1020000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x1f>;
- };
-
- opp-1104000000 {
- opp-hz = /bits/ 64 <1104000000>;
- opp-microvolt-speed0 = <1000000>;
- opp-microvolt-speed2 = <1000000>;
- opp-microvolt-speed3 = <1000000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x0d>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt-speed0 = <1050000>;
- opp-microvolt-speed1 = <1020000>;
- opp-microvolt-speed2 = <1050000>;
- opp-microvolt-speed3 = <1050000>;
- opp-microvolt-speed4 = <1100000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x1f>;
- };
-
- opp-1320000000 {
- opp-hz = /bits/ 64 <1320000000>;
- opp-microvolt = <1100000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x1d>;
- };
-
- opp-1416000000 {
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <1100000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x0d>;
- };
-
- opp-1512000000 {
- opp-hz = /bits/ 64 <1512000000>;
- opp-microvolt-speed1 = <1100000>;
- opp-microvolt-speed3 = <1100000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x0a>;
- };
- };
-};
-
-&cpu0 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu1 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu2 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu3 {
- operating-points-v2 = <&cpu_opp_table>;
-};
diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi
deleted file mode 100644
index fc7315b..0000000
--- a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2020 Arm Ltd.
- *
- * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3.
- * Excludes PMIC nodes and properties, since they are different between the two.
- */
-
-#include "sun50i-h616.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- aliases {
- ethernet0 = &emac0;
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
- default-state = "on";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
- };
- };
-
- reg_vcc5v: vcc5v {
- /* board wide 5V supply directly from the USB-C socket */
- compatible = "regulator-fixed";
- regulator-name = "vcc-5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- reg_usb1_vbus: regulator-usb1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb1-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <®_vcc5v>;
- enable-active-high;
- gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
- };
-};
-
-&ehci1 {
- status = "okay";
-};
-
-/* USB 2 & 3 are on headers only. */
-
-&emac0 {
- pinctrl-names = "default";
- pinctrl-0 = <&ext_rgmii_pins>;
- phy-handle = <&ext_rgmii_phy>;
- status = "okay";
-};
-
-&mdio0 {
- ext_rgmii_phy: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
-
-&mmc0 {
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- bus-width = <4>;
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_ph_pins>;
- status = "okay";
-};
-
-&usbotg {
- /*
- * PHY0 pins are connected to a USB-C socket, but a role switch
- * is not implemented: both CC pins are pulled to GND.
- * The VBUS pins power the device, so a fixed peripheral mode
- * is the best choice.
- * The board can be powered via GPIOs, in this case port0 *can*
- * act as a host (with a cable/adapter ignoring CC), as VBUS is
- * then provided by the GPIOs. Any user of this setup would
- * need to adjust the DT accordingly: dr_mode set to "host",
- * enabling OHCI0 and EHCI0.
- */
- dr_mode = "peripheral";
- status = "okay";
-};
-
-&usbphy {
- usb1_vbus-supply = <®_usb1_vbus>;
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts
deleted file mode 100644
index a360d85..0000000
--- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts
+++ /dev/null
@@ -1,145 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2020 Arm Ltd.
- */
-
-/dts-v1/;
-
-#include "sun50i-h616-orangepi-zero.dtsi"
-#include "sun50i-h616-cpu-opp.dtsi"
-
-/ {
- model = "OrangePi Zero2";
- compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdca>;
-};
-
-&emac0 {
- allwinner,rx-delay-ps = <3100>;
- allwinner,tx-delay-ps = <700>;
- phy-mode = "rgmii";
- phy-supply = <®_dcdce>;
-};
-
-&mmc0 {
- vmmc-supply = <®_dcdce>;
-};
-
-&r_rsb {
- status = "okay";
-
- axp305: pmic@745 {
- compatible = "x-powers,axp305", "x-powers,axp805",
- "x-powers,axp806";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x745>;
-
- x-powers,self-working-mode;
- vina-supply = <®_vcc5v>;
- vinb-supply = <®_vcc5v>;
- vinc-supply = <®_vcc5v>;
- vind-supply = <®_vcc5v>;
- vine-supply = <®_vcc5v>;
- aldoin-supply = <®_vcc5v>;
- bldoin-supply = <®_vcc5v>;
- cldoin-supply = <®_vcc5v>;
-
- regulators {
- reg_aldo1: aldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-sys";
- };
-
- reg_aldo2: aldo2 { /* 3.3V on headers */
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3-ext";
- };
-
- reg_aldo3: aldo3 { /* 3.3V on headers */
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3-ext2";
- };
-
- reg_bldo1: bldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8";
- };
-
- bldo2 {
- /* unused */
- };
-
- bldo3 {
- /* unused */
- };
-
- bldo4 {
- /* unused */
- };
-
- cldo1 {
- /* reserved */
- };
-
- cldo2 {
- /* unused */
- };
-
- cldo3 {
- /* unused */
- };
-
- reg_dcdca: dcdca {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-cpu";
- };
-
- reg_dcdcc: dcdcc {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <990000>;
- regulator-name = "vdd-gpu-sys";
- };
-
- reg_dcdcd: dcdcd {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vdd-dram";
- };
-
- reg_dcdce: dcdce {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-eth-mmc";
- };
-
- sw {
- /* unused */
- };
- };
- };
-};
-
-&pio {
- vcc-pc-supply = <®_aldo1>;
- vcc-pf-supply = <®_aldo1>;
- vcc-pg-supply = <®_bldo1>;
- vcc-ph-supply = <®_aldo1>;
- vcc-pi-supply = <®_aldo1>;
-};
diff --git a/arch/arm/dts/sun50i-h616-x96-mate.dts b/arch/arm/dts/sun50i-h616-x96-mate.dts
deleted file mode 100644
index 26d25b5..0000000
--- a/arch/arm/dts/sun50i-h616-x96-mate.dts
+++ /dev/null
@@ -1,207 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2021 Arm Ltd.
- */
-
-/dts-v1/;
-
-#include "sun50i-h616.dtsi"
-#include "sun50i-h616-cpu-opp.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- model = "X96 Mate";
- compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- reg_vcc5v: vcc5v {
- /* board wide 5V supply directly from the DC input */
- compatible = "regulator-fixed";
- regulator-name = "vcc-5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-};
-
-&cpu0 {
- cpu-supply = <®_dcdca>;
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ir {
- status = "okay";
-};
-
-&mmc0 {
- vmmc-supply = <®_dcdce>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- bus-width = <4>;
- status = "okay";
-};
-
-&mmc2 {
- vmmc-supply = <®_dcdce>;
- vqmmc-supply = <®_bldo1>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- status = "okay";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&r_rsb {
- status = "okay";
-
- axp305: pmic@745 {
- compatible = "x-powers,axp305", "x-powers,axp805",
- "x-powers,axp806";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x745>;
-
- x-powers,self-working-mode;
- vina-supply = <®_vcc5v>;
- vinb-supply = <®_vcc5v>;
- vinc-supply = <®_vcc5v>;
- vind-supply = <®_vcc5v>;
- vine-supply = <®_vcc5v>;
- aldoin-supply = <®_vcc5v>;
- bldoin-supply = <®_vcc5v>;
- cldoin-supply = <®_vcc5v>;
-
- regulators {
- reg_aldo1: aldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-sys";
- };
-
- /* Enabled by the Android BSP */
- reg_aldo2: aldo2 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3-ext";
- status = "disabled";
- };
-
- /* Enabled by the Android BSP */
- reg_aldo3: aldo3 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3-ext2";
- status = "disabled";
- };
-
- reg_bldo1: bldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8";
- };
-
- /* Enabled by the Android BSP */
- reg_bldo2: bldo2 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8-2";
- status = "disabled";
- };
-
- bldo3 {
- /* unused */
- };
-
- bldo4 {
- /* unused */
- };
-
- cldo1 {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- regulator-name = "vcc2v5";
- };
-
- cldo2 {
- /* unused */
- };
-
- cldo3 {
- /* unused */
- };
-
- reg_dcdca: dcdca {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-cpu";
- };
-
- reg_dcdcc: dcdcc {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <990000>;
- regulator-name = "vdd-gpu-sys";
- };
-
- reg_dcdcd: dcdcd {
- regulator-always-on;
- regulator-min-microvolt = <1360000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-dram";
- };
-
- reg_dcdce: dcdce {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-eth-mmc";
- };
-
- sw {
- /* unused */
- };
- };
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_ph_pins>;
- status = "okay";
-};
-
-&usbotg {
- dr_mode = "host"; /* USB A type receptable */
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi
deleted file mode 100644
index 921d5f6..0000000
--- a/arch/arm/dts/sun50i-h616.dtsi
+++ /dev/null
@@ -1,930 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2020 Arm Ltd.
-// based on the H6 dtsi, which is:
-// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/sun50i-h616-ccu.h>
-#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
-#include <dt-bindings/clock/sun6i-rtc.h>
-#include <dt-bindings/reset/sun50i-h616-ccu.h>
-#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53";
- device_type = "cpu";
- reg = <0>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
- #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53";
- device_type = "cpu";
- reg = <1>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
- #cooling-cells = <2>;
- };
-
- cpu2: cpu@2 {
- compatible = "arm,cortex-a53";
- device_type = "cpu";
- reg = <2>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
- #cooling-cells = <2>;
- };
-
- cpu3: cpu@3 {
- compatible = "arm,cortex-a53";
- device_type = "cpu";
- reg = <3>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
- #cooling-cells = <2>;
- };
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- /*
- * 256 KiB reserved for Trusted Firmware-A (BL31).
- * This is added by BL31 itself, but some bootloaders fail
- * to propagate this into the DTB handed to kernels.
- */
- secmon@40000000 {
- reg = <0x0 0x40000000 0x0 0x40000>;
- no-map;
- };
- };
-
- osc24M: osc24M-clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "osc24M";
- };
-
- pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- arm,no-tick-in-suspend;
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x40000000>;
-
- syscon: syscon@3000000 {
- compatible = "allwinner,sun50i-h616-system-control";
- reg = <0x03000000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sram_c: sram@28000 {
- compatible = "mmio-sram";
- reg = <0x00028000 0x30000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x00028000 0x30000>;
- };
- };
-
- ccu: clock@3001000 {
- compatible = "allwinner,sun50i-h616-ccu";
- reg = <0x03001000 0x1000>;
- clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
- clock-names = "hosc", "losc", "iosc";
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- dma: dma-controller@3002000 {
- compatible = "allwinner,sun50i-h616-dma",
- "allwinner,sun50i-a100-dma";
- reg = <0x03002000 0x1000>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
- clock-names = "bus", "mbus";
- dma-channels = <16>;
- dma-requests = <49>;
- resets = <&ccu RST_BUS_DMA>;
- #dma-cells = <1>;
- };
-
- sid: efuse@3006000 {
- compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
- reg = <0x03006000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- ths_calibration: thermal-sensor-calibration@14 {
- reg = <0x14 0x8>;
- };
-
- cpu_speed_grade: cpu-speed-grade@0 {
- reg = <0x0 2>;
- };
- };
-
- watchdog: watchdog@30090a0 {
- compatible = "allwinner,sun50i-h616-wdt",
- "allwinner,sun6i-a31-wdt";
- reg = <0x030090a0 0x20>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc24M>;
- };
-
- pio: pinctrl@300b000 {
- compatible = "allwinner,sun50i-h616-pinctrl";
- reg = <0x0300b000 0x400>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
- clock-names = "apb", "hosc", "losc";
- gpio-controller;
- #gpio-cells = <3>;
- interrupt-controller;
- #interrupt-cells = <3>;
-
- ext_rgmii_pins: rgmii-pins {
- pins = "PI0", "PI1", "PI2", "PI3", "PI4",
- "PI5", "PI7", "PI8", "PI9", "PI10",
- "PI11", "PI12", "PI13", "PI14", "PI15",
- "PI16";
- function = "emac0";
- drive-strength = <40>;
- };
-
- i2c0_pins: i2c0-pins {
- pins = "PI5", "PI6";
- function = "i2c0";
- };
-
- i2c3_ph_pins: i2c3-ph-pins {
- pins = "PH4", "PH5";
- function = "i2c3";
- };
-
- ir_rx_pin: ir-rx-pin {
- pins = "PH10";
- function = "ir_rx";
- };
-
- mmc0_pins: mmc0-pins {
- pins = "PF0", "PF1", "PF2", "PF3",
- "PF4", "PF5";
- function = "mmc0";
- drive-strength = <30>;
- bias-pull-up;
- };
-
- /omit-if-no-ref/
- mmc1_pins: mmc1-pins {
- pins = "PG0", "PG1", "PG2", "PG3",
- "PG4", "PG5";
- function = "mmc1";
- drive-strength = <30>;
- bias-pull-up;
- };
-
- mmc2_pins: mmc2-pins {
- pins = "PC0", "PC1", "PC5", "PC6",
- "PC8", "PC9", "PC10", "PC11",
- "PC13", "PC14", "PC15", "PC16";
- function = "mmc2";
- drive-strength = <30>;
- bias-pull-up;
- };
-
- /omit-if-no-ref/
- spi0_pins: spi0-pins {
- pins = "PC0", "PC2", "PC4";
- function = "spi0";
- };
-
- /omit-if-no-ref/
- spi0_cs0_pin: spi0-cs0-pin {
- pins = "PC3";
- function = "spi0";
- };
-
- /omit-if-no-ref/
- spi1_pins: spi1-pins {
- pins = "PH6", "PH7", "PH8";
- function = "spi1";
- };
-
- /omit-if-no-ref/
- spi1_cs0_pin: spi1-cs0-pin {
- pins = "PH5";
- function = "spi1";
- };
-
- spdif_tx_pin: spdif-tx-pin {
- pins = "PH4";
- function = "spdif";
- };
-
- uart0_ph_pins: uart0-ph-pins {
- pins = "PH0", "PH1";
- function = "uart0";
- };
-
- /omit-if-no-ref/
- uart1_pins: uart1-pins {
- pins = "PG6", "PG7";
- function = "uart1";
- };
-
- /omit-if-no-ref/
- uart1_rts_cts_pins: uart1-rts-cts-pins {
- pins = "PG8", "PG9";
- function = "uart1";
- };
-
- /omit-if-no-ref/
- x32clk_fanout_pin: x32clk-fanout-pin {
- pins = "PG10";
- function = "clock";
- };
- };
-
- gic: interrupt-controller@3021000 {
- compatible = "arm,gic-400";
- reg = <0x03021000 0x1000>,
- <0x03022000 0x2000>,
- <0x03024000 0x2000>,
- <0x03026000 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- interrupt-controller;
- #interrupt-cells = <3>;
- };
-
- mmc0: mmc@4020000 {
- compatible = "allwinner,sun50i-h616-mmc",
- "allwinner,sun50i-a100-mmc";
- reg = <0x04020000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
- clock-names = "ahb", "mmc";
- resets = <&ccu RST_BUS_MMC0>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins>;
- status = "disabled";
- max-frequency = <150000000>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- mmc-ddr-3_3v;
- cap-sdio-irq;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc1: mmc@4021000 {
- compatible = "allwinner,sun50i-h616-mmc",
- "allwinner,sun50i-a100-mmc";
- reg = <0x04021000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
- clock-names = "ahb", "mmc";
- resets = <&ccu RST_BUS_MMC1>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
- status = "disabled";
- max-frequency = <150000000>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- mmc-ddr-3_3v;
- cap-sdio-irq;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc2: mmc@4022000 {
- compatible = "allwinner,sun50i-h616-emmc",
- "allwinner,sun50i-a100-emmc";
- reg = <0x04022000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
- clock-names = "ahb", "mmc";
- resets = <&ccu RST_BUS_MMC2>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins>;
- status = "disabled";
- max-frequency = <150000000>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- mmc-ddr-3_3v;
- cap-sdio-irq;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- uart0: serial@5000000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x05000000 0x400>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART0>;
- dmas = <&dma 14>, <&dma 14>;
- dma-names = "tx", "rx";
- resets = <&ccu RST_BUS_UART0>;
- status = "disabled";
- };
-
- uart1: serial@5000400 {
- compatible = "snps,dw-apb-uart";
- reg = <0x05000400 0x400>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART1>;
- dmas = <&dma 15>, <&dma 15>;
- dma-names = "tx", "rx";
- resets = <&ccu RST_BUS_UART1>;
- status = "disabled";
- };
-
- uart2: serial@5000800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x05000800 0x400>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART2>;
- dmas = <&dma 16>, <&dma 16>;
- dma-names = "tx", "rx";
- resets = <&ccu RST_BUS_UART2>;
- status = "disabled";
- };
-
- uart3: serial@5000c00 {
- compatible = "snps,dw-apb-uart";
- reg = <0x05000c00 0x400>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART3>;
- dmas = <&dma 17>, <&dma 17>;
- dma-names = "tx", "rx";
- resets = <&ccu RST_BUS_UART3>;
- status = "disabled";
- };
-
- uart4: serial@5001000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x05001000 0x400>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART4>;
- dmas = <&dma 18>, <&dma 18>;
- dma-names = "tx", "rx";
- resets = <&ccu RST_BUS_UART4>;
- status = "disabled";
- };
-
- uart5: serial@5001400 {
- compatible = "snps,dw-apb-uart";
- reg = <0x05001400 0x400>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART5>;
- dmas = <&dma 19>, <&dma 19>;
- dma-names = "tx", "rx";
- resets = <&ccu RST_BUS_UART5>;
- status = "disabled";
- };
-
- i2c0: i2c@5002000 {
- compatible = "allwinner,sun50i-h616-i2c",
- "allwinner,sun8i-v536-i2c",
- "allwinner,sun6i-a31-i2c";
- reg = <0x05002000 0x400>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_I2C0>;
- dmas = <&dma 43>, <&dma 43>;
- dma-names = "rx", "tx";
- resets = <&ccu RST_BUS_I2C0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1: i2c@5002400 {
- compatible = "allwinner,sun50i-h616-i2c",
- "allwinner,sun8i-v536-i2c",
- "allwinner,sun6i-a31-i2c";
- reg = <0x05002400 0x400>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_I2C1>;
- dmas = <&dma 44>, <&dma 44>;
- dma-names = "rx", "tx";
- resets = <&ccu RST_BUS_I2C1>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c2: i2c@5002800 {
- compatible = "allwinner,sun50i-h616-i2c",
- "allwinner,sun8i-v536-i2c",
- "allwinner,sun6i-a31-i2c";
- reg = <0x05002800 0x400>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_I2C2>;
- dmas = <&dma 45>, <&dma 45>;
- dma-names = "rx", "tx";
- resets = <&ccu RST_BUS_I2C2>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c3: i2c@5002c00 {
- compatible = "allwinner,sun50i-h616-i2c",
- "allwinner,sun8i-v536-i2c",
- "allwinner,sun6i-a31-i2c";
- reg = <0x05002c00 0x400>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_I2C3>;
- dmas = <&dma 46>, <&dma 46>;
- dma-names = "rx", "tx";
- resets = <&ccu RST_BUS_I2C3>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c4: i2c@5003000 {
- compatible = "allwinner,sun50i-h616-i2c",
- "allwinner,sun8i-v536-i2c",
- "allwinner,sun6i-a31-i2c";
- reg = <0x05003000 0x400>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_I2C4>;
- dmas = <&dma 47>, <&dma 47>;
- dma-names = "rx", "tx";
- resets = <&ccu RST_BUS_I2C4>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi0: spi@5010000 {
- compatible = "allwinner,sun50i-h616-spi",
- "allwinner,sun8i-h3-spi";
- reg = <0x05010000 0x1000>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
- clock-names = "ahb", "mod";
- dmas = <&dma 22>, <&dma 22>;
- dma-names = "rx", "tx";
- resets = <&ccu RST_BUS_SPI0>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi1: spi@5011000 {
- compatible = "allwinner,sun50i-h616-spi",
- "allwinner,sun8i-h3-spi";
- reg = <0x05011000 0x1000>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
- clock-names = "ahb", "mod";
- dmas = <&dma 23>, <&dma 23>;
- dma-names = "rx", "tx";
- resets = <&ccu RST_BUS_SPI1>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- emac0: ethernet@5020000 {
- compatible = "allwinner,sun50i-h616-emac0",
- "allwinner,sun50i-a64-emac";
- reg = <0x05020000 0x10000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&ccu CLK_BUS_EMAC0>;
- clock-names = "stmmaceth";
- resets = <&ccu RST_BUS_EMAC0>;
- reset-names = "stmmaceth";
- syscon = <&syscon>;
- status = "disabled";
-
- mdio0: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- spdif: spdif@5093000 {
- compatible = "allwinner,sun50i-h616-spdif";
- reg = <0x05093000 0x400>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
- clock-names = "apb", "spdif";
- resets = <&ccu RST_BUS_SPDIF>;
- dmas = <&dma 2>;
- dma-names = "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spdif_tx_pin>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- ths: thermal-sensor@5070400 {
- compatible = "allwinner,sun50i-h616-ths";
- reg = <0x05070400 0x400>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_THS>;
- clock-names = "bus";
- resets = <&ccu RST_BUS_THS>;
- nvmem-cells = <&ths_calibration>;
- nvmem-cell-names = "calibration";
- allwinner,sram = <&syscon>;
- #thermal-sensor-cells = <1>;
- };
-
- usbotg: usb@5100000 {
- compatible = "allwinner,sun50i-h616-musb",
- "allwinner,sun8i-h3-musb";
- reg = <0x05100000 0x0400>;
- clocks = <&ccu CLK_BUS_OTG>;
- resets = <&ccu RST_BUS_OTG>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mc";
- phys = <&usbphy 0>;
- phy-names = "usb";
- extcon = <&usbphy 0>;
- status = "disabled";
- };
-
- usbphy: phy@5100400 {
- compatible = "allwinner,sun50i-h616-usb-phy";
- reg = <0x05100400 0x24>,
- <0x05101800 0x14>,
- <0x05200800 0x14>,
- <0x05310800 0x14>,
- <0x05311800 0x14>;
- reg-names = "phy_ctrl",
- "pmu0",
- "pmu1",
- "pmu2",
- "pmu3";
- clocks = <&ccu CLK_USB_PHY0>,
- <&ccu CLK_USB_PHY1>,
- <&ccu CLK_USB_PHY2>,
- <&ccu CLK_USB_PHY3>,
- <&ccu CLK_BUS_EHCI2>;
- clock-names = "usb0_phy",
- "usb1_phy",
- "usb2_phy",
- "usb3_phy",
- "pmu2_clk";
- resets = <&ccu RST_USB_PHY0>,
- <&ccu RST_USB_PHY1>,
- <&ccu RST_USB_PHY2>,
- <&ccu RST_USB_PHY3>;
- reset-names = "usb0_reset",
- "usb1_reset",
- "usb2_reset",
- "usb3_reset";
- status = "disabled";
- #phy-cells = <1>;
- };
-
- ehci0: usb@5101000 {
- compatible = "allwinner,sun50i-h616-ehci",
- "generic-ehci";
- reg = <0x05101000 0x100>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_OHCI0>,
- <&ccu CLK_BUS_EHCI0>,
- <&ccu CLK_USB_OHCI0>;
- resets = <&ccu RST_BUS_OHCI0>,
- <&ccu RST_BUS_EHCI0>;
- phys = <&usbphy 0>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci0: usb@5101400 {
- compatible = "allwinner,sun50i-h616-ohci",
- "generic-ohci";
- reg = <0x05101400 0x100>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_OHCI0>,
- <&ccu CLK_USB_OHCI0>;
- resets = <&ccu RST_BUS_OHCI0>;
- phys = <&usbphy 0>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ehci1: usb@5200000 {
- compatible = "allwinner,sun50i-h616-ehci",
- "generic-ehci";
- reg = <0x05200000 0x100>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_OHCI1>,
- <&ccu CLK_BUS_EHCI1>,
- <&ccu CLK_USB_OHCI1>;
- resets = <&ccu RST_BUS_OHCI1>,
- <&ccu RST_BUS_EHCI1>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci1: usb@5200400 {
- compatible = "allwinner,sun50i-h616-ohci",
- "generic-ohci";
- reg = <0x05200400 0x100>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_OHCI1>,
- <&ccu CLK_USB_OHCI1>;
- resets = <&ccu RST_BUS_OHCI1>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ehci2: usb@5310000 {
- compatible = "allwinner,sun50i-h616-ehci",
- "generic-ehci";
- reg = <0x05310000 0x100>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_OHCI2>,
- <&ccu CLK_BUS_EHCI2>,
- <&ccu CLK_USB_OHCI2>;
- resets = <&ccu RST_BUS_OHCI2>,
- <&ccu RST_BUS_EHCI2>;
- phys = <&usbphy 2>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci2: usb@5310400 {
- compatible = "allwinner,sun50i-h616-ohci",
- "generic-ohci";
- reg = <0x05310400 0x100>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_OHCI2>,
- <&ccu CLK_USB_OHCI2>;
- resets = <&ccu RST_BUS_OHCI2>;
- phys = <&usbphy 2>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ehci3: usb@5311000 {
- compatible = "allwinner,sun50i-h616-ehci",
- "generic-ehci";
- reg = <0x05311000 0x100>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_OHCI3>,
- <&ccu CLK_BUS_EHCI3>,
- <&ccu CLK_USB_OHCI3>;
- resets = <&ccu RST_BUS_OHCI3>,
- <&ccu RST_BUS_EHCI3>;
- phys = <&usbphy 3>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci3: usb@5311400 {
- compatible = "allwinner,sun50i-h616-ohci",
- "generic-ohci";
- reg = <0x05311400 0x100>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_OHCI3>,
- <&ccu CLK_USB_OHCI3>;
- resets = <&ccu RST_BUS_OHCI3>;
- phys = <&usbphy 3>;
- phy-names = "usb";
- status = "disabled";
- };
-
- rtc: rtc@7000000 {
- compatible = "allwinner,sun50i-h616-rtc";
- reg = <0x07000000 0x400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
- <&ccu CLK_PLL_SYSTEM_32K>;
- clock-names = "bus", "hosc",
- "pll-32k";
- #clock-cells = <1>;
- };
-
- r_ccu: clock@7010000 {
- compatible = "allwinner,sun50i-h616-r-ccu";
- reg = <0x07010000 0x210>;
- clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
- <&ccu CLK_PLL_PERIPH0>;
- clock-names = "hosc", "losc", "iosc", "pll-periph";
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- nmi_intc: interrupt-controller@7010320 {
- compatible = "allwinner,sun50i-h616-nmi",
- "allwinner,sun9i-a80-nmi";
- reg = <0x07010320 0xc>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- r_pio: pinctrl@7022000 {
- compatible = "allwinner,sun50i-h616-r-pinctrl";
- reg = <0x07022000 0x400>;
- clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
- <&rtc CLK_OSC32K>;
- clock-names = "apb", "hosc", "losc";
- gpio-controller;
- #gpio-cells = <3>;
-
- /omit-if-no-ref/
- r_i2c_pins: r-i2c-pins {
- pins = "PL0", "PL1";
- function = "s_i2c";
- };
-
- r_rsb_pins: r-rsb-pins {
- pins = "PL0", "PL1";
- function = "s_rsb";
- };
- };
-
- ir: ir@7040000 {
- compatible = "allwinner,sun50i-h616-ir",
- "allwinner,sun6i-a31-ir";
- reg = <0x07040000 0x400>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&r_ccu CLK_R_APB1_IR>,
- <&r_ccu CLK_IR>;
- clock-names = "apb", "ir";
- resets = <&r_ccu RST_R_APB1_IR>;
- pinctrl-names = "default";
- pinctrl-0 = <&ir_rx_pin>;
- status = "disabled";
- };
-
- r_i2c: i2c@7081400 {
- compatible = "allwinner,sun50i-h616-i2c",
- "allwinner,sun8i-v536-i2c",
- "allwinner,sun6i-a31-i2c";
- reg = <0x07081400 0x400>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&r_ccu CLK_R_APB2_I2C>;
- dmas = <&dma 48>, <&dma 48>;
- dma-names = "rx", "tx";
- resets = <&r_ccu RST_R_APB2_I2C>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- r_rsb: rsb@7083000 {
- compatible = "allwinner,sun50i-h616-rsb",
- "allwinner,sun8i-a23-rsb";
- reg = <0x07083000 0x400>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&r_ccu CLK_R_APB2_RSB>;
- clock-frequency = <3000000>;
- resets = <&r_ccu RST_R_APB2_RSB>;
- pinctrl-names = "default";
- pinctrl-0 = <&r_rsb_pins>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- thermal-zones {
- cpu-thermal {
- polling-delay-passive = <500>;
- polling-delay = <1000>;
- thermal-sensors = <&ths 2>;
- sustainable-power = <1000>;
-
- trips {
- cpu_threshold: cpu-trip-0 {
- temperature = <60000>;
- type = "passive";
- hysteresis = <0>;
- };
- cpu_target: cpu-trip-1 {
- temperature = <70000>;
- type = "passive";
- hysteresis = <0>;
- };
- cpu_critical: cpu-trip-2 {
- temperature = <110000>;
- type = "critical";
- hysteresis = <0>;
- };
- };
- };
-
- gpu-thermal {
- polling-delay-passive = <500>;
- polling-delay = <1000>;
- thermal-sensors = <&ths 0>;
- sustainable-power = <1100>;
-
- trips {
- gpu_temp_critical: gpu-trip-0 {
- temperature = <110000>;
- type = "critical";
- hysteresis = <0>;
- };
- };
- };
-
- ve-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
- thermal-sensors = <&ths 1>;
-
- trips {
- ve_temp_critical: ve-trip-0 {
- temperature = <110000>;
- type = "critical";
- hysteresis = <0>;
- };
- };
- };
-
- ddr-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
- thermal-sensors = <&ths 3>;
-
- trips {
- ddr_temp_critical: ddr-trip-0 {
- temperature = <110000>;
- type = "critical";
- hysteresis = <0>;
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi b/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi
deleted file mode 100644
index e92d150..0000000
--- a/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) Jisheng Zhang <jszhang@kernel.org>
- */
-
-#include "sun50i-h616.dtsi"
-#include "sun50i-h616-cpu-opp.dtsi"
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins>;
- vmmc-supply = <®_dldo1>;
- vqmmc-supply = <®_aldo1>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- status = "okay";
-};
-
-&r_i2c {
- status = "okay";
-
- axp313: pmic@36 {
- compatible = "x-powers,axp313a";
- reg = <0x36>;
- #interrupt-cells = <1>;
- interrupt-controller;
-
- regulators {
- reg_aldo1: aldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-1v8-pll";
- };
-
- reg_dldo1: dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3-io";
- };
-
- reg_dcdc1: dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <990000>;
- regulator-name = "vdd-gpu-sys";
- };
-
- reg_dcdc2: dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-cpu";
- };
-
- reg_dcdc3: dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-dram";
- };
- };
- };
-};
-
-&pio {
- vcc-pc-supply = <®_dldo1>;
- vcc-pf-supply = <®_dldo1>;
- vcc-pg-supply = <®_aldo1>;
- vcc-ph-supply = <®_dldo1>;
- vcc-pi-supply = <®_dldo1>;
-};
diff --git a/arch/arm/dts/sun50i-h618-longanpi-3h.dts b/arch/arm/dts/sun50i-h618-longanpi-3h.dts
deleted file mode 100644
index 18b29c6..0000000
--- a/arch/arm/dts/sun50i-h618-longanpi-3h.dts
+++ /dev/null
@@ -1,144 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) Jisheng Zhang <jszhang@kernel.org>
- */
-
-/dts-v1/;
-
-#include "sun50i-h618-longan-module-3h.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Sipeed Longan Pi 3H";
- compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618";
-
- aliases {
- ethernet0 = &emac0;
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- color = <LED_COLOR_ID_ORANGE>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <0>;
- gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
- };
-
- led-1 {
- color = <LED_COLOR_ID_ORANGE>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <1>;
- gpios = <&pio 6 4 GPIO_ACTIVE_LOW>; /* PG4 */
- };
- };
-
- reg_vcc5v: regulator-vcc5v {
- /* board wide 5V supply directly from the USB-C socket */
- compatible = "regulator-fixed";
- regulator-name = "vcc-5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- reg_vcc3v3: regulator-vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- vin-supply = <®_vcc5v>;
- };
-};
-
-&axp313 {
- vin1-supply = <®_vcc5v>;
- vin2-supply = <®_vcc5v>;
- vin3-supply = <®_vcc5v>;
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-/* WiFi & BT combo module is connected to this Host */
-&ehci3 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&emac0 {
- pinctrl-names = "default";
- pinctrl-0 = <&ext_rgmii_pins>;
- phy-mode = "rgmii";
- phy-handle = <&ext_rgmii_phy>;
- allwinner,rx-delay-ps = <3100>;
- allwinner,tx-delay-ps = <700>;
- phy-supply = <®_vcc3v3>;
- status = "okay";
-};
-
-&mdio0 {
- ext_rgmii_phy: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
-
-&mmc0 {
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- vmmc-supply = <®_vcc3v3>;
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&usbotg {
- /*
- * PHY0 pins are connected to a USB-C socket, but a role switch
- * is not implemented: both CC pins are pulled to GND.
- * The VBUS pins power the device, so a fixed peripheral mode
- * is the best choice.
- * The board can be powered via GPIOs, in this case port0 *can*
- * act as a host (with a cable/adapter ignoring CC), as VBUS is
- * then provided by the GPIOs. Any user of this setup would
- * need to adjust the DT accordingly: dr_mode set to "host",
- * enabling OHCI0 and EHCI0.
- */
- dr_mode = "peripheral";
- status = "okay";
-};
-
-&usbphy {
- usb1_vbus-supply = <®_vcc5v>;
- usb2_vbus-supply = <®_vcc5v>;
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts b/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts
deleted file mode 100644
index 6a4f0da..0000000
--- a/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts
+++ /dev/null
@@ -1,181 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2023 Arm Ltd.
- */
-
-/dts-v1/;
-
-#include "sun50i-h616.dtsi"
-#include "sun50i-h616-cpu-opp.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "OrangePi Zero 2W";
- compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h618";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
- };
- };
-
- reg_vcc5v: vcc5v {
- /* board wide 5V supply directly from the USB-C socket */
- compatible = "regulator-fixed";
- regulator-name = "vcc-5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- reg_vcc3v3: vcc3v3 {
- /* SY8089 DC/DC converter */
- compatible = "regulator-fixed";
- regulator-name = "vcc-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <®_vcc5v>;
- regulator-always-on;
- };
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&ehci1 {
- status = "okay";
-};
-
-/* USB 2 & 3 are on the FPC connector (or the exansion board) */
-
-&mmc0 {
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- bus-width = <4>;
- vmmc-supply = <®_vcc3v3>;
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&pio {
- vcc-pc-supply = <®_dldo1>;
- vcc-pf-supply = <®_dldo1>; /* internally via VCC-IO */
- vcc-pg-supply = <®_aldo1>;
- vcc-ph-supply = <®_dldo1>; /* internally via VCC-IO */
- vcc-pi-supply = <®_dldo1>;
-};
-
-&r_i2c {
- status = "okay";
-
- axp313: pmic@36 {
- compatible = "x-powers,axp313a";
- reg = <0x36>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupt-parent = <&pio>;
- interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */
-
- vin1-supply = <®_vcc5v>;
- vin2-supply = <®_vcc5v>;
- vin3-supply = <®_vcc5v>;
-
- regulators {
- /* Supplies VCC-PLL and DRAM */
- reg_aldo1: aldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8";
- };
-
- /* Supplies VCC-IO, so needs to be always on. */
- reg_dldo1: dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3";
- };
-
- reg_dcdc1: dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <990000>;
- regulator-name = "vdd-gpu-sys";
- };
-
- reg_dcdc2: dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-cpu";
- };
-
- reg_dcdc3: dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-dram";
- };
- };
- };
-};
-
-&spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_ph_pins>;
- status = "okay";
-};
-
-&usbotg {
- /*
- * PHY0 pins are connected to a USB-C socket, but a role switch
- * is not implemented: both CC pins are pulled to GND.
- * The VBUS pins power the device, so a fixed peripheral mode
- * is the best choice.
- * The board can be powered via GPIOs, in this case port0 *can*
- * act as a host (with a cable/adapter ignoring CC), as VBUS is
- * then provided by the GPIOs. Any user of this setup would
- * need to adjust the DT accordingly: dr_mode set to "host",
- * enabling OHCI0 and EHCI0.
- */
- dr_mode = "peripheral";
- status = "okay";
-};
-
-&usbphy {
- usb1_vbus-supply = <®_vcc5v>;
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts
deleted file mode 100644
index e1cd757..0000000
--- a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2023 Arm Ltd.
- */
-
-/dts-v1/;
-
-#include "sun50i-h616-orangepi-zero.dtsi"
-#include "sun50i-h616-cpu-opp.dtsi"
-
-/ {
- model = "OrangePi Zero3";
- compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&emac0 {
- allwinner,tx-delay-ps = <700>;
- phy-mode = "rgmii-rxid";
- phy-supply = <®_dldo1>;
-};
-
-&ext_rgmii_phy {
- motorcomm,clk-out-frequency-hz = <125000000>;
-};
-
-&mmc0 {
- /*
- * The schematic shows the card detect pin wired up to PF6, via an
- * inverter, but it just doesn't work.
- */
- broken-cd;
- vmmc-supply = <®_dldo1>;
-};
-
-&r_i2c {
- status = "okay";
-
- axp313: pmic@36 {
- compatible = "x-powers,axp313a";
- reg = <0x36>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupt-parent = <&pio>;
- interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */
-
- vin1-supply = <®_vcc5v>;
- vin2-supply = <®_vcc5v>;
- vin3-supply = <®_vcc5v>;
-
- regulators {
- /* Supplies VCC-PLL, so needs to be always on. */
- reg_aldo1: aldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8";
- };
-
- /* Supplies VCC-IO, so needs to be always on. */
- reg_dldo1: dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3";
- };
-
- reg_dcdc1: dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <990000>;
- regulator-name = "vdd-gpu-sys";
- };
-
- reg_dcdc2: dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-cpu";
- };
-
- reg_dcdc3: dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-dram";
- };
- };
- };
-};
-
-&pio {
- vcc-pc-supply = <®_dldo1>;
- vcc-pf-supply = <®_dldo1>;
- vcc-pg-supply = <®_aldo1>;
- vcc-ph-supply = <®_dldo1>;
- vcc-pi-supply = <®_dldo1>;
-};
diff --git a/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts b/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts
deleted file mode 100644
index d6631bf..0000000
--- a/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts
+++ /dev/null
@@ -1,189 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2023 Arm Ltd.
- */
-
-/dts-v1/;
-
-#include "sun50i-h616.dtsi"
-#include "sun50i-h616-cpu-opp.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- model = "Transpeed 8K618-T";
- compatible = "transpeed,8k618-t", "allwinner,sun50i-h618";
-
- aliases {
- ethernet1 = &sdio_wifi;
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- reg_vcc5v: vcc5v {
- /* board wide 5V supply directly from the DC input */
- compatible = "regulator-fixed";
- regulator-name = "vcc-5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- reg_vcc3v3: vcc3v3 {
- /* discrete 3.3V regulator */
- compatible = "regulator-fixed";
- regulator-name = "vcc-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- wifi_pwrseq: pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rtc CLK_OSC32K_FANOUT>;
- clock-names = "ext_clock";
- pinctrl-0 = <&x32clk_fanout_pin>;
- pinctrl-names = "default";
- reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
- };
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ir {
- status = "okay";
-};
-
-&mmc0 {
- vmmc-supply = <®_dldo1>;
- cd-gpios = <&pio 8 16 GPIO_ACTIVE_LOW>; /* PI16 */
- bus-width = <4>;
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_dldo1>;
- vqmmc-supply = <®_aldo1>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- sdio_wifi: wifi@1 {
- reg = <1>;
- };
-};
-
-&mmc2 {
- vmmc-supply = <®_dldo1>;
- vqmmc-supply = <®_aldo1>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- status = "okay";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&r_i2c {
- status = "okay";
-
- axp313: pmic@36 {
- compatible = "x-powers,axp313a";
- reg = <0x36>;
- #interrupt-cells = <1>;
- interrupt-controller;
-
- vin1-supply = <®_vcc5v>;
- vin2-supply = <®_vcc5v>;
- vin3-supply = <®_vcc5v>;
-
- regulators {
- reg_aldo1: aldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-1v8-pll";
- };
-
- reg_dldo1: dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3-io-mmc";
- };
-
- reg_dcdc1: dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <990000>;
- regulator-name = "vdd-gpu-sys";
- };
-
- reg_dcdc2: dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-cpu";
- };
-
- reg_dcdc3: dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1360000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-dram";
- };
- };
- };
-};
-
-&pio {
- vcc-pc-supply = <®_aldo1>;
- vcc-pg-supply = <®_dldo1>;
- vcc-ph-supply = <®_dldo1>;
- vcc-pi-supply = <®_dldo1>;
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_ph_pins>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&usbotg {
- dr_mode = "host"; /* USB A type receptable */
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts
deleted file mode 100644
index ee30584..0000000
--- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts
+++ /dev/null
@@ -1,327 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>.
- */
-
-/dts-v1/;
-
-#include "sun50i-h616.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Anbernic RG35XX 2024";
- chassis-type = "handset";
- compatible = "anbernic,rg35xx-2024", "allwinner,sun50i-h700";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio_keys_gamepad: gpio-keys-gamepad {
- compatible = "gpio-keys";
-
- button-a {
- label = "Action-Pad A";
- gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_EAST>;
- };
-
- button-b {
- label = "Action-Pad B";
- gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_SOUTH>;
- };
-
- button-down {
- label = "D-Pad Down";
- gpios = <&pio 4 0 GPIO_ACTIVE_LOW>; /* PE0 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_DPAD_DOWN>;
- };
-
- button-l1 {
- label = "Key L1";
- gpios = <&pio 0 10 GPIO_ACTIVE_LOW>; /* PA10 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_TL>;
- };
-
- button-l2 {
- label = "Key L2";
- gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_TL2>;
- };
-
- button-left {
- label = "D-Pad left";
- gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_DPAD_LEFT>;
- };
-
- button-menu {
- label = "Key Menu";
- gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_MODE>;
- };
-
- button-r1 {
- label = "Key R1";
- gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_TR>;
- };
-
- button-r2 {
- label = "Key R2";
- gpios = <&pio 0 7 GPIO_ACTIVE_LOW>; /* PA7 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_TR2>;
- };
-
- button-right {
- label = "D-Pad Right";
- gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_DPAD_RIGHT>;
- };
-
- button-select {
- label = "Key Select";
- gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_SELECT>;
- };
- button-start {
- label = "Key Start";
- gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_START>;
- };
-
- button-up {
- label = "D-Pad Up";
- gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_DPAD_UP>;
- };
-
- button-x {
- label = "Action-Pad X";
- gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_NORTH>;
- };
-
- button-y {
- label = "Action Pad Y";
- gpios = <&pio 0 2 GPIO_ACTIVE_LOW>; /* PA2 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_WEST>;
- };
- };
-
- gpio-keys-volume {
- compatible = "gpio-keys";
- autorepeat;
-
- button-vol-up {
- label = "Key Volume Up";
- gpios = <&pio 4 1 GPIO_ACTIVE_LOW>; /* PE1 */
- linux,input-type = <EV_KEY>;
- linux,code = <KEY_VOLUMEUP>;
- };
-
- button-vol-down {
- label = "Key Volume Down";
- gpios = <&pio 4 2 GPIO_ACTIVE_LOW>; /* PE2 */
- linux,input-type = <EV_KEY>;
- linux,code = <KEY_VOLUMEDOWN>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */
- default-state = "on";
- };
- };
-
- reg_vcc5v: regulator-vcc5v { /* USB-C power input */
- compatible = "regulator-fixed";
- regulator-name = "vcc-5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc1>;
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&mmc0 {
- vmmc-supply = <®_cldo3>;
- disable-wp;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- bus-width = <4>;
- status = "okay";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&pio {
- vcc-pa-supply = <®_cldo3>;
- vcc-pc-supply = <®_cldo3>;
- vcc-pe-supply = <®_cldo3>;
- vcc-pf-supply = <®_cldo3>;
- vcc-pg-supply = <®_aldo4>;
- vcc-ph-supply = <®_cldo3>;
- vcc-pi-supply = <®_cldo3>;
-};
-
-&r_rsb {
- status = "okay";
-
- axp717: pmic@3a3 {
- compatible = "x-powers,axp717";
- reg = <0x3a3>;
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&nmi_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- vin1-supply = <®_vcc5v>;
- vin2-supply = <®_vcc5v>;
- vin3-supply = <®_vcc5v>;
- vin4-supply = <®_vcc5v>;
-
- regulators {
- reg_dcdc1: dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-cpu";
- };
-
- reg_dcdc2: dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <940000>;
- regulator-max-microvolt = <940000>;
- regulator-name = "vdd-gpu-sys";
- };
-
- reg_dcdc3: dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-dram";
- };
-
- reg_aldo1: aldo1 {
- /* 1.8v - unused */
- };
-
- reg_aldo2: aldo2 {
- /* 1.8v - unused */
- };
-
- reg_aldo3: aldo3 {
- /* 1.8v - unused */
- };
-
- reg_aldo4: aldo4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
- };
-
- reg_bldo1: bldo1 {
- /* 1.8v - unused */
- };
-
- reg_bldo2: bldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pll";
- };
-
- reg_bldo3: bldo3 {
- /* 2.8v - unused */
- };
-
- reg_bldo4: bldo4 {
- /* 1.2v - unused */
- };
-
- reg_cldo1: cldo1 {
- /* 3.3v - audio codec - not yet implemented */
- };
-
- reg_cldo2: cldo2 {
- /* 3.3v - unused */
- };
-
- reg_cldo3: cldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-io";
- };
-
- reg_cldo4: cldo4 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi";
- };
-
- reg_boost: boost {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5200000>;
- regulator-name = "boost";
- };
-
- reg_cpusldo: cpusldo {
- /* unused */
- };
- };
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_ph_pins>;
- status = "okay";
-};
-
-/* the AXP717 has USB type-C role switch functionality, not yet described by the binding */
-&usbotg {
- dr_mode = "peripheral"; /* USB type-C receptable */
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts
deleted file mode 100644
index 6303625..0000000
--- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts
+++ /dev/null
@@ -1,36 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>.
- * Copyright (C) 2024 Chris Morgan <macroalpha82@gmail.com>.
- */
-
-#include "sun50i-h700-anbernic-rg35xx-plus.dts"
-
-/ {
- model = "Anbernic RG35XX H";
- compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700";
-};
-
-&gpio_keys_gamepad {
- button-thumbl {
- label = "GPIO Thumb Left";
- gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_THUMBL>;
- };
-
- button-thumbr {
- label = "GPIO Thumb Right";
- gpios = <&pio 4 9 GPIO_ACTIVE_LOW>; /* PE9 */
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_THUMBR>;
- };
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts
deleted file mode 100644
index 60a8e49..0000000
--- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>.
- */
-
-#include "sun50i-h700-anbernic-rg35xx-2024.dts"
-
-/ {
- model = "Anbernic RG35XX Plus";
- compatible = "anbernic,rg35xx-plus", "allwinner,sun50i-h700";
-
- wifi_pwrseq: pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rtc CLK_OSC32K_FANOUT>;
- clock-names = "ext_clock";
- pinctrl-0 = <&x32clk_fanout_pin>;
- pinctrl-names = "default";
- post-power-on-delay-ms = <200>;
- reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
- };
-};
-
-/* SDIO WiFi RTL8821CS */
-&mmc1 {
- vmmc-supply = <®_cldo4>;
- vqmmc-supply = <®_aldo4>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- sdio_wifi: wifi@1 {
- reg = <1>;
- interrupt-parent = <&pio>;
- interrupts = <6 15 IRQ_TYPE_LEVEL_LOW>; /* PG15 */
- interrupt-names = "host-wake";
- };
-};
-
-/* Bluetooth RTL8821CS */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt";
- device-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
- enable-gpios = <&pio 6 19 GPIO_ACTIVE_HIGH>; /* PG19 */
- host-wake-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16 */
- };
-};
diff --git a/arch/arm/dts/tegra-u-boot.dtsi b/arch/arm/dts/tegra-u-boot.dtsi
index b3d0dec..c200f2d 100644
--- a/arch/arm/dts/tegra-u-boot.dtsi
+++ b/arch/arm/dts/tegra-u-boot.dtsi
@@ -19,6 +19,27 @@
};
};
+#ifdef CONFIG_MULTI_DTB_FIT
+ image2 {
+ filename = "u-boot-dtb-tegra.bin";
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+ u-boot-nodtb {
+ offset = <(U_BOOT_OFFSET)>;
+ };
+ fit-dtb {
+#ifdef CONFIG_MULTI_DTB_FIT_LZO
+ filename = "fit-dtb.blob.lzo";
+#elif CONFIG_MULTI_DTB_FIT_GZIP
+ filename = "fit-dtb.blob.gz";
+#else
+ filename = "fit-dtb.blob";
+#endif
+ type = "blob";
+ };
+ };
+#else
/* Same as image1 - some tools still expect the -dtb suffix */
image2 {
filename = "u-boot-dtb-tegra.bin";
@@ -29,6 +50,7 @@
offset = <(U_BOOT_OFFSET)>;
};
};
+#endif
image3 {
filename = "u-boot-nodtb-tegra.bin";
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 7a4e097..a399c94 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -68,8 +68,9 @@
/* These are the available SKUs (product types) for Tegra */
enum {
- SKU_ID_T20_7 = 0x7,
+ SKU_ID_AP20 = 0x7,
SKU_ID_T20 = 0x8,
+ SKU_ID_AP20H = 0xf,
SKU_ID_T25SE = 0x14,
SKU_ID_AP25 = 0x17,
SKU_ID_T25 = 0x18,
diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h
index 6e6ea14..2ae109a 100644
--- a/arch/arm/include/asm/arch-tegra/usb.h
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -336,10 +336,13 @@
#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
#define UTMIP_XCVR_HSSLEW_MSB_MASK \
(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
-#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
-#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
-#define UTMIP_XCVR_SETUP_SHIFT 0
-#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
+
+#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
+#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22)
+#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
+#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
+#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
+#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25)
/* USBx_UTMIP_XCVR_CFG1_0 */
#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h
index 2e8b335..0541406 100644
--- a/arch/arm/include/asm/arch-tegra30/funcmux.h
+++ b/arch/arm/include/asm/arch-tegra30/funcmux.h
@@ -16,5 +16,6 @@
/* UART configs */
FUNCMUX_UART1_ULPI = 0,
+ FUNCMUX_UART5_SDMMC1 = 1,
};
#endif /* _TEGRA30_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h
index d4ac567..19d1269 100644
--- a/arch/arm/include/asm/mach-imx/ele_api.h
+++ b/arch/arm/include/asm/mach-imx/ele_api.h
@@ -47,6 +47,8 @@
#define ELE_ATTEST_REQ (0xDB)
#define ELE_RELEASE_PATCH_REQ (0xDC)
#define ELE_OTP_SEQ_SWITH_REQ (0xDD)
+#define ELE_WRITE_SHADOW_REQ (0xF2)
+#define ELE_READ_SHADOW_REQ (0xF3)
/* ELE failure indications */
#define ELE_ROM_PING_FAILURE_IND (0x0A)
@@ -154,4 +156,6 @@
int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response);
int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response);
int ele_start_rng(void);
+int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response);
+int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response);
#endif
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index ed44df3..324e010 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -345,9 +345,9 @@
u16 lc;
err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
- if (err != SC_ERR_NONE) {
+ if (err) {
printf("Error in get lifecycle\n");
- return -EIO;
+ return err;
}
if (lc != 0x20) {
@@ -357,9 +357,9 @@
}
err = sc_seco_forward_lifecycle(-1, 16);
- if (err != SC_ERR_NONE) {
+ if (err) {
printf("Error in forward lifecycle to OEM closed\n");
- return -EIO;
+ return err;
}
return 0;
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 2ff4ff3..37a5473 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -48,7 +48,7 @@
{
sc_pm_reset_reason_t reason;
- if (sc_pm_reset_reason(-1, &reason) != SC_ERR_NONE)
+ if (sc_pm_reset_reason(-1, &reason))
return "Unknown reset";
switch (reason) {
@@ -160,6 +160,7 @@
sc_faddr_t tcml_addr;
u32 tcml_size = SZ_128K;
ulong addr;
+ int ret;
switch (core_id) {
case 0:
@@ -187,10 +188,12 @@
printf("Power on M4 and MU\n");
- if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
- return -EIO;
+ ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON);
+ if (ret)
+ return ret;
- if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+ ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON);
+ if (ret)
return -EIO;
printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
@@ -199,7 +202,8 @@
memcpy((void *)tcml_addr, (void *)addr, tcml_size);
printf("Start M4 %u\n", core_id);
- if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
+ ret = sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr);
+ if (ret)
return -EIO;
printf("bootaux complete\n");
@@ -214,6 +218,7 @@
sc_faddr_t aux_core_ram;
u32 size;
ulong addr;
+ int ret;
switch (core_id) {
case 0:
@@ -242,20 +247,23 @@
printf("Power on aux core %d\n", core_id);
- if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
- return -EIO;
+ ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON);
+ if (ret)
+ return ret;
if (mu_rsrc != SC_R_NONE) {
- if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+ ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON);
+ if (ret)
return -EIO;
}
if (core_id == 1) {
struct power_domain pd;
- if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) {
+ ret = sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false);
+ if (ret) {
printf("Error enable clock\n");
- return -EIO;
+ return ret;
}
if (!imx8_power_domain_lookup_name("audio_sai0", &pd)) {
@@ -286,8 +294,9 @@
printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
- if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE)
- return -EIO;
+ ret = sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram);
+ if (ret)
+ return ret;
printf("bootaux complete\n");
return 0;
@@ -313,7 +322,7 @@
return 0;
}
- if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE)
+ if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode))
return 0;
if (power_mode != SC_PM_PW_MODE_OFF)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index d1fdaec..9d1fabe 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -197,6 +197,7 @@
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MP_DH_DHCOM_PDK2
bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 1766681..8065161 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -108,6 +108,23 @@
default 0x0
help
TPR12 value from vendor DRAM settings.
+
+choice
+ prompt "H616 PHY pin mapping selection"
+ default DRAM_SUN50I_H616_PHY_ADDR_MAP_0
+
+config DRAM_SUN50I_H616_PHY_ADDR_MAP_0
+ bool "H313/H616/H618"
+ help
+ The pin mapping selection used by the H313, H616, H618, and
+ possibly other dies which use the H616 DRAM controller.
+
+config DRAM_SUN50I_H616_PHY_ADDR_MAP_1
+ bool "H700"
+ help
+ The pin mapping selection used by the H700 and possibly other
+ dies which use the H616 DRAM controller.
+endchoice
endif
config SUN6I_PRCM
@@ -437,6 +454,7 @@
select ARM64
select DRAM_SUN50I_H616
select SUN50I_GEN_H6
+ imply OF_UPSTREAM
endchoice
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 37c139e..863c4f1 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -55,8 +55,8 @@
writel_relaxed(cfg1, &mctl_com->master[port].cfg1);
}
-#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
- mbus_configure_port(port, bwlimit, false, \
+#define MBUS_CONF(port, priority, qos, acs, bwl0, bwl1, bwl2) \
+ mbus_configure_port(port, true, priority, \
MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
static void mctl_set_master_priority(void)
@@ -68,24 +68,25 @@
writel(399, &mctl_com->tmr);
writel(BIT(16), &mctl_com->bwcr);
- MBUS_CONF( 0, true, HIGHEST, 0, 256, 128, 100);
- MBUS_CONF( 1, true, HIGH, 0, 1536, 1400, 256);
- MBUS_CONF( 2, true, HIGHEST, 0, 512, 256, 96);
- MBUS_CONF( 3, true, HIGH, 0, 256, 100, 80);
- MBUS_CONF( 4, true, HIGH, 2, 8192, 5500, 5000);
- MBUS_CONF( 5, true, HIGH, 2, 100, 64, 32);
- MBUS_CONF( 6, true, HIGH, 2, 100, 64, 32);
- MBUS_CONF( 8, true, HIGH, 0, 256, 128, 64);
- MBUS_CONF(11, true, HIGH, 0, 256, 128, 100);
- MBUS_CONF(14, true, HIGH, 0, 1024, 256, 64);
- MBUS_CONF(16, true, HIGHEST, 6, 8192, 2800, 2400);
- MBUS_CONF(21, true, HIGHEST, 6, 2048, 768, 512);
- MBUS_CONF(25, true, HIGHEST, 0, 100, 64, 32);
- MBUS_CONF(26, true, HIGH, 2, 8192, 5500, 5000);
- MBUS_CONF(37, true, HIGH, 0, 256, 128, 64);
- MBUS_CONF(38, true, HIGH, 2, 100, 64, 32);
- MBUS_CONF(39, true, HIGH, 2, 8192, 5500, 5000);
- MBUS_CONF(40, true, HIGH, 2, 100, 64, 32);
+ MBUS_CONF(0, false, HIGHEST, 0, 256, 128, 100);
+ MBUS_CONF(1, false, HIGH, 0, 1536, 1400, 256);
+ MBUS_CONF(2, false, HIGHEST, 0, 512, 256, 96);
+ MBUS_CONF(3, false, HIGH, 0, 256, 100, 80);
+ MBUS_CONF(4, false, HIGH, 2, 8192, 5500, 5000);
+ MBUS_CONF(5, false, HIGH, 2, 100, 64, 32);
+ MBUS_CONF(6, false, HIGH, 2, 100, 64, 32);
+ MBUS_CONF(8, false, HIGH, 0, 256, 128, 64);
+ MBUS_CONF(11, false, HIGH, 0, 256, 128, 100);
+ MBUS_CONF(14, false, HIGH, 0, 1024, 256, 64);
+ MBUS_CONF(16, false, HIGHEST, 6, 8192, 2800, 2400);
+ MBUS_CONF(21, false, HIGHEST, 6, 2048, 768, 512);
+ MBUS_CONF(22, false, HIGH, 0, 256, 128, 100);
+ MBUS_CONF(25, true, HIGHEST, 0, 100, 64, 32);
+ MBUS_CONF(26, false, HIGH, 2, 8192, 5500, 5000);
+ MBUS_CONF(37, false, HIGH, 0, 256, 128, 64);
+ MBUS_CONF(38, false, HIGH, 2, 100, 64, 32);
+ MBUS_CONF(39, false, HIGH, 2, 8192, 5500, 5000);
+ MBUS_CONF(40, false, HIGH, 2, 100, 64, 32);
dmb();
}
@@ -225,8 +226,28 @@
mctl_ctl->addrmap[8] = 0x3F3F;
}
+#ifdef CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_1
static const u8 phy_init[] = {
#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333
+ 0x08, 0x02, 0x12, 0x05, 0x15, 0x17, 0x18, 0x0b,
+ 0x14, 0x07, 0x04, 0x13, 0x0c, 0x00, 0x16, 0x1a,
+ 0x0a, 0x11, 0x03, 0x10, 0x0e, 0x01, 0x0d, 0x19,
+ 0x06, 0x09, 0x0f
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)
+ 0x18, 0x00, 0x04, 0x09, 0x06, 0x05, 0x02, 0x19,
+ 0x17, 0x03, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
+ 0x08, 0x01, 0x1a
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
+ 0x03, 0x00, 0x17, 0x05, 0x02, 0x19, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
+ 0x18, 0x04, 0x1a
+#endif
+};
+#else /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */
+static const u8 phy_init[] = {
+#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333
0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19,
0x0a, 0x15, 0x03, 0x13, 0x04, 0x0c, 0x10, 0x06,
0x0f, 0x11, 0x1a, 0x01, 0x12, 0x17, 0x00, 0x08,
@@ -243,7 +264,7 @@
0x18, 0x03, 0x1a
#endif
};
-
+#endif /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */
#define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f)
static void mctl_phy_configure_odt(const struct dram_para *para)
{
@@ -293,14 +314,22 @@
dmb();
}
-static bool mctl_phy_write_leveling(const struct dram_config *config)
+static bool mctl_phy_write_leveling(const struct dram_para *para,
+ const struct dram_config *config)
{
bool result = true;
u32 val;
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0xc0, 0x80);
- writel(4, SUNXI_DRAM_PHY0_BASE + 0xc);
- writel(0x40, SUNXI_DRAM_PHY0_BASE + 0x10);
+
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4) {
+ /* MR2 value */
+ writel(0x1b, SUNXI_DRAM_PHY0_BASE + 0xc);
+ writel(0, SUNXI_DRAM_PHY0_BASE + 0x10);
+ } else {
+ writel(4, SUNXI_DRAM_PHY0_BASE + 0xc);
+ writel(0x40, SUNXI_DRAM_PHY0_BASE + 0x10);
+ }
setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
@@ -859,9 +888,9 @@
}
break;
case SUNXI_DRAM_TYPE_LPDDR4:
- if (para->tpr2 & 1) {
- writel(val, SUNXI_DRAM_PHY0_BASE + 0x788);
- } else {
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x788);
+ if (config->ranks == 2) {
+ val = (para->tpr10 >> 11) & 0x1e;
writel(val, SUNXI_DRAM_PHY0_BASE + 0x794);
};
break;
@@ -986,12 +1015,16 @@
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 0xe0, 0x20);
}
+ clrbits_le32(&mctl_com->unk_0x500, 0x200);
+ udelay(1);
+
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 8);
mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x180), 4, 4);
+ udelay(1000);
+
writel(0x37, SUNXI_DRAM_PHY0_BASE + 0x58);
- clrbits_le32(&mctl_com->unk_0x500, 0x200);
writel(0, &mctl_ctl->swctl);
setbits_le32(&mctl_ctl->dfimisc, 1);
@@ -1010,6 +1043,8 @@
mctl_await_completion(&mctl_ctl->swstat, 1, 1);
mctl_await_completion(&mctl_ctl->statr, 3, 1);
+ udelay(200);
+
writel(0, &mctl_ctl->swctl);
clrbits_le32(&mctl_ctl->dfimisc, 1);
@@ -1080,19 +1115,27 @@
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
writel(0xb04, &mctl_ctl->mrctrl1);
+ udelay(10);
writel(0x80000030, &mctl_ctl->mrctrl0);
+ udelay(10);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
writel(0xc72, &mctl_ctl->mrctrl1);
+ udelay(10);
writel(0x80000030, &mctl_ctl->mrctrl0);
+ udelay(10);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
writel(0xe09, &mctl_ctl->mrctrl1);
+ udelay(10);
writel(0x80000030, &mctl_ctl->mrctrl0);
+ udelay(10);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
writel(0x1624, &mctl_ctl->mrctrl1);
+ udelay(10);
writel(0x80000030, &mctl_ctl->mrctrl0);
+ udelay(10);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
break;
case SUNXI_DRAM_TYPE_DDR4:
@@ -1108,7 +1151,7 @@
if (para->tpr10 & TPR10_WRITE_LEVELING) {
for (i = 0; i < 5; i++)
- if (mctl_phy_write_leveling(config))
+ if (mctl_phy_write_leveling(para, config))
break;
if (i == 5) {
debug("write leveling failed!\n");
@@ -1234,9 +1277,6 @@
setbits_le32(&mctl_ctl->unk_0x3180, BIT(31) | BIT(30));
setbits_le32(&mctl_ctl->unk_0x4180, BIT(31) | BIT(30));
- if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
- setbits_le32(&mctl_ctl->dbictl, 0x1);
-
setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
@@ -1248,8 +1288,10 @@
setbits_le32(&mctl_ctl->clken, BIT(8));
clrsetbits_le32(&mctl_com->unk_0x500, BIT(24), 0x300);
+ udelay(1);
/* this write seems to enable PHY MMIO region */
setbits_le32(&mctl_com->unk_0x500, BIT(24));
+ udelay(1);
if (!mctl_phy_init(para, config))
return false;
@@ -1321,28 +1363,33 @@
static void mctl_auto_detect_dram_size(const struct dram_para *para,
struct dram_config *config)
{
- /* detect row address bits */
- config->cols = 8;
- config->rows = 18;
+ unsigned int shift;
+
+ /* max. config for columns, but not rows */
+ config->cols = 11;
+ config->rows = 13;
mctl_core_init(para, config);
- for (config->rows = 13; config->rows < 18; config->rows++) {
- /* 8 banks, 8 bit per byte and 16/32 bit width */
- if (mctl_mem_matches((1 << (config->rows + config->cols +
- 4 + config->bus_full_width))))
+ shift = config->bus_full_width + 1;
+
+ /* detect column address bits */
+ for (config->cols = 8; config->cols < 11; config->cols++) {
+ if (mctl_mem_matches(1ULL << (config->cols + shift)))
break;
}
+ debug("detected %u columns\n", config->cols);
- /* detect column address bits */
- config->cols = 11;
+ /* reconfigure to make sure that all active rows are accessible */
+ config->rows = 18;
mctl_core_init(para, config);
- for (config->cols = 8; config->cols < 11; config->cols++) {
- /* 8 bits per byte and 16/32 bit width */
- if (mctl_mem_matches(1 << (config->cols + 1 +
- config->bus_full_width)))
+ /* detect row address bits */
+ shift = config->bus_full_width + 4 + config->cols;
+ for (config->rows = 13; config->rows < 18; config->rows++) {
+ if (mctl_mem_matches(1ULL << (config->rows + shift)))
break;
}
+ debug("detected %u rows\n", config->rows);
}
static unsigned long mctl_calc_size(const struct dram_config *config)
diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
index e6446b9..6f5c4ac 100644
--- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
@@ -23,7 +23,7 @@
u8 trcd = max(ns_to_t(18), 2);
u8 trc = ns_to_t(65);
u8 txp = max(ns_to_t(8), 2);
- u8 trtp = max(ns_to_t(8), 4);
+ u8 trtp = 4;
u8 trp = ns_to_t(21);
u8 tras = ns_to_t(42);
u16 trefi = ns_to_t(3904) / 32;
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c
index 1ea620e..f35bdba 100644
--- a/arch/arm/mach-tegra/ap.c
+++ b/arch/arm/mach-tegra/ap.c
@@ -32,7 +32,7 @@
* Tegra30, 0x35 for T114, and 0x40 for Tegra124.
*/
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
- debug("%s: CHIPID is 0x%02X\n", __func__, rev);
+ debug("%s: CHIPID is 0x%02x\n", __func__, rev);
return rev;
}
@@ -43,7 +43,7 @@
struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
sku_id = readl(&fuse->sku_info) & 0xff;
- debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
+ debug("%s: SKU info byte is 0x%02x\n", __func__, sku_id);
return sku_id;
}
@@ -58,8 +58,9 @@
switch (chip_id) {
case CHIPID_TEGRA20:
switch (sku_id) {
- case SKU_ID_T20_7:
+ case SKU_ID_AP20:
case SKU_ID_T20:
+ case SKU_ID_AP20H:
return TEGRA_SOC_T20;
case SKU_ID_T25SE:
case SKU_ID_AP25:
@@ -103,8 +104,8 @@
}
/* unknown chip/sku id */
- printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
- __func__, chip_id, sku_id);
+ printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02x/0x%02x)\n",
+ __func__, chip_id, sku_id);
return TEGRA_SOC_UNKNOWN;
}
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index cc37878..7ca56a3 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -181,7 +181,7 @@
-1,
-1,
-1,
- -1,
+ FUNCMUX_UART5_SDMMC1, /* UARTE */
#elif defined(CONFIG_TEGRA114)
-1,
-1,
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 8e7fd7e..6e9ef68 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -6,6 +6,7 @@
#include <config.h>
#include <dm.h>
+#include <dm/root.h>
#include <env.h>
#include <errno.h>
#include <init.h>
@@ -457,3 +458,18 @@
return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
}
+
+#if IS_ENABLED(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ int ret, rescan;
+
+ ret = fdtdec_resetup(&rescan);
+ if (!ret && rescan) {
+ dm_uninit();
+ dm_init_and_scan(true);
+ }
+
+ return 0;
+}
+#endif
diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c
index d3c480e..99acc59 100644
--- a/arch/sh/cpu/sh4/cache.c
+++ b/arch/sh/cpu/sh4/cache.c
@@ -33,8 +33,9 @@
}
}
-#define CACHE_ENABLE 0
-#define CACHE_DISABLE 1
+#define CACHE_ENABLE 0
+#define CACHE_DISABLE 1
+#define CACHE_INVALIDATE 2
static int cache_control(unsigned int cmd)
{
@@ -46,7 +47,9 @@
if (ccr & CCR_CACHE_ENABLE)
cache_wback_all();
- if (cmd == CACHE_DISABLE)
+ if (cmd == CACHE_INVALIDATE)
+ outl(CCR_CACHE_ICI | ccr, CCR);
+ else if (cmd == CACHE_DISABLE)
outl(CCR_CACHE_STOP, CCR);
else
outl(CCR_CACHE_INIT, CCR);
@@ -103,7 +106,7 @@
void invalidate_icache_all(void)
{
- puts("No arch specific invalidate_icache_all available!\n");
+ cache_control(CACHE_INVALIDATE);
}
int icache_status(void)
diff --git a/board/asus/grouper/MAINTAINERS b/board/asus/grouper/MAINTAINERS
index f4068d8..3c59632 100644
--- a/board/asus/grouper/MAINTAINERS
+++ b/board/asus/grouper/MAINTAINERS
@@ -2,6 +2,6 @@
M: Svyatoslav Ryhel <clamor95@gmail.com>
S: Maintained
F: board/asus/grouper/
-F: configs/grouper_common_defconfig
-F: doc/board/asus/grouper_common.rst
+F: configs/grouper_defconfig
+F: doc/board/asus/grouper.rst
F: include/configs/grouper.h
diff --git a/board/asus/grouper/Makefile b/board/asus/grouper/Makefile
index 05c6ffb..8a8e653 100644
--- a/board/asus/grouper/Makefile
+++ b/board/asus/grouper/Makefile
@@ -6,9 +6,7 @@
# (C) Copyright 2021
# Svyatoslav Ryhel <clamor95@gmail.com>
-ifdef CONFIG_XPL_BUILD
-obj-$(CONFIG_DM_PMIC_MAX77663) += grouper-spl-max.o
-obj-$(CONFIG_DM_PMIC_TPS65910) += grouper-spl-ti.o
-endif
+obj-$(CONFIG_SPL_BUILD) += grouper-spl.o
+obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o
obj-y += grouper.o
diff --git a/board/asus/grouper/board-info.c b/board/asus/grouper/board-info.c
new file mode 100644
index 0000000..4892acc
--- /dev/null
+++ b/board/asus/grouper/board-info.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <env.h>
+#include <spl_gpio.h>
+
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+
+/*
+ * PMIC_ID is GMI_CS2_N_PK3
+ * MODEM_ID is GMI_CS4_N_PK2
+ *
+ * Extended Project ID
+ * ====================================
+ * MODEM_ID PMIC_ID project name
+ * 0 0 grouper-E1565
+ * 0 1 grouper-PM269
+ * 1 0 tilapia
+ */
+enum project_rev {
+ E1565, PM269, TILAPIA, COUNT,
+};
+
+static const char * const project_id_to_fdt[] = {
+ [E1565] = "tegra30-asus-nexus7-grouper-E1565",
+ [PM269] = "tegra30-asus-nexus7-grouper-PM269",
+ [TILAPIA] = "tegra30-asus-nexus7-tilapia-E1565",
+};
+
+static int id_gpio_get_value(u32 pingrp, u32 pin)
+{
+ /* Configure pinmux */
+ pinmux_set_func(pingrp, PMUX_FUNC_GMI);
+ pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN);
+ pinmux_tristate_enable(pingrp);
+ pinmux_set_io(pingrp, PMUX_PIN_INPUT);
+
+ /*
+ * Since this function may be called
+ * during DM reload we should use SPL
+ * GPIO functions which do not depend
+ * on DM.
+ */
+ spl_gpio_input(NULL, pin);
+ return spl_gpio_get_value(NULL, pin);
+}
+
+static int get_project_id(void)
+{
+ u32 pmic_id, modem_id, proj_id;
+
+ modem_id = id_gpio_get_value(PMUX_PINGRP_GMI_CS4_N_PK2,
+ TEGRA_GPIO(K, 2));
+ pmic_id = id_gpio_get_value(PMUX_PINGRP_GMI_CS2_N_PK3,
+ TEGRA_GPIO(K, 3));
+
+ proj_id = (modem_id << 1 | pmic_id) & COUNT;
+
+ log_debug("[GROUPER]: project id %d (%s)\n", proj_id,
+ project_id_to_fdt[proj_id]);
+
+ return proj_id;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, project_id_to_fdt[get_project_id()]))
+ return 0;
+
+ return -1;
+}
+
+void nvidia_board_late_init(void)
+{
+ char dt_path[64] = { 0 };
+
+ snprintf(dt_path, sizeof(dt_path), "%s.dtb",
+ project_id_to_fdt[get_project_id()]);
+ env_set("fdtfile", dt_path);
+}
diff --git a/board/asus/grouper/configs/grouper_E1565.config b/board/asus/grouper/configs/grouper_E1565.config
deleted file mode 100644
index 265295c..0000000
--- a/board/asus/grouper/configs/grouper_E1565.config
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565"
-CONFIG_CMD_POWEROFF=y
-# CONFIG_MAX77663_GPIO is not set
-CONFIG_DM_PMIC_MAX77663=y
-CONFIG_DM_REGULATOR_MAX77663=y
-CONFIG_SYSRESET_MAX77663=y
diff --git a/board/asus/grouper/configs/grouper_PM269.config b/board/asus/grouper/configs/grouper_PM269.config
deleted file mode 100644
index a7ee358..0000000
--- a/board/asus/grouper/configs/grouper_PM269.config
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-PM269"
-CONFIG_CMD_POWEROFF=y
-CONFIG_DM_PMIC_TPS65910=y
-# CONFIG_DM_REGULATOR_TPS65910 is not set
-CONFIG_DM_REGULATOR_TPS65911=y
-CONFIG_SYSRESET_TPS65910=y
diff --git a/board/asus/grouper/configs/tilapia.config b/board/asus/grouper/configs/tilapia.config
deleted file mode 100644
index d461b47..0000000
--- a/board/asus/grouper/configs/tilapia.config
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-tilapia-E1565"
-CONFIG_SYS_PROMPT="Tegra30 (Tilapia) # "
-CONFIG_CMD_POWEROFF=y
-# CONFIG_MAX77663_GPIO is not set
-CONFIG_DM_PMIC_MAX77663=y
-CONFIG_DM_REGULATOR_MAX77663=y
-CONFIG_SYSRESET_MAX77663=y
diff --git a/board/asus/grouper/grouper-spl-max.c b/board/asus/grouper/grouper-spl-max.c
deleted file mode 100644
index 3e58bf9..0000000
--- a/board/asus/grouper/grouper-spl-max.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * T30 Grouper MAX SPL stage configuration
- *
- * (C) Copyright 2010-2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2022
- * Svyatoslav Ryhel <clamor95@gmail.com>
- */
-
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/tegra_i2c.h>
-#include <linux/delay.h>
-
-#define MAX77663_I2C_ADDR (0x3C << 1)
-
-#define MAX77663_REG_SD0 0x16
-#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0)
-#define MAX77663_REG_SD1 0x17
-#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1)
-#define MAX77663_REG_LDO4 0x2B
-#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4)
-
-#define MAX77663_REG_GPIO4 0x3A
-#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4)
-
-void pmic_enable_cpu_vdd(void)
-{
- /* Set VDD_CORE to 1.200V. */
- tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA);
-
- udelay(1000);
-
- /* Bring up VDD_CPU to 1.0125V. */
- tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA);
- udelay(1000);
-
- /* Bring up VDD_RTC to 1.200V. */
- tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA);
- udelay(10 * 1000);
-
- /* Set 32k-out gpio state */
- tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA);
-}
diff --git a/board/asus/grouper/grouper-spl-ti.c b/board/asus/grouper/grouper-spl-ti.c
deleted file mode 100644
index 1dcce80..0000000
--- a/board/asus/grouper/grouper-spl-ti.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * T30 Grouper TI SPL stage configuration
- *
- * (C) Copyright 2010-2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2022
- * Svyatoslav Ryhel <clamor95@gmail.com>
- */
-
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/tegra_i2c.h>
-#include <linux/delay.h>
-
-#define TPS65911_I2C_ADDR (0x2D << 1)
-#define TPS65911_VDDCTRL_OP_REG 0x28
-#define TPS65911_VDDCTRL_SR_REG 0x27
-#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
-#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
-
-#define TPS62361B_I2C_ADDR (0x60 << 1)
-#define TPS62361B_SET3_REG 0x03
-#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
-
-void pmic_enable_cpu_vdd(void)
-{
- /* Set VDD_CORE to 1.200V. */
- tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
-
- udelay(1000);
-
- /*
- * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
- * First set VDD to 1.0125V, then enable the VDD regulator.
- */
- tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
- udelay(1000);
- tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
- udelay(10 * 1000);
-}
diff --git a/board/asus/grouper/grouper-spl.c b/board/asus/grouper/grouper-spl.c
new file mode 100644
index 0000000..a8d4e54
--- /dev/null
+++ b/board/asus/grouper/grouper-spl.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * T30 Grouper SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2022
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <spl_gpio.h>
+#include <linux/delay.h>
+
+#define MAX77663_I2C_ADDR (0x3C << 1)
+
+#define MAX77663_REG_SD0 0x16
+#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0)
+#define MAX77663_REG_SD1 0x17
+#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1)
+#define MAX77663_REG_LDO4 0x2B
+#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4)
+
+#define MAX77663_REG_GPIO4 0x3A
+#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4)
+
+#define TPS65911_I2C_ADDR (0x2D << 1)
+
+#define TPS65911_VDDCTRL_OP_REG 0x28
+#define TPS65911_VDDCTRL_SR_REG 0x27
+#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62361B_I2C_ADDR (0x60 << 1)
+
+#define TPS62361B_SET3_REG 0x03
+#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
+
+/*
+ * PCB_ID[8] is GMI_CS2_N_PK3
+ *
+ * PMIC module detection
+ * ==============================
+ * PCB_ID[8] 0 1
+ * PMIC Maxim TI
+ */
+static bool ti_pmic_detected(void)
+{
+ /* Configure pinmux */
+ pinmux_set_func(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_FUNC_GMI);
+ pinmux_set_pullupdown(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_PULL_DOWN);
+ pinmux_tristate_enable(PMUX_PINGRP_GMI_CS2_N_PK3);
+ pinmux_set_io(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_PIN_INPUT);
+
+ spl_gpio_input(NULL, TEGRA_GPIO(K, 3));
+ return spl_gpio_get_value(NULL, TEGRA_GPIO(K, 3));
+}
+
+static void max_enable_cpu_vdd(void)
+{
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA);
+
+ udelay(1000);
+
+ /* Bring up VDD_CPU to 1.0125V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA);
+ udelay(1000);
+
+ /* Bring up VDD_RTC to 1.200V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA);
+ udelay(10 * 1000);
+
+ /* Set 32k-out gpio state */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA);
+}
+
+static void ti_enable_cpu_vdd(void)
+{
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
+
+ udelay(1000);
+
+ /*
+ * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+ * First set VDD to 1.0125V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
+ udelay(10 * 1000);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+ if (ti_pmic_detected())
+ ti_enable_cpu_vdd();
+ else
+ max_enable_cpu_vdd();
+}
diff --git a/board/asus/grouper/grouper.env b/board/asus/grouper/grouper.env
new file mode 100644
index 0000000..b1f4aeb
--- /dev/null
+++ b/board/asus/grouper/grouper.env
@@ -0,0 +1,15 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+button_cmd_1_name=Lid
+button_cmd_1=poweroff
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_2=update bootloader=run flash_uboot
+bootmenu_3=reboot RCM=enterrcm
+bootmenu_4=reboot=reset
+bootmenu_5=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/asus/transformer-t20/transformer-t20.env b/board/asus/transformer-t20/transformer-t20.env
new file mode 100644
index 0000000..2f7e820
--- /dev/null
+++ b/board/asus/transformer-t20/transformer-t20.env
@@ -0,0 +1,17 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+button_cmd_1_name=Lid sensor
+button_cmd_1=poweroff
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+boot_dev=1
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=update bootloader=run flash_uboot
+bootmenu_4=reboot RCM=enterrcm
+bootmenu_5=reboot=reset
+bootmenu_6=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/asus/transformer-t30/MAINTAINERS b/board/asus/transformer-t30/MAINTAINERS
index 071a9c0..869cc5a 100644
--- a/board/asus/transformer-t30/MAINTAINERS
+++ b/board/asus/transformer-t30/MAINTAINERS
@@ -4,5 +4,4 @@
F: board/asus/transformer-t30/
F: configs/transformer_t30_defconfig
F: doc/board/asus/transformer_t30.rst
-F: include/configs/transformer-common.h
F: include/configs/transformer-t30.h
diff --git a/board/asus/transformer-t30/Makefile b/board/asus/transformer-t30/Makefile
index ad70078..22b6160 100644
--- a/board/asus/transformer-t30/Makefile
+++ b/board/asus/transformer-t30/Makefile
@@ -6,6 +6,7 @@
# (C) Copyright 2021
# Svyatoslav Ryhel <clamor95@gmail.com>
-obj-$(CONFIG_XPL_BUILD) += transformer-t30-spl.o
+obj-$(CONFIG_SPL_BUILD) += transformer-t30-spl.o
+obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o
obj-y += transformer-t30.o
diff --git a/board/asus/transformer-t30/board-info.c b/board/asus/transformer-t30/board-info.c
new file mode 100644
index 0000000..a2b540c
--- /dev/null
+++ b/board/asus/transformer-t30/board-info.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <env.h>
+#include <spl_gpio.h>
+
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+
+/*
+ * PCB_ID[1] is kb_row5_pr5
+ * PCB_ID[3] is kb_col7_pq7
+ * PCB_ID[4] is kb_row2_pr2
+ * PCB_ID[5] is kb_col5_pq5
+ *
+ * Project ID
+ * =====================================================
+ * PCB_ID[1] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project
+ * 0 0 0 0 TF201
+ * 0 0 0 1 P1801
+ * 0 0 1 0 TF300T
+ * 0 0 1 1 TF300TG
+ * 0 1 0 0 TF700T
+ * 0 1 0 1 TF300TL
+ * 0 1 1 0 Extension
+ * 0 1 1 1 TF500T
+ * 1 0 0 0 TF502T/TF600T
+ * =====================================================
+ */
+enum project_rev {
+ TF201, P1801, TF300T, TF300TG, TF700T,
+ TF300TL, EXT, TF500T, TF600T
+};
+
+static const char * const project_id_to_fdt[] = {
+ [TF201] = "tegra30-asus-tf201",
+ [P1801] = "tegra30-asus-p1801-t",
+ [TF300T] = "tegra30-asus-tf300t",
+ [TF300TG] = "tegra30-asus-tf300tg",
+ [TF700T] = "tegra30-asus-tf700t",
+ [TF300TL] = "tegra30-asus-tf300tl",
+ [TF600T] = "tegra30-asus-tf600t",
+};
+
+static int id_gpio_get_value(u32 pingrp, u32 pin)
+{
+ /* Configure pinmux */
+ pinmux_set_func(pingrp, PMUX_FUNC_KBC);
+ pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN);
+ pinmux_tristate_enable(pingrp);
+ pinmux_set_io(pingrp, PMUX_PIN_INPUT);
+
+ /*
+ * Since this function may be called
+ * during DM reload we should use SPL
+ * GPIO functions which do not depend
+ * on DM.
+ */
+ spl_gpio_input(NULL, pin);
+ return spl_gpio_get_value(NULL, pin);
+}
+
+static int get_project_id(void)
+{
+ u32 pcb_id1, pcb_id3, pcb_id4, pcb_id5;
+
+ pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_ROW5_PR5,
+ TEGRA_GPIO(R, 5));
+ pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL7_PQ7,
+ TEGRA_GPIO(Q, 7));
+ pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_ROW2_PR2,
+ TEGRA_GPIO(R, 2));
+ pcb_id5 = id_gpio_get_value(PMUX_PINGRP_KB_COL5_PQ5,
+ TEGRA_GPIO(Q, 5));
+
+ /* Construct board ID */
+ int proj_id = pcb_id1 << 3 | pcb_id5 << 2 |
+ pcb_id4 << 1 | pcb_id3;
+
+ log_debug("[TRANSFORMER]: project id %d (%s)\n", proj_id,
+ project_id_to_fdt[proj_id]);
+
+ /* Mark tablet with SPI flash */
+ if (proj_id == TF600T)
+ env_set_hex("spiflash", true);
+ else
+ env_set_hex("spiflash", false);
+
+ return proj_id & 0xf;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, project_id_to_fdt[get_project_id()]))
+ return 0;
+
+ return -1;
+}
+
+void nvidia_board_late_init(void)
+{
+ char dt_path[64] = { 0 };
+
+ snprintf(dt_path, sizeof(dt_path), "%s.dtb",
+ project_id_to_fdt[get_project_id()]);
+ env_set("fdtfile", dt_path);
+}
diff --git a/board/asus/transformer-t30/configs/p1801-t.config b/board/asus/transformer-t30/configs/p1801-t.config
deleted file mode 100644
index f378f54..0000000
--- a/board/asus/transformer-t30/configs/p1801-t.config
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-p1801-t"
-# CONFIG_I2C_MUX is not set
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4cb0
diff --git a/board/asus/transformer-t30/configs/tf201.config b/board/asus/transformer-t30/configs/tf201.config
deleted file mode 100644
index e4fd303..0000000
--- a/board/asus/transformer-t30/configs/tf201.config
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf201"
-# CONFIG_I2C_MUX is not set
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00
diff --git a/board/asus/transformer-t30/configs/tf300t.config b/board/asus/transformer-t30/configs/tf300t.config
deleted file mode 100644
index 9ad2ebd..0000000
--- a/board/asus/transformer-t30/configs/tf300t.config
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300t"
-# CONFIG_I2C_MUX is not set
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00
diff --git a/board/asus/transformer-t30/configs/tf300tg.config b/board/asus/transformer-t30/configs/tf300tg.config
deleted file mode 100644
index 7b44a91..0000000
--- a/board/asus/transformer-t30/configs/tf300tg.config
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300tg"
-# CONFIG_I2C_MUX is not set
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4c80
diff --git a/board/asus/transformer-t30/configs/tf300tl.config b/board/asus/transformer-t30/configs/tf300tl.config
deleted file mode 100644
index 81e96d5..0000000
--- a/board/asus/transformer-t30/configs/tf300tl.config
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300tl"
-# CONFIG_I2C_MUX is not set
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00
diff --git a/board/asus/transformer-t30/configs/tf600t.config b/board/asus/transformer-t30/configs/tf600t.config
deleted file mode 100644
index b373486..0000000
--- a/board/asus/transformer-t30/configs/tf600t.config
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf600t"
-CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
-# CONFIG_I2C_MUX is not set
-CONFIG_TEGRA20_SLINK=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00
diff --git a/board/asus/transformer-t30/configs/tf700t.config b/board/asus/transformer-t30/configs/tf700t.config
deleted file mode 100644
index 887c25f..0000000
--- a/board/asus/transformer-t30/configs/tf700t.config
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf700t"
-CONFIG_CLK_GPIO=y
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4c90
-CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y
diff --git a/board/asus/transformer-t30/transformer-t30.env b/board/asus/transformer-t30/transformer-t30.env
new file mode 100644
index 0000000..9b6f407
--- /dev/null
+++ b/board/asus/transformer-t30/transformer-t30.env
@@ -0,0 +1,17 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=if spiflash; then run update_spi; else bootmenu; fi
+button_cmd_1_name=Lid sensor
+button_cmd_1=poweroff
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+boot_dev=1
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=update bootloader=run flash_uboot
+bootmenu_4=reboot RCM=enterrcm
+bootmenu_5=reboot=reset
+bootmenu_6=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/dhelectronics/dh_imx6/MAINTAINERS b/board/dhelectronics/dh_imx6/MAINTAINERS
index 8f9b5ff..472e908 100644
--- a/board/dhelectronics/dh_imx6/MAINTAINERS
+++ b/board/dhelectronics/dh_imx6/MAINTAINERS
@@ -3,6 +3,5 @@
M: Christoph Niedermaier <cniedermaier@dh-electronics.com>
L: u-boot@dh-electronics.com
S: Maintained
-F: board/dhelectronics/dh_imx6/
-F: include/configs/dh_imx6.h
-F: configs/dh_imx6_defconfig
+N: imx6.*dh[cs]o
+N: dh_imx6
diff --git a/board/dhelectronics/dh_imx8mp/MAINTAINERS b/board/dhelectronics/dh_imx8mp/MAINTAINERS
index db69781..cf9f772 100644
--- a/board/dhelectronics/dh_imx8mp/MAINTAINERS
+++ b/board/dhelectronics/dh_imx8mp/MAINTAINERS
@@ -2,7 +2,5 @@
M: Marek Vasut <marex@denx.de>
L: u-boot@dh-electronics.com
S: Maintained
-F: arch/arm/dts/imx8mp-dhcom*
-F: board/dhelectronics/dh_imx8mp/
-F: configs/imx8mp_dhcom*defconfig
-F: include/configs/imx8mp_dhcom*
+N: imx8mp.*dh[cs]o
+N: dh_imx8mp
diff --git a/board/htc/endeavoru/endeavoru-spl.c b/board/htc/endeavoru/endeavoru-spl.c
index 3c4caff..33ff72b 100644
--- a/board/htc/endeavoru/endeavoru-spl.c
+++ b/board/htc/endeavoru/endeavoru-spl.c
@@ -9,13 +9,12 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/tegra_i2c.h>
+#include <spl_gpio.h>
#include <linux/delay.h>
/*
@@ -35,24 +34,6 @@
#define TPS80032_SMPS1_CFG_STATE_DATA (0x0100 | TPS80032_SMPS1_CFG_STATE_REG)
#define TPS80032_SMPS2_CFG_STATE_DATA (0x0100 | TPS80032_SMPS2_CFG_STATE_REG)
-#define TEGRA_GPIO_PS0 144
-
-void pmic_enable_cpu_vdd(void)
-{
- /* Set VDD_CORE to 1.200V. */
- tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS2_CFG_VOLTAGE_DATA);
- udelay(1000);
- tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS2_CFG_STATE_DATA);
-
- udelay(1000);
-
- /* Bring up VDD_CPU to 1.0125V. */
- tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS1_CFG_VOLTAGE_DATA);
- udelay(1000);
- tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS1_CFG_STATE_DATA);
- udelay(10 * 1000);
-}
-
/*
* Unlike all other supported Tegra devices and most known Tegra devices, the
* HTC One X has no hardware way to enter APX/RCM mode, which may lead to a
@@ -65,15 +46,13 @@
* proposed to add the RCM rebooting hook as early into SPL as possible since
* SPL is much more robust and has minimal changes that can break bootflow.
*
- * gpio_early_init_uart() function was chosen as it is the earliest function
+ * pmic_enable_cpu_vdd() function was chosen as it is the earliest function
* exposed for setup by the device. Hook performs a check for volume up
* button state and triggers RCM if it is pressed.
*/
-void gpio_early_init_uart(void)
+void apx_hook(void)
{
- struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
- struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(TEGRA_GPIO_PS0)];
- u32 value;
+ int value;
/* Configure pinmux */
pinmux_set_func(PMUX_PINGRP_KB_ROW8_PS0, PMUX_FUNC_KBC);
@@ -81,19 +60,8 @@
pinmux_tristate_disable(PMUX_PINGRP_KB_ROW8_PS0);
pinmux_set_io(PMUX_PINGRP_KB_ROW8_PS0, PMUX_PIN_INPUT);
- /* Configure GPIO direction as input. */
- value = readl(&bank->gpio_dir_out[GPIO_PORT(TEGRA_GPIO_PS0)]);
- value &= ~(1 << GPIO_BIT(TEGRA_GPIO_PS0));
- writel(value, &bank->gpio_dir_out[GPIO_PORT(TEGRA_GPIO_PS0)]);
-
- /* Enable the pin as a GPIO */
- value = readl(&bank->gpio_config[GPIO_PORT(TEGRA_GPIO_PS0)]);
- value |= 1 << GPIO_BIT(TEGRA_GPIO_PS0);
- writel(value, &bank->gpio_config[GPIO_PORT(TEGRA_GPIO_PS0)]);
-
- /* Get GPIO value */
- value = readl(&bank->gpio_in[GPIO_PORT(TEGRA_GPIO_PS0)]);
- value = (value >> GPIO_BIT(TEGRA_GPIO_PS0)) & 1;
+ spl_gpio_input(NULL, TEGRA_GPIO(S, 0));
+ value = spl_gpio_get_value(NULL, TEGRA_GPIO(S, 0));
/* Enter RCM if button is pressed */
if (!value) {
@@ -101,3 +69,22 @@
tegra_pmc_writel(PMC_CNTRL_MAIN_RST, PMC_CNTRL);
}
}
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Check if RCM request is active */
+ apx_hook();
+
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS2_CFG_VOLTAGE_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS2_CFG_STATE_DATA);
+
+ udelay(1000);
+
+ /* Bring up VDD_CPU to 1.0125V. */
+ tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS1_CFG_VOLTAGE_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS1_CFG_STATE_DATA);
+ udelay(10 * 1000);
+}
diff --git a/board/htc/endeavoru/endeavoru.env b/board/htc/endeavoru/endeavoru.env
new file mode 100644
index 0000000..53e9b56
--- /dev/null
+++ b/board/htc/endeavoru/endeavoru.env
@@ -0,0 +1,13 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_2=update bootloader=run flash_uboot
+bootmenu_3=reboot RCM=enterrcm
+bootmenu_4=reboot=reset
+bootmenu_5=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/lenovo/ideapad-yoga-11/ideapad-yoga-11.env b/board/lenovo/ideapad-yoga-11/ideapad-yoga-11.env
new file mode 100644
index 0000000..7bc2b80
--- /dev/null
+++ b/board/lenovo/ideapad-yoga-11/ideapad-yoga-11.env
@@ -0,0 +1,16 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+button_cmd_1_name=Lid sensor
+button_cmd_1=poweroff
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=update bootloader=run update_spi
+bootmenu_4=reboot RCM=enterrcm
+bootmenu_5=reboot=reset
+bootmenu_6=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/lg/x3-t30/configs/p880.config b/board/lg/x3-t30/configs/p880.config
index 57c2885..44e0fa7 100644
--- a/board/lg/x3-t30/configs/p880.config
+++ b/board/lg/x3-t30/configs/p880.config
@@ -1,3 +1,4 @@
+CONFIG_ENV_SOURCE_FILE="p880"
CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p880"
CONFIG_SYS_PROMPT="Tegra30 (P880) # "
CONFIG_VIDEO_LCD_RENESAS_R69328=y
diff --git a/board/lg/x3-t30/configs/p895.config b/board/lg/x3-t30/configs/p895.config
index 2eba925..267ae3a 100644
--- a/board/lg/x3-t30/configs/p895.config
+++ b/board/lg/x3-t30/configs/p895.config
@@ -1,3 +1,4 @@
+CONFIG_ENV_SOURCE_FILE="p895"
CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p895"
CONFIG_SYS_PROMPT="Tegra30 (P895) # "
CONFIG_VIDEO_LCD_RENESAS_R61307=y
diff --git a/board/lg/x3-t30/p880.env b/board/lg/x3-t30/p880.env
new file mode 100644
index 0000000..f2bf298
--- /dev/null
+++ b/board/lg/x3-t30/p880.env
@@ -0,0 +1,15 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+boot_dev=1
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=update bootloader=run flash_uboot
+bootmenu_4=reboot RCM=enterrcm
+bootmenu_5=reboot=reset
+bootmenu_6=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/lg/x3-t30/p895.env b/board/lg/x3-t30/p895.env
new file mode 100644
index 0000000..53e9b56
--- /dev/null
+++ b/board/lg/x3-t30/p895.env
@@ -0,0 +1,13 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_2=update bootloader=run flash_uboot
+bootmenu_3=reboot RCM=enterrcm
+bootmenu_4=reboot=reset
+bootmenu_5=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/microsoft/surface-rt/surface-rt.env b/board/microsoft/surface-rt/surface-rt.env
new file mode 100644
index 0000000..6829290
--- /dev/null
+++ b/board/microsoft/surface-rt/surface-rt.env
@@ -0,0 +1,14 @@
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+button_cmd_1_name=Hall Sensor
+button_cmd_1=poweroff
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=boot from USB=usb reset; usb start; bootflow scan
+bootmenu_4=reboot RCM=enterrcm
+bootmenu_5=reboot=reset
+bootmenu_6=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/nvidia/cardhu/cardhu.env b/board/nvidia/cardhu/cardhu.env
new file mode 100644
index 0000000..9d1e3e1
--- /dev/null
+++ b/board/nvidia/cardhu/cardhu.env
@@ -0,0 +1,2 @@
+board_name=cardhu-a04
+fdtfile=tegra30-cardhu-a04.dtb
diff --git a/board/nvidia/p2771-0000/p2771-0000.env b/board/nvidia/p2771-0000/p2771-0000.env
new file mode 100644
index 0000000..6789cc1
--- /dev/null
+++ b/board/nvidia/p2771-0000/p2771-0000.env
@@ -0,0 +1,22 @@
+calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r ramdisk_addr_r
+
+kernel_addr_r_align=00200000
+kernel_addr_r_offset=00080000
+kernel_addr_r_size=02000000
+kernel_addr_r_aliases=loadaddr
+
+fdt_addr_r_align=00200000
+fdt_addr_r_offset=00000000
+fdt_addr_r_size=00200000
+
+scriptaddr_align=00200000
+scriptaddr_offset=00000000
+scriptaddr_size=00200000
+
+pxefile_addr_r_align=00200000
+pxefile_addr_r_offset=00000000
+pxefile_addr_r_size=00200000
+
+ramdisk_addr_r_align=00200000
+ramdisk_addr_r_offset=00000000
+ramdisk_addr_r_size=02000000
diff --git a/board/nvidia/p3450-0000/p3450-0000.env b/board/nvidia/p3450-0000/p3450-0000.env
new file mode 100644
index 0000000..f21d2fc
--- /dev/null
+++ b/board/nvidia/p3450-0000/p3450-0000.env
@@ -0,0 +1,7 @@
+/* Only MMC/PXE/DHCP for now, add USB back in later when supported */
+boot_targets=mmc1 mmc0 pxe dhcp
+
+preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then
+ load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr;
+ source ${scriptaddr};
+ fi
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 4ad77c7..8479987 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -132,6 +132,11 @@
S: Maintained
F: configs/Ampe_A76_defconfig
+ANBERNIC RG35XX-2024
+M: Chris Morgan <macromorgan@hotmail.com>
+S: Maintained
+F: configs/anbernic_rg35xx_h700_defconfig
+
BANANAPI M1 PLUS
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
diff --git a/board/toradex/apalis-tk1/apalis-tk1.env b/board/toradex/apalis-tk1/apalis-tk1.env
new file mode 100644
index 0000000..9c2d9a9
--- /dev/null
+++ b/board/toradex/apalis-tk1/apalis-tk1.env
@@ -0,0 +1,45 @@
+/*
+ * Custom Boot configuration:
+ * 1. 8bit SD port (MMC1)
+ * 2. 4bit SD port (MMC2)
+ * 3. eMMC (MMC0)
+ */
+boot_targets=mmc1 mmc2 mmc0 usb pxe dhcp
+
+boot_file=zImage
+boot_script_dhcp=boot.scr
+console=ttyS0
+defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000
+ usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0
+ user_debug=30 pcie_aspm=off
+dfu_alt_info=apalis-tk1.img raw 0x0 0x500 mmcpart 1;
+ boot part 0 1 mmcpart 0;
+ rootfs part 0 2 mmcpart 0;
+ zImage fat 0 1 mmcpart 0;
+ tegra124-apalis-eval.dtb fat 0 1 mmcpart 0
+fdt_board=eval
+fdt_fixup=;
+fdt_module=apalis-v1.2
+uboot_hwpart=1
+uboot_blk=0
+set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff &&
+ setexpr blkcnt ${blkcnt} / 0x200
+update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} &&
+ mmc write ${loadaddr} ${uboot_blk} ${blkcnt}
+setethupdate=if env exists ethaddr; then; else setenv ethaddr
+ 00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr}
+ flash_eth.img && source ${loadaddr}
+setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan;
+ load ${interface} ${drive}:1 ${loadaddr} flash_blk.img
+ || setenv drive 2; mmc rescan; load ${interface} ${drive}:1
+ ${loadaddr} flash_blk.img &&
+ source ${loadaddr}
+setup=setenv setupargs igb_mac=${ethaddr}
+ consoleblank=0 no_console_suspend=1 console=tty1
+ console=${console},${baudrate}n8 debug_uartport=lsport,0
+ ${memargs}
+setupdate=run setsdupdate || run setusbupdate || run setethupdate
+setusbupdate=usb start && setenv interface usb; setenv drive 0;
+ load ${interface} ${drive}:1 ${loadaddr} flash_blk.img &&
+ source ${loadaddr}
+vidargs=fbcon=map:1
diff --git a/board/toradex/apalis_t30/apalis_t30.env b/board/toradex/apalis_t30/apalis_t30.env
new file mode 100644
index 0000000..a8f2904
--- /dev/null
+++ b/board/toradex/apalis_t30/apalis_t30.env
@@ -0,0 +1,9 @@
+uboot_hwpart=1
+uboot_blk=0
+
+set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff &&
+ setexpr blkcnt ${blkcnt} / 0x200
+update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} &&
+ mmc write ${loadaddr} ${uboot_blk} ${blkcnt}
+
+boot_script_dhcp=boot.scr
diff --git a/board/toradex/colibri_t20/colibri_t20.env b/board/toradex/colibri_t20/colibri_t20.env
new file mode 100644
index 0000000..5e9f063
--- /dev/null
+++ b/board/toradex/colibri_t20/colibri_t20.env
@@ -0,0 +1,3 @@
+/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
+boot_script_dhcp=boot.scr
+update_uboot=nand erase.part u-boot && nand write ${loadaddr} u-boot ${filesize}
diff --git a/board/toradex/colibri_t30/colibri_t30.env b/board/toradex/colibri_t30/colibri_t30.env
new file mode 100644
index 0000000..a8f2904
--- /dev/null
+++ b/board/toradex/colibri_t30/colibri_t30.env
@@ -0,0 +1,9 @@
+uboot_hwpart=1
+uboot_blk=0
+
+set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff &&
+ setexpr blkcnt ${blkcnt} / 0x200
+update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} &&
+ mmc write ${loadaddr} ${uboot_blk} ${blkcnt}
+
+boot_script_dhcp=boot.scr
diff --git a/board/wexler/qc750/qc750.env b/board/wexler/qc750/qc750.env
new file mode 100644
index 0000000..f2bf298
--- /dev/null
+++ b/board/wexler/qc750/qc750.env
@@ -0,0 +1,15 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+boot_dev=1
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=update bootloader=run flash_uboot
+bootmenu_4=reboot RCM=enterrcm
+bootmenu_5=reboot=reset
+bootmenu_6=power off=poweroff
+bootmenu_delay=-1
diff --git a/configs/anbernic_rg35xx_h700_defconfig b/configs/anbernic_rg35xx_h700_defconfig
new file mode 100644
index 0000000..cd3d6bf
--- /dev/null
+++ b/configs/anbernic_rg35xx_h700_defconfig
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h700-anbernic-rg35xx-2024"
+CONFIG_SPL=y
+CONFIG_DRAM_SUN50I_H616_DX_ODT=0x08080808
+CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
+CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
+CONFIG_DRAM_SUN50I_H616_ODT_EN=0x7887bbbb
+CONFIG_DRAM_SUN50I_H616_TPR2=0x1
+CONFIG_DRAM_SUN50I_H616_TPR6=0x40808080
+CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6633
+CONFIG_DRAM_SUN50I_H616_TPR11=0x1b1f1e1c
+CONFIG_DRAM_SUN50I_H616_TPR12=0x06060606
+CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_1=y
+CONFIG_MACH_SUN50I_H616=y
+CONFIG_SUNXI_DRAM_H616_LPDDR4=y
+CONFIG_DRAM_CLK=672
+CONFIG_R_I2C_ENABLE=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
+CONFIG_REGULATOR_AXP=y
+CONFIG_AXP717_POWER=y
+CONFIG_AXP_DCDC2_VOLT=940
+CONFIG_AXP_DCDC3_VOLT=1100
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index 7fa6161..baab3bf 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -4,6 +4,7 @@
CONFIG_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="apalis-tk1"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis"
@@ -19,7 +20,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=1
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="setenv fdtfile ${soc}-${fdt_module}-${fdt_board}.dtb && run distro_bootcmd"
+CONFIG_BOOTCOMMAND="setenv fdtfile ${soc}-${fdt_module}-${fdt_board}.dtb && bootflow scan"
CONFIG_SYS_CBSIZE=1024
CONFIG_SYS_PBSIZE=1054
CONFIG_CONSOLE_MUX=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index d7da23e..963b280 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -4,6 +4,7 @@
CONFIG_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="apalis_t30"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index 7d88a25..3fca1ae 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -4,6 +4,7 @@
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80110000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="cardhu"
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 67456c8..a1a12e2 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -4,6 +4,7 @@
CONFIG_TEXT_BASE=0x00110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="colibri_t20"
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x200000
CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 5044feb..3be175b 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -4,6 +4,7 @@
CONFIG_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="colibri_t30"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig
index fddc3d8..f0c8ce1 100644
--- a/configs/endeavoru_defconfig
+++ b/configs/endeavoru_defconfig
@@ -5,6 +5,7 @@
CONFIG_INITRD_TAG=y
CONFIG_TEXT_BASE=0x80110000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="endeavoru"
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0xFFFFD000
CONFIG_DEFAULT_DEVICE_TREE="tegra30-htc-endeavoru"
diff --git a/configs/grouper_common_defconfig b/configs/grouper_defconfig
similarity index 84%
rename from configs/grouper_common_defconfig
rename to configs/grouper_defconfig
index 7d8cb61..d07d740 100644
--- a/configs/grouper_common_defconfig
+++ b/configs/grouper_defconfig
@@ -5,6 +5,7 @@
CONFIG_INITRD_TAG=y
CONFIG_TEXT_BASE=0x80110000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="grouper"
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0xFFFFD000
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565"
@@ -38,6 +39,7 @@
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_UMS_ABORT_KEYED=y
@@ -47,6 +49,9 @@
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIST="tegra30-asus-nexus7-grouper-E1565 tegra30-asus-nexus7-grouper-PM269 tegra30-asus-nexus7-tilapia-E1565"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
@@ -61,10 +66,16 @@
CONFIG_SYS_I2C_TEGRA=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_MAX77663=y
+CONFIG_DM_PMIC_TPS65910=y
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_MAX77663=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_TPS65911=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_MAX77663=y
+CONFIG_SYSRESET_TPS65910=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
diff --git a/configs/ideapad-yoga-11_defconfig b/configs/ideapad-yoga-11_defconfig
index 4618c52..a9dd521 100644
--- a/configs/ideapad-yoga-11_defconfig
+++ b/configs/ideapad-yoga-11_defconfig
@@ -5,6 +5,7 @@
CONFIG_INITRD_TAG=y
CONFIG_TEXT_BASE=0x80110000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="ideapad-yoga-11"
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0xFFFFD000
CONFIG_DEFAULT_DEVICE_TREE="tegra30-lenovo-ideapad-yoga-11"
diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig
index dcc529f..9f75ab1 100644
--- a/configs/imx8mp_debix_model_a_defconfig
+++ b/configs/imx8mp_debix_model_a_defconfig
@@ -8,7 +8,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-debix-model-a"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-debix-model-a"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_IMX8MP_DEBIX_MODEL_A=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig
index c4e4f8b..f60ee73 100644
--- a/configs/orangepi_zero2_defconfig
+++ b/configs/orangepi_zero2_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-orangepi-zero2"
+CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h616-orangepi-zero2"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x08080808
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
diff --git a/configs/orangepi_zero2w_defconfig b/configs/orangepi_zero2w_defconfig
index 5734d9d..cbb702d 100644
--- a/configs/orangepi_zero2w_defconfig
+++ b/configs/orangepi_zero2w_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero2w"
+CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-orangepi-zero2w"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig
index 44b7ec7..4e9b0ec 100644
--- a/configs/orangepi_zero3_defconfig
+++ b/configs/orangepi_zero3_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3"
+CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-orangepi-zero3"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
index 3554ba6..a125865 100644
--- a/configs/p2771-0000-000_defconfig
+++ b/configs/p2771-0000-000_defconfig
@@ -5,6 +5,7 @@
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=1026
+CONFIG_ENV_SOURCE_FILE="p2771-0000"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-000"
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
index ac7ed8e..a002178 100644
--- a/configs/p3450-0000_defconfig
+++ b/configs/p3450-0000_defconfig
@@ -6,6 +6,7 @@
CONFIG_TEXT_BASE=0x80080000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="p3450-0000"
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
diff --git a/configs/qc750_defconfig b/configs/qc750_defconfig
index d0b07ee..58a3c83 100644
--- a/configs/qc750_defconfig
+++ b/configs/qc750_defconfig
@@ -5,6 +5,7 @@
CONFIG_INITRD_TAG=y
CONFIG_TEXT_BASE=0x80110000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="qc750"
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0xFFFFD000
CONFIG_DEFAULT_DEVICE_TREE="tegra30-wexler-qc750"
diff --git a/configs/surface-rt_defconfig b/configs/surface-rt_defconfig
index dbb08ab..c1fd4a5 100644
--- a/configs/surface-rt_defconfig
+++ b/configs/surface-rt_defconfig
@@ -5,6 +5,7 @@
CONFIG_INITRD_TAG=y
CONFIG_TEXT_BASE=0x80110000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="surface-rt"
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0xFFFFD000
CONFIG_DEFAULT_DEVICE_TREE="tegra30-microsoft-surface-rt"
diff --git a/configs/tanix_tx1_defconfig b/configs/tanix_tx1_defconfig
index 9915fff..706306b 100644
--- a/configs/tanix_tx1_defconfig
+++ b/configs/tanix_tx1_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_DEFAULT_DEVICE_TREE="sun50i-h313-tanix-tx1"
+CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h313-tanix-tx1"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x06060606
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0d0d0d0d
diff --git a/configs/transformer_t20_defconfig b/configs/transformer_t20_defconfig
index f424ce8..df993c3 100644
--- a/configs/transformer_t20_defconfig
+++ b/configs/transformer_t20_defconfig
@@ -5,6 +5,7 @@
CONFIG_INITRD_TAG=y
CONFIG_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="transformer-t20"
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0xFFFFD000
CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101"
diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig
index 1078403..9102dcc 100644
--- a/configs/transformer_t30_defconfig
+++ b/configs/transformer_t30_defconfig
@@ -5,6 +5,7 @@
CONFIG_INITRD_TAG=y
CONFIG_TEXT_BASE=0x80110000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="transformer-t30"
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0xFFFFD000
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf201"
@@ -49,10 +50,14 @@
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIST="tegra30-asus-p1801-t tegra30-asus-tf201 tegra30-asus-tf300t tegra30-asus-tf300tg tegra30-asus-tf300tl tegra30-asus-tf600t tegra30-asus-tf700t"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_BUTTON=y
+CONFIG_CLK_GPIO=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x91000000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
@@ -64,6 +69,7 @@
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_GPIO=y
CONFIG_BUTTON_KEYBOARD=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_TPS65910=y
CONFIG_DM_REGULATOR=y
@@ -71,6 +77,7 @@
CONFIG_DM_REGULATOR_TPS65911=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
CONFIG_SYSRESET_TPS65910=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
@@ -79,7 +86,9 @@
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="ASUS"
CONFIG_USB_GADGET_VENDOR_NUM=0x0b05
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4daf
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y
CONFIG_VIDEO_TEGRA20=y
diff --git a/configs/transpeed-8k618-t_defconfig b/configs/transpeed-8k618-t_defconfig
index 020d397..1d5a0c2 100644
--- a/configs/transpeed-8k618-t_defconfig
+++ b/configs/transpeed-8k618-t_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-transpeed-8k618-t"
+CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-transpeed-8k618-t"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig
index 42a3b8c..f876cc9 100644
--- a/configs/x96_mate_defconfig
+++ b/configs/x96_mate_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-x96-mate"
+CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h616-x96-mate"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
diff --git a/disk/Kconfig b/disk/Kconfig
index ffa835e..b0bd025 100644
--- a/disk/Kconfig
+++ b/disk/Kconfig
@@ -49,6 +49,16 @@
default y if MAC_PARTITION
select SPL_PARTITIONS
+config TEGRA_PARTITION
+ bool "Enable Nvidia Tegra partition table"
+ select PARTITIONS
+ select EFI_PARTITION
+ help
+ Say Y here if you would like to use U-Boot on a device that
+ is using the Nvidia Tegra partition table and cannot alter it.
+
+ If unsure, say N.
+
config DOS_PARTITION
bool "Enable MS Dos partition table"
default y if BOOT_DEFAULTS
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 580821a..7f04c6e 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -318,6 +318,17 @@
/* Read legacy MBR from block 0 and validate it */
if ((blk_dread(desc, 0, 1, (ulong *)legacymbr) != 1)
|| (is_pmbr_valid(legacymbr) != 1)) {
+ /*
+ * TegraPT is compatible with EFI part, but it
+ * cannot pass the Protective MBR check. Skip it
+ * if CONFIG_TEGRA_PARTITION is enabled and the
+ * device in question is eMMC.
+ */
+ if (IS_ENABLED(CONFIG_TEGRA_PARTITION))
+ if (!is_pmbr_valid(legacymbr) &&
+ desc->uclass_id == UCLASS_MMC &&
+ !desc->devnum)
+ return 0;
return -1;
}
return 0;
diff --git a/doc/board/asus/grouper_common.rst b/doc/board/asus/grouper.rst
similarity index 93%
rename from doc/board/asus/grouper_common.rst
rename to doc/board/asus/grouper.rst
index 47a854e..d56a9ca 100644
--- a/doc/board/asus/grouper_common.rst
+++ b/doc/board/asus/grouper.rst
@@ -19,14 +19,14 @@
Build U-Boot
------------
-Device support is implemented by applying config fragment to a generic board
-defconfig. Valid fragments are ``tilapia.config``, ``grouper_E1565.config``
-and ``grouper_PM269.config``.
+U-Boot features ability to detect grouper board revision on which it is
+loaded. Currently are supported both TI and MAXIM based WiFi-only models
+along with cellular one.
.. code-block:: bash
$ export CROSS_COMPILE=arm-linux-gnueabi-
- $ make grouper_common_defconfig grouper_E1565.config # For maxim based grouper
+ $ make grouper_defconfig # For all grouper versions and tilapia
$ make
After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
diff --git a/doc/board/asus/index.rst b/doc/board/asus/index.rst
index 2b10328..2cac04c 100644
--- a/doc/board/asus/index.rst
+++ b/doc/board/asus/index.rst
@@ -6,6 +6,6 @@
.. toctree::
:maxdepth: 2
- grouper_common
+ grouper
transformer_t20
transformer_t30
diff --git a/doc/board/asus/transformer_t30.rst b/doc/board/asus/transformer_t30.rst
index ff9792d..bebc4b9 100644
--- a/doc/board/asus/transformer_t30.rst
+++ b/doc/board/asus/transformer_t30.rst
@@ -20,15 +20,18 @@
Build U-Boot
------------
-Device support is implemented by applying a config fragment to a generic board
-defconfig. Valid fragments are ``tf201.config``, ``tf300t.config``,
-``tf300tg.config``, ``tf300tl.config``, ``tf700t.config``, ``tf600t.config`` and
-``p1801-t.config``.
+U-Boot features ability to detect transformer device model on which it is
+loaded. The list of supported devices include:
+- ASUS Transformer Prime TF201
+- ASUS Transformer Pad (3G/LTE) TF300T/TG/TL
+- ASUS Transformer Infinity TF700T
+- ASUS Portable AiO P1801-T
+- ASUS VivoTab RT TF600T
.. code-block:: bash
$ export CROSS_COMPILE=arm-linux-gnueabi-
- $ make transformer_t30_defconfig tf201.config # For TF201
+ $ make transformer_t30_defconfig
$ make
After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 34d91cd..1d04090 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -197,6 +197,8 @@
base = (void *)ANATOP_BASE_ADDR;
+ clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0));
+
clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index b44d560..7875a99 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -55,6 +55,17 @@
DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
.offset = _offset)
+#define CPG_PLL20CR 0x0834 /* PLL20 Control Register */
+#define CPG_PLL21CR 0x0838 /* PLL21 Control Register */
+#define CPG_PLL30CR 0x083c /* PLL30 Control Register */
+#define CPG_PLL31CR 0x0840 /* PLL31 Control Register */
+
+#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */
+#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */
+#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */
+#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */
+#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */
+
static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -64,10 +75,10 @@
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
- DEF_PLL(".pll20", CLK_PLL20, 0x0834),
- DEF_PLL(".pll21", CLK_PLL21, 0x0838),
- DEF_PLL(".pll30", CLK_PLL30, 0x083c),
- DEF_PLL(".pll31", CLK_PLL31, 0x0840),
+ DEF_PLL(".pll20", CLK_PLL20, CPG_PLL20CR),
+ DEF_PLL(".pll21", CLK_PLL21, CPG_PLL21CR),
+ DEF_PLL(".pll30", CLK_PLL30, CPG_PLL30CR),
+ DEF_PLL(".pll31", CLK_PLL31, CPG_PLL31CR),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1),
@@ -110,17 +121,17 @@
DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1),
- DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
- DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
+ DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),
+ DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, CPG_SD0CKCR),
DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
R8A779A0_CLK_RPC),
- DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
- DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
- DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
- DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884),
+ DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR),
+ DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR),
+ DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, CPG_CSICKCR),
+ DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, CPG_DSIEXTCKCR),
DEF_GEN4_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index ea98bc6..fdca63a 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -15,6 +15,12 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
+#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */
+#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */
+#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */
+#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */
+#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */
+
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A779F0_CLK_R,
@@ -110,13 +116,13 @@
DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
- DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870),
- DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870),
+ DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),
+ DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, CPG_SD0CKCR),
DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
- DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
+ DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR),
DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8),
DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 4df0a69..9fb672a 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -15,6 +15,12 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
+#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */
+#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */
+#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */
+#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */
+#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */
+
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A779G0_CLK_CP,
@@ -141,14 +147,14 @@
DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
- DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
- DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
+ DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR),
+ DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, CPG_CSICKCR),
DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
- DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
+ DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, CPG_DSIEXTCKCR),
- DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
- DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
- DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
+ DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),
+ DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, CPG_SD0CKCR),
+ DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR),
DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index b20d559..2e98e26 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -15,6 +15,12 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
+#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */
+#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */
+#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */
+#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */
+#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */
+
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A779H0_CLK_R,
@@ -155,14 +161,14 @@
DEF_FIXED("viobusd2", R8A779H0_CLK_VIOBUSD2, CLK_VIOSRC, 2, 1),
DEF_FIXED("vcbusd1", R8A779H0_CLK_VCBUSD1, CLK_VCSRC, 1, 1),
DEF_FIXED("vcbusd2", R8A779H0_CLK_VCBUSD2, CLK_VCSRC, 2, 1),
- DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
- DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
+ DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR),
+ DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, CPG_CSICKCR),
DEF_FIXED("dsiref", R8A779H0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
- DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
- DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
+ DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, CPG_DSIEXTCKCR),
+ DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR),
- DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, 0x870),
- DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, 0x870),
+ DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),
+ DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, CPG_SD0CKCR),
DEF_BASE("rpc", R8A779H0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A779H0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779H0_CLK_RPC),
@@ -175,6 +181,9 @@
DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
+ DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2),
+ DEF_MOD("csi40", 331, R8A779H0_CLK_CSI),
+ DEF_MOD("csi41", 400, R8A779H0_CLK_CSI),
DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
@@ -183,14 +192,57 @@
DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER),
DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
+ DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M),
+ DEF_MOD("ispcs0", 612, R8A779H0_CLK_S0D2_VIO),
+ DEF_MOD("ispcs1", 613, R8A779H0_CLK_S0D2_VIO),
+ DEF_MOD("msi0", 618, R8A779H0_CLK_MSO),
+ DEF_MOD("msi1", 619, R8A779H0_CLK_MSO),
+ DEF_MOD("msi2", 620, R8A779H0_CLK_MSO),
+ DEF_MOD("msi3", 621, R8A779H0_CLK_MSO),
+ DEF_MOD("msi4", 622, R8A779H0_CLK_MSO),
+ DEF_MOD("msi5", 623, R8A779H0_CLK_MSO),
+ DEF_MOD("pcie0", 624, R8A779H0_CLK_S0D2_HSC),
+ DEF_MOD("pwm", 628, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
+ DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4),
+ DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4),
+ DEF_MOD("scif3", 704, R8A779H0_CLK_SASYNCPERD4),
+ DEF_MOD("scif4", 705, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0),
DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER),
DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER),
+ DEF_MOD("tmu0", 713, R8A779H0_CLK_SASYNCRT),
+ DEF_MOD("tmu1", 714, R8A779H0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2),
+ DEF_MOD("vin00", 730, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin01", 731, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin02", 800, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin03", 801, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin04", 802, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin05", 803, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin06", 804, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin07", 805, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin10", 806, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin11", 807, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin12", 808, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin13", 809, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin14", 810, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO),
+ DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
+ DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
+ DEF_MOD("cmt1", 911, R8A779H0_CLK_R),
+ DEF_MOD("cmt2", 912, R8A779H0_CLK_R),
+ DEF_MOD("cmt3", 913, R8A779H0_CLK_R),
DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
+ DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M),
+ DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER),
+ DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER),
};
/*
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index 6751af8..091aaee 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -75,10 +75,10 @@
};
static const struct ccu_reset a80_mmc_resets[] = {
- [0] = GATE(0x0, BIT(18)),
- [1] = GATE(0x4, BIT(18)),
- [2] = GATE(0x8, BIT(18)),
- [3] = GATE(0xc, BIT(18)),
+ [0] = RESET(0x0, BIT(18)),
+ [1] = RESET(0x4, BIT(18)),
+ [2] = RESET(0x8, BIT(18)),
+ [3] = RESET(0xc, BIT(18)),
};
const struct ccu_desc a80_ccu_desc = {
diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
index 6cafffa..b83df35 100644
--- a/drivers/gpio/tegra_gpio.c
+++ b/drivers/gpio/tegra_gpio.c
@@ -257,6 +257,56 @@
.xlate = tegra_gpio_xlate,
};
+/*
+ * SPL GPIO functions.
+ */
+int spl_gpio_output(void *regs, uint gpio, int value)
+{
+ /* Configure GPIO output value. */
+ set_level(gpio, value);
+
+ /* Configure GPIO direction as output. */
+ set_direction(gpio, DIRECTION_OUTPUT);
+
+ /* Enable the pin as a GPIO */
+ set_config(gpio, 1);
+
+ return 0;
+}
+
+int spl_gpio_input(void *regs, uint gpio)
+{
+ /* Configure GPIO direction as input. */
+ set_direction(gpio, DIRECTION_INPUT);
+
+ /* Enable the pin as a GPIO */
+ set_config(gpio, 1);
+
+ return 0;
+}
+
+int spl_gpio_get_value(void *regs, uint gpio)
+{
+ struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+ struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+ int val;
+
+ if (get_direction(gpio) == DIRECTION_INPUT)
+ val = readl(&bank->gpio_in[GPIO_PORT(gpio)]);
+ else
+ val = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
+
+ return (val >> GPIO_BIT(gpio)) & 1;
+}
+
+int spl_gpio_set_value(void *regs, uint gpio, int value)
+{
+ /* Configure GPIO output value. */
+ set_level(gpio, value);
+
+ return 0;
+}
+
/**
* Returns the name of a GPIO port
*
diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c
index b753419..661f70c 100644
--- a/drivers/misc/imx_ele/ele_api.c
+++ b/drivers/misc/imx_ele/ele_api.c
@@ -5,12 +5,12 @@
*
*/
-#include <hang.h>
-#include <malloc.h>
-#include <memalign.h>
#include <asm/io.h>
-#include <dm.h>
+#include <asm/mach-imx/sys_proto.h>
#include <asm/mach-imx/ele_api.h>
+#include <dm.h>
+#include <malloc.h>
+#include <memalign.h>
#include <misc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -205,8 +205,7 @@
return -EINVAL;
}
- if ((fuse_id != 1 && fuse_num != 1) ||
- (fuse_id == 1 && fuse_num != 4)) {
+ if (is_imx8ulp() && ((fuse_id != 1 && fuse_num != 1) || (fuse_id == 1 && fuse_num != 4))) {
printf("Invalid fuse number parameter\n");
return -EINVAL;
}
@@ -226,7 +225,7 @@
*response = msg.data[0];
fuse_words[0] = msg.data[1];
- if (fuse_id == 1) {
+ if (fuse_id == 1 && is_imx8ulp()) {
/* OTP_UNIQ_ID */
fuse_words[1] = msg.data[2];
fuse_words[2] = msg.data[3];
@@ -256,6 +255,36 @@
if (lock)
msg.data[0] |= (1 << 31);
+ msg.data[1] = fuse_val;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+ __func__, ret, fuse_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response)
+{
+ struct udevice *dev = gd->arch.ele_dev;
+ int size = sizeof(struct ele_msg);
+ struct ele_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("ele dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
+ msg.size = 3;
+ msg.command = ELE_WRITE_SHADOW_REQ;
+ msg.data[0] = fuse_id;
msg.data[1] = fuse_val;
ret = misc_call(dev, false, &msg, size, &msg, size);
@@ -266,6 +295,42 @@
if (response)
*response = msg.data[0];
+ return ret;
+}
+
+int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response)
+{
+ struct udevice *dev = gd->arch.ele_dev;
+ int size = sizeof(struct ele_msg);
+ struct ele_msg msg = {};
+ int ret;
+
+ if (!dev) {
+ printf("ele dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ if (!fuse_val) {
+ printf("Invalid parameters for shadow read\n");
+ return -EINVAL;
+ }
+
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
+ msg.size = 2;
+ msg.command = ELE_READ_SHADOW_REQ;
+ msg.data[0] = fuse_id;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+ __func__, ret, fuse_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ *fuse_val = msg.data[1];
+
return ret;
}
diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c
index 0cf81f3..cdb85b9 100644
--- a/drivers/misc/imx_ele/ele_mu.c
+++ b/drivers/misc/imx_ele/ele_mu.c
@@ -21,25 +21,35 @@
#define MU_SR_TE0_MASK BIT(0)
#define MU_SR_RF0_MASK BIT(0)
-#define MU_TR_COUNT 8
-#define MU_RR_COUNT 4
void mu_hal_init(ulong base)
{
struct mu_type *mu_base = (struct mu_type *)base;
+ u32 rr_num = (readl(&mu_base->par) & 0xFF00) >> 8;
+ int i;
writel(0, &mu_base->tcr);
writel(0, &mu_base->rcr);
+
+ while (true) {
+ /* If there is pending RX data, clear them by read them out */
+ if (!(readl(&mu_base->sr) & BIT(6)))
+ return;
+
+ for (i = 0; i < rr_num; i++)
+ readl(&mu_base->rr[i]);
+ }
}
int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg)
{
struct mu_type *mu_base = (struct mu_type *)base;
u32 mask = MU_SR_TE0_MASK << reg_index;
- u32 val;
+ u32 val, tr_num;
int ret;
- assert(reg_index < MU_TR_COUNT);
+ tr_num = readl(&mu_base->par) & 0xFF;
+ assert(reg_index < tr_num);
debug("sendmsg tsr 0x%x\n", readl(&mu_base->tsr));
@@ -61,11 +71,12 @@
{
struct mu_type *mu_base = (struct mu_type *)base;
u32 mask = MU_SR_RF0_MASK << reg_index;
- u32 val;
+ u32 val, rr_num;
int ret;
u32 count = 10;
- assert(reg_index < MU_RR_COUNT);
+ rr_num = (readl(&mu_base->par) & 0xFF00) >> 8;
+ assert(reg_index < rr_num);
debug("receivemsg rsr 0x%x\n", readl(&mu_base->rsr));
@@ -96,7 +107,7 @@
{
struct ele_msg *msg = (struct ele_msg *)data;
int ret;
- u8 count = 0;
+ u8 count = 0, rr_num;
if (!msg)
return -EINVAL;
@@ -113,9 +124,11 @@
return -EINVAL;
}
+ rr_num = (readl(&base->par) & 0xFF00) >> 8;
+
/* Read remaining words */
while (count < msg->size) {
- ret = mu_hal_receivemsg((ulong)base, count % MU_RR_COUNT,
+ ret = mu_hal_receivemsg((ulong)base, count % rr_num,
&msg->data[count - 1]);
if (ret)
return ret;
@@ -129,7 +142,7 @@
{
struct ele_msg *msg = (struct ele_msg *)data;
int ret;
- u8 count = 0;
+ u8 count = 0, tr_num;
if (!msg)
return -EINVAL;
@@ -144,9 +157,11 @@
return ret;
count++;
+ tr_num = readl(&base->par) & 0xFF;
+
/* Write remaining words */
while (count < msg->size) {
- ret = mu_hal_sendmsg((ulong)base, count % MU_TR_COUNT,
+ ret = mu_hal_sendmsg((ulong)base, count % tr_num,
msg->data[count - 1]);
if (ret)
return ret;
@@ -229,6 +244,7 @@
static const struct udevice_id imx8ulp_mu_ids[] = {
{ .compatible = "fsl,imx8ulp-mu" },
{ .compatible = "fsl,imx93-mu-s4" },
+ { .compatible = "fsl,imx95-mu-ele" },
{ }
};
diff --git a/drivers/misc/imx_ele/fuse.c b/drivers/misc/imx_ele/fuse.c
index d12539c..c1e7434 100644
--- a/drivers/misc/imx_ele/fuse.c
+++ b/drivers/misc/imx_ele/fuse.c
@@ -11,10 +11,10 @@
#include <env.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/global_data.h>
+#include <env.h>
DECLARE_GLOBAL_DATA_PTR;
-#define FUSE_BANKS 64
#define WORDS_PER_BANKS 8
struct fsb_map_entry {
@@ -32,6 +32,7 @@
#if defined(CONFIG_IMX8ULP)
#define FSB_OTP_SHADOW 0x800
+#define IS_FSB_ALLOWED (true)
struct fsb_map_entry fsb_mapping_table[] = {
{ 3, 8 },
@@ -84,6 +85,8 @@
};
#elif defined(CONFIG_ARCH_IMX9)
#define FSB_OTP_SHADOW 0x8000
+#define IS_FSB_ALLOWED (!IS_ENABLED(CONFIG_SCMI_FIRMWARE) && \
+ !(readl(BLK_CTRL_NS_ANOMIX_BASE_ADDR + 0x28) & BIT(0)))
struct fsb_map_entry fsb_mapping_table[] = {
{ 0, 8 },
@@ -138,8 +141,7 @@
/* map the fuse from ocotp fuse map to FSB*/
for (i = 0; i < size; i++) {
if (fsb_mapping_table[i].fuse_bank != -1 &&
- fsb_mapping_table[i].fuse_bank == bank &&
- fsb_mapping_table[i].fuse_words > word) {
+ fsb_mapping_table[i].fuse_bank == bank) {
break;
}
@@ -150,8 +152,13 @@
return -1; /* Failed to find */
if (fsb_mapping_table[i].redundancy) {
+ if ((fsb_mapping_table[i].fuse_words << 1) <= word)
+ return -2; /* Not valid word */
+
*redundancy = true;
return (word >> 1) + word_pos;
+ } else if (fsb_mapping_table[i].fuse_words <= word) {
+ return -2; /* Not valid word */
}
*redundancy = false;
@@ -187,24 +194,14 @@
int fuse_sense(u32 bank, u32 word, u32 *val)
{
s32 word_index;
- bool redundancy;
- if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ if (word >= WORDS_PER_BANKS || !val)
return -EINVAL;
- word_index = map_fsb_fuse_index(bank, word, &redundancy);
- if (word_index >= 0) {
- *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
- if (redundancy)
- *val = (*val >> ((word % 2) * 16)) & 0xFFFF;
-
- return 0;
- }
-
word_index = map_ele_fuse_index(bank, word);
if (word_index >= 0) {
u32 data[4];
- u32 res, size = 4;
+ u32 res = 0, size = 4;
int ret;
/* Only UID return 4 words */
@@ -236,28 +233,29 @@
return -ENOENT;
}
+
#elif defined(CONFIG_ARCH_IMX9)
int fuse_sense(u32 bank, u32 word, u32 *val)
{
s32 word_index;
bool redundancy;
- if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ if (word >= WORDS_PER_BANKS || !val)
return -EINVAL;
- word_index = map_fsb_fuse_index(bank, word, &redundancy);
- if (word_index >= 0) {
- *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
- if (redundancy)
- *val = (*val >> ((word % 2) * 16)) & 0xFFFF;
+ if (!IS_ENABLED(CONFIG_SCMI_FIRMWARE)) {
+ word_index = map_fsb_fuse_index(bank, word, &redundancy);
- return 0;
+ /* ELE read common fuse API supports all FSB fuse. */
+ if (word_index < 0)
+ word_index = map_ele_fuse_index(bank, word);
+ } else {
+ word_index = bank * 8 + word;
}
- word_index = map_ele_fuse_index(bank, word);
if (word_index >= 0) {
u32 data;
- u32 res, size = 1;
+ u32 res = 0, size = 1;
int ret;
ret = ele_read_common_fuse(word_index, &data, size, &res);
@@ -275,18 +273,62 @@
}
#endif
-int fuse_read(u32 bank, u32 word, u32 *val)
+static int fuse_read_default(u32 bank, u32 word, u32 *val)
{
+ s32 word_index;
+ bool redundancy;
+
+ if (IS_FSB_ALLOWED) {
+ word_index = map_fsb_fuse_index(bank, word, &redundancy);
+ if (word_index >= 0) {
+ *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
+ if (redundancy)
+ *val = (*val >> ((word % 2) * 16)) & 0xFFFF;
+
+ return 0;
+ }
+ }
+
return fuse_sense(bank, word, val);
}
+static int fuse_read_ele_shd(u32 bank, u32 word, u32 *val)
+{
+ u32 res = 0;
+ int ret;
+ struct udevice *dev = gd->arch.ele_dev;
+
+ if (!dev)
+ return -ENODEV;
+
+ ret = ele_read_shadow_fuse((bank * 8 + word), val, &res);
+ if (ret) {
+ printf("ele read shadow fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ return 0;
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+ if (word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
+ env_get_yesno("enable_ele_shd") == 1)
+ return fuse_read_ele_shd(bank, word, val);
+ else
+ return fuse_read_default(bank, word, val);
+}
+
int fuse_prog(u32 bank, u32 word, u32 val)
{
- u32 res;
+ u32 res = 0;
int ret;
bool lock = false;
- if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ if (word >= WORDS_PER_BANKS || !val)
return -EINVAL;
/* Lock 8ULP ECC fuse word, so second programming will return failure.
@@ -314,6 +356,17 @@
int fuse_override(u32 bank, u32 word, u32 val)
{
- printf("Override fuse to i.MX8ULP in u-boot is forbidden\n");
- return -EPERM;
+ u32 res = 0;
+ int ret;
+
+ if (word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ ret = ele_write_shadow_fuse((bank * 8 + word), val, &res);
+ if (ret) {
+ printf("ahab write shadow fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ return 0;
}
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index aa58b79..2a39d1c 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -70,20 +70,20 @@
#define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
#define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
#define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
-#define GPSR0_6 F_(IRQ0, IP0SR0_27_24)
-#define GPSR0_5 F_(IRQ1, IP0SR0_23_20)
-#define GPSR0_4 F_(IRQ2, IP0SR0_19_16)
-#define GPSR0_3 F_(IRQ3, IP0SR0_15_12)
+#define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24)
+#define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20)
+#define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16)
+#define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12)
#define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
#define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
#define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
/* GPSR1 */
-#define GPSR1_28 F_(HTX3, IP3SR1_19_16)
-#define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12)
-#define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8)
-#define GPSR1_25 F_(HSCK3, IP3SR1_7_4)
-#define GPSR1_24 F_(HRX3, IP3SR1_3_0)
+#define GPSR1_28 F_(HTX3_A, IP3SR1_19_16)
+#define GPSR1_27 F_(HCTS3_N_A, IP3SR1_15_12)
+#define GPSR1_26 F_(HRTS3_N_A, IP3SR1_11_8)
+#define GPSR1_25 F_(HSCK3_A, IP3SR1_7_4)
+#define GPSR1_24 F_(HRX3_A, IP3SR1_3_0)
#define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
#define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
#define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
@@ -121,14 +121,14 @@
#define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)
#define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)
#define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)
-#define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0)
-#define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)
+#define GPSR2_8 F_(TPU0TO0_A, IP1SR2_3_0)
+#define GPSR2_7 F_(TPU0TO1_A, IP0SR2_31_28)
#define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
-#define GPSR2_5 F_(FXR_TXENB_N, IP0SR2_23_20)
+#define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20)
#define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
#define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)
#define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)
-#define GPSR2_1 F_(FXR_TXENA_N, IP0SR2_7_4)
+#define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4)
#define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)
/* GPSR3 */
@@ -277,13 +277,13 @@
/* SR0 */
/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -292,72 +292,72 @@
#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR1 */
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) FM(CTS1_N_X) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) FM(RTS1_N_X) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_31_28 F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR2 */
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_7_4 FM(FXR_TXENA_N_A) FM(CANFD1_RX) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX_A) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX_A) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_31_28 FM(TPU0TO1_A) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_3_0 FM(TPU0TO0_A) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -383,8 +383,8 @@
#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -720,22 +720,22 @@
/* IP0SR0 */
PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B),
- PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_A),
+ PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_B),
PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),
- PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3),
+ PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A),
PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),
- PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2),
+ PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A),
PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),
- PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1),
+ PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A),
PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),
- PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0),
+ PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A),
PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),
PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),
@@ -752,75 +752,75 @@
PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD),
PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),
- PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1),
- PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_A),
+ PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1_A),
+ PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_B),
PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
- PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1),
- PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1),
+ PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A),
+ PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A),
PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),
- PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1),
- PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1),
+ PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A),
+ PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A),
/* IP2SR0 */
PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),
- PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N),
- PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N),
+ PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A),
+ PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A),
PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),
- PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N),
- PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N),
+ PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A),
+ PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A),
PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),
- PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1),
- PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1),
+ PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A),
+ PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A),
/* IP0SR1 */
PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
- PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A),
- PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3),
+ PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B),
+ PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B),
PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
- PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_A),
- PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3),
+ PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B),
+ PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B),
PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
- PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_A),
- PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N),
+ PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B),
+ PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B),
PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
- PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A),
- PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N),
+ PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B),
+ PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B),
PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
- PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
- PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3),
+ PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B),
+ PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B),
PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
- PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_X),
- PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_X),
+ PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B),
+ PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B),
PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
- PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_X),
- PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_X),
+ PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B),
+ PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B),
/* IP1SR1 */
PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
- PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_X),
- PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_X),
+ PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B),
+ PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B),
PINMUX_IPSR_GPSR(IP1SR1_3_0, CANFD5_TX_B),
PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
- PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_X),
- PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_X),
+ PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B),
+ PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B),
PINMUX_IPSR_GPSR(IP1SR1_7_4, CANFD5_RX_B),
PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
- PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_X),
- PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_X),
+ PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B),
+ PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B),
PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
@@ -829,15 +829,15 @@
PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
- PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8_A),
+ PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8),
PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
- PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9_A),
+ PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9),
PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
- PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A),
+ PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),
/* IP2SR1 */
PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
@@ -847,99 +847,99 @@
PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A),
PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK),
- PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3),
+ PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3_B),
PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS),
- PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4),
+ PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4_B),
PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),
- PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_A),
+ PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_B),
PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),
- PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_A),
+ PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_B),
PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_A),
- PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2),
+ PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2_A),
PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),
/* IP3SR1 */
- PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
+ PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A),
PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
- PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
+ PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A),
PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),
PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
- PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_A),
+ PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B),
- PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
+ PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A),
PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),
PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
- PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_A),
+ PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B),
- PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
+ PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A),
PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
- PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
+ PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A),
PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
/* IP0SR2 */
PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
- PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_A),
+ PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B),
- PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N),
+ PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A),
PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
- PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_A),
+ PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B),
PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
- PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX),
+ PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX_A),
PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5),
PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),
- PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX),
+ PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX_A),
PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B),
PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),
- PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N),
+ PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A),
PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),
- PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1),
+ PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A),
PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),
- PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_B),
+ PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C),
/* IP1SR2 */
- PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0),
+ PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A),
PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX),
- PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_A),
+ PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B),
PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
- PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_X),
+ PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B),
PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),
- PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_X),
+ PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B),
PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
- PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2),
- PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_A),
+ PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A),
+ PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C),
PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
- PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3),
+ PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A),
PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),
- PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A),
+ PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C),
PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
- PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B),
+ PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),
PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),
@@ -981,12 +981,12 @@
PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),
PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),
PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A),
- PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_X),
+ PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_A),
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),
PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_N_A),
- PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_X),
+ PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_A),
PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
@@ -1533,15 +1533,14 @@
};
/* - CANFD5 ----------------------------------------------------------------- */
-static const unsigned int canfd5_data_pins[] = {
- /* CANFD5_TX, CANFD5_RX */
+static const unsigned int canfd5_data_a_pins[] = {
+ /* CANFD5_TX_A, CANFD5_RX_A */
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
};
-static const unsigned int canfd5_data_mux[] = {
- CANFD5_TX_MARK, CANFD5_RX_MARK,
+static const unsigned int canfd5_data_a_mux[] = {
+ CANFD5_TX_A_MARK, CANFD5_RX_A_MARK,
};
-/* - CANFD5_B ----------------------------------------------------------------- */
static const unsigned int canfd5_data_b_pins[] = {
/* CANFD5_TX_B, CANFD5_RX_B */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
@@ -1601,49 +1600,48 @@
};
/* - HSCIF1 ----------------------------------------------------------------- */
-static const unsigned int hscif1_data_pins[] = {
- /* HRX1, HTX1 */
+static const unsigned int hscif1_data_a_pins[] = {
+ /* HRX1_A, HTX1_A */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
};
-static const unsigned int hscif1_data_mux[] = {
- HRX1_MARK, HTX1_MARK,
+static const unsigned int hscif1_data_a_mux[] = {
+ HRX1_A_MARK, HTX1_A_MARK,
};
-static const unsigned int hscif1_clk_pins[] = {
- /* HSCK1 */
+static const unsigned int hscif1_clk_a_pins[] = {
+ /* HSCK1_A */
RCAR_GP_PIN(0, 18),
};
-static const unsigned int hscif1_clk_mux[] = {
- HSCK1_MARK,
+static const unsigned int hscif1_clk_a_mux[] = {
+ HSCK1_A_MARK,
};
-static const unsigned int hscif1_ctrl_pins[] = {
- /* HRTS1_N, HCTS1_N */
+static const unsigned int hscif1_ctrl_a_pins[] = {
+ /* HRTS1_N_A, HCTS1_N_A */
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
};
-static const unsigned int hscif1_ctrl_mux[] = {
- HRTS1_N_MARK, HCTS1_N_MARK,
+static const unsigned int hscif1_ctrl_a_mux[] = {
+ HRTS1_N_A_MARK, HCTS1_N_A_MARK,
};
-/* - HSCIF1_X---------------------------------------------------------------- */
-static const unsigned int hscif1_data_x_pins[] = {
- /* HRX1_X, HTX1_X */
+static const unsigned int hscif1_data_b_pins[] = {
+ /* HRX1_B, HTX1_B */
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
};
-static const unsigned int hscif1_data_x_mux[] = {
- HRX1_X_MARK, HTX1_X_MARK,
+static const unsigned int hscif1_data_b_mux[] = {
+ HRX1_B_MARK, HTX1_B_MARK,
};
-static const unsigned int hscif1_clk_x_pins[] = {
- /* HSCK1_X */
+static const unsigned int hscif1_clk_b_pins[] = {
+ /* HSCK1_B */
RCAR_GP_PIN(1, 10),
};
-static const unsigned int hscif1_clk_x_mux[] = {
- HSCK1_X_MARK,
+static const unsigned int hscif1_clk_b_mux[] = {
+ HSCK1_B_MARK,
};
-static const unsigned int hscif1_ctrl_x_pins[] = {
- /* HRTS1_N_X, HCTS1_N_X */
+static const unsigned int hscif1_ctrl_b_pins[] = {
+ /* HRTS1_N_B, HCTS1_N_B */
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
};
-static const unsigned int hscif1_ctrl_x_mux[] = {
- HRTS1_N_X_MARK, HCTS1_N_X_MARK,
+static const unsigned int hscif1_ctrl_b_mux[] = {
+ HRTS1_N_B_MARK, HCTS1_N_B_MARK,
};
/* - HSCIF2 ----------------------------------------------------------------- */
@@ -1670,49 +1668,48 @@
};
/* - HSCIF3 ----------------------------------------------------------------- */
-static const unsigned int hscif3_data_pins[] = {
- /* HRX3, HTX3 */
+static const unsigned int hscif3_data_a_pins[] = {
+ /* HRX3_A, HTX3_A */
RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
};
-static const unsigned int hscif3_data_mux[] = {
- HRX3_MARK, HTX3_MARK,
+static const unsigned int hscif3_data_a_mux[] = {
+ HRX3_A_MARK, HTX3_A_MARK,
};
-static const unsigned int hscif3_clk_pins[] = {
- /* HSCK3 */
+static const unsigned int hscif3_clk_a_pins[] = {
+ /* HSCK3_A */
RCAR_GP_PIN(1, 25),
};
-static const unsigned int hscif3_clk_mux[] = {
- HSCK3_MARK,
+static const unsigned int hscif3_clk_a_mux[] = {
+ HSCK3_A_MARK,
};
-static const unsigned int hscif3_ctrl_pins[] = {
- /* HRTS3_N, HCTS3_N */
+static const unsigned int hscif3_ctrl_a_pins[] = {
+ /* HRTS3_N_A, HCTS3_N_A */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
};
-static const unsigned int hscif3_ctrl_mux[] = {
- HRTS3_N_MARK, HCTS3_N_MARK,
+static const unsigned int hscif3_ctrl_a_mux[] = {
+ HRTS3_N_A_MARK, HCTS3_N_A_MARK,
};
-/* - HSCIF3_A ----------------------------------------------------------------- */
-static const unsigned int hscif3_data_a_pins[] = {
- /* HRX3_A, HTX3_A */
+static const unsigned int hscif3_data_b_pins[] = {
+ /* HRX3_B, HTX3_B */
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
};
-static const unsigned int hscif3_data_a_mux[] = {
- HRX3_A_MARK, HTX3_A_MARK,
+static const unsigned int hscif3_data_b_mux[] = {
+ HRX3_B_MARK, HTX3_B_MARK,
};
-static const unsigned int hscif3_clk_a_pins[] = {
- /* HSCK3_A */
+static const unsigned int hscif3_clk_b_pins[] = {
+ /* HSCK3_B */
RCAR_GP_PIN(1, 3),
};
-static const unsigned int hscif3_clk_a_mux[] = {
- HSCK3_A_MARK,
+static const unsigned int hscif3_clk_b_mux[] = {
+ HSCK3_B_MARK,
};
-static const unsigned int hscif3_ctrl_a_pins[] = {
- /* HRTS3_N_A, HCTS3_N_A */
+static const unsigned int hscif3_ctrl_b_pins[] = {
+ /* HRTS3_N_B, HCTS3_N_B */
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
};
-static const unsigned int hscif3_ctrl_a_mux[] = {
- HRTS3_N_A_MARK, HCTS3_N_A_MARK,
+static const unsigned int hscif3_ctrl_b_mux[] = {
+ HRTS3_N_B_MARK, HCTS3_N_B_MARK,
};
/* - I2C0 ------------------------------------------------------------------- */
@@ -1769,6 +1766,90 @@
SDA5_MARK, SCL5_MARK,
};
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_a_pins[] = {
+ /* IRQ0_A */
+ RCAR_GP_PIN(0, 6),
+};
+static const unsigned int intc_ex_irq0_a_mux[] = {
+ IRQ0_A_MARK,
+};
+static const unsigned int intc_ex_irq0_b_pins[] = {
+ /* IRQ0_B */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int intc_ex_irq0_b_mux[] = {
+ IRQ0_B_MARK,
+};
+
+static const unsigned int intc_ex_irq1_a_pins[] = {
+ /* IRQ1_A */
+ RCAR_GP_PIN(0, 5),
+};
+static const unsigned int intc_ex_irq1_a_mux[] = {
+ IRQ1_A_MARK,
+};
+static const unsigned int intc_ex_irq1_b_pins[] = {
+ /* IRQ1_B */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int intc_ex_irq1_b_mux[] = {
+ IRQ1_B_MARK,
+};
+
+static const unsigned int intc_ex_irq2_a_pins[] = {
+ /* IRQ2_A */
+ RCAR_GP_PIN(0, 4),
+};
+static const unsigned int intc_ex_irq2_a_mux[] = {
+ IRQ2_A_MARK,
+};
+static const unsigned int intc_ex_irq2_b_pins[] = {
+ /* IRQ2_B */
+ RCAR_GP_PIN(0, 13),
+};
+static const unsigned int intc_ex_irq2_b_mux[] = {
+ IRQ2_B_MARK,
+};
+
+static const unsigned int intc_ex_irq3_a_pins[] = {
+ /* IRQ3_A */
+ RCAR_GP_PIN(0, 3),
+};
+static const unsigned int intc_ex_irq3_a_mux[] = {
+ IRQ3_A_MARK,
+};
+static const unsigned int intc_ex_irq3_b_pins[] = {
+ /* IRQ3_B */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int intc_ex_irq3_b_mux[] = {
+ IRQ3_B_MARK,
+};
+
+static const unsigned int intc_ex_irq4_a_pins[] = {
+ /* IRQ4_A */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int intc_ex_irq4_a_mux[] = {
+ IRQ4_A_MARK,
+};
+static const unsigned int intc_ex_irq4_b_pins[] = {
+ /* IRQ4_B */
+ RCAR_GP_PIN(2, 3),
+};
+static const unsigned int intc_ex_irq4_b_mux[] = {
+ IRQ4_B_MARK,
+};
+
+static const unsigned int intc_ex_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(2, 2),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+ IRQ5_MARK,
+};
+
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data_pins[] = {
/* MMC_SD_D[0:3], MMC_D[4:7] */
@@ -2095,16 +2176,16 @@
PCIE1_CLKREQ_N_MARK,
};
-/* - PWM0_A ------------------------------------------------------------------- */
-static const unsigned int pwm0_a_pins[] = {
- /* PWM0_A */
+/* - PWM0 ------------------------------------------------------------------- */
+static const unsigned int pwm0_pins[] = {
+ /* PWM0 */
RCAR_GP_PIN(1, 15),
};
-static const unsigned int pwm0_a_mux[] = {
- PWM0_A_MARK,
+static const unsigned int pwm0_mux[] = {
+ PWM0_MARK,
};
-/* - PWM1_A ------------------------------------------------------------------- */
+/* - PWM1 ------------------------------------------------------------------- */
static const unsigned int pwm1_a_pins[] = {
/* PWM1_A */
RCAR_GP_PIN(3, 13),
@@ -2113,7 +2194,6 @@
PWM1_A_MARK,
};
-/* - PWM1_B ------------------------------------------------------------------- */
static const unsigned int pwm1_b_pins[] = {
/* PWM1_B */
RCAR_GP_PIN(2, 13),
@@ -2122,16 +2202,16 @@
PWM1_B_MARK,
};
-/* - PWM2_B ------------------------------------------------------------------- */
-static const unsigned int pwm2_b_pins[] = {
- /* PWM2_B */
+/* - PWM2 ------------------------------------------------------------------- */
+static const unsigned int pwm2_pins[] = {
+ /* PWM2 */
RCAR_GP_PIN(2, 14),
};
-static const unsigned int pwm2_b_mux[] = {
- PWM2_B_MARK,
+static const unsigned int pwm2_mux[] = {
+ PWM2_MARK,
};
-/* - PWM3_A ------------------------------------------------------------------- */
+/* - PWM3 ------------------------------------------------------------------- */
static const unsigned int pwm3_a_pins[] = {
/* PWM3_A */
RCAR_GP_PIN(1, 22),
@@ -2140,7 +2220,6 @@
PWM3_A_MARK,
};
-/* - PWM3_B ------------------------------------------------------------------- */
static const unsigned int pwm3_b_pins[] = {
/* PWM3_B */
RCAR_GP_PIN(2, 15),
@@ -2185,22 +2264,22 @@
PWM7_MARK,
};
-/* - PWM8_A ------------------------------------------------------------------- */
-static const unsigned int pwm8_a_pins[] = {
- /* PWM8_A */
+/* - PWM8 ------------------------------------------------------------------- */
+static const unsigned int pwm8_pins[] = {
+ /* PWM8 */
RCAR_GP_PIN(1, 13),
};
-static const unsigned int pwm8_a_mux[] = {
- PWM8_A_MARK,
+static const unsigned int pwm8_mux[] = {
+ PWM8_MARK,
};
-/* - PWM9_A ------------------------------------------------------------------- */
-static const unsigned int pwm9_a_pins[] = {
- /* PWM9_A */
+/* - PWM9 ------------------------------------------------------------------- */
+static const unsigned int pwm9_pins[] = {
+ /* PWM9 */
RCAR_GP_PIN(1, 14),
};
-static const unsigned int pwm9_a_mux[] = {
- PWM9_A_MARK,
+static const unsigned int pwm9_mux[] = {
+ PWM9_MARK,
};
/* - QSPI0 ------------------------------------------------------------------ */
@@ -2263,75 +2342,51 @@
};
/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_pins[] = {
- /* RX1, TX1 */
+static const unsigned int scif1_data_a_pins[] = {
+ /* RX1_A, TX1_A */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
};
-static const unsigned int scif1_data_mux[] = {
- RX1_MARK, TX1_MARK,
+static const unsigned int scif1_data_a_mux[] = {
+ RX1_A_MARK, TX1_A_MARK,
};
-static const unsigned int scif1_clk_pins[] = {
- /* SCK1 */
+static const unsigned int scif1_clk_a_pins[] = {
+ /* SCK1_A */
RCAR_GP_PIN(0, 18),
};
-static const unsigned int scif1_clk_mux[] = {
- SCK1_MARK,
+static const unsigned int scif1_clk_a_mux[] = {
+ SCK1_A_MARK,
};
-static const unsigned int scif1_ctrl_pins[] = {
- /* RTS1_N, CTS1_N */
+static const unsigned int scif1_ctrl_a_pins[] = {
+ /* RTS1_N_A, CTS1_N_A */
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
};
-static const unsigned int scif1_ctrl_mux[] = {
- RTS1_N_MARK, CTS1_N_MARK,
+static const unsigned int scif1_ctrl_a_mux[] = {
+ RTS1_N_A_MARK, CTS1_N_A_MARK,
};
-/* - SCIF1_X ------------------------------------------------------------------ */
-static const unsigned int scif1_data_x_pins[] = {
- /* RX1_X, TX1_X */
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX1_B, TX1_B */
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
};
-static const unsigned int scif1_data_x_mux[] = {
- RX1_X_MARK, TX1_X_MARK,
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
};
-static const unsigned int scif1_clk_x_pins[] = {
- /* SCK1_X */
+static const unsigned int scif1_clk_b_pins[] = {
+ /* SCK1_B */
RCAR_GP_PIN(1, 10),
};
-static const unsigned int scif1_clk_x_mux[] = {
- SCK1_X_MARK,
+static const unsigned int scif1_clk_b_mux[] = {
+ SCK1_B_MARK,
};
-static const unsigned int scif1_ctrl_x_pins[] = {
- /* RTS1_N_X, CTS1_N_X */
+static const unsigned int scif1_ctrl_b_pins[] = {
+ /* RTS1_N_B, CTS1_N_B */
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
};
-static const unsigned int scif1_ctrl_x_mux[] = {
- RTS1_N_X_MARK, CTS1_N_X_MARK,
+static const unsigned int scif1_ctrl_b_mux[] = {
+ RTS1_N_B_MARK, CTS1_N_B_MARK,
};
/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_pins[] = {
- /* RX3, TX3 */
- RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
-};
-static const unsigned int scif3_data_mux[] = {
- RX3_MARK, TX3_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
- /* SCK3 */
- RCAR_GP_PIN(1, 4),
-};
-static const unsigned int scif3_clk_mux[] = {
- SCK3_MARK,
-};
-static const unsigned int scif3_ctrl_pins[] = {
- /* RTS3_N, CTS3_N */
- RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-};
-static const unsigned int scif3_ctrl_mux[] = {
- RTS3_N_MARK, CTS3_N_MARK,
-};
-
-/* - SCIF3_A ------------------------------------------------------------------ */
static const unsigned int scif3_data_a_pins[] = {
/* RX3_A, TX3_A */
RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
@@ -2354,6 +2409,28 @@
RTS3_N_A_MARK, CTS3_N_A_MARK,
};
+static const unsigned int scif3_data_b_pins[] = {
+ /* RX3_B, TX3_B */
+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
+};
+static const unsigned int scif3_data_b_mux[] = {
+ RX3_B_MARK, TX3_B_MARK,
+};
+static const unsigned int scif3_clk_b_pins[] = {
+ /* SCK3_B */
+ RCAR_GP_PIN(1, 4),
+};
+static const unsigned int scif3_clk_b_mux[] = {
+ SCK3_B_MARK,
+};
+static const unsigned int scif3_ctrl_b_pins[] = {
+ /* RTS3_N_B, CTS3_N_B */
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scif3_ctrl_b_mux[] = {
+ RTS3_N_B_MARK, CTS3_N_B_MARK,
+};
+
/* - SCIF4 ------------------------------------------------------------------ */
static const unsigned int scif4_data_pins[] = {
/* RX4, TX4 */
@@ -2410,64 +2487,63 @@
SSI_SCK_MARK, SSI_WS_MARK,
};
-/* - TPU ------------------------------------------------------------------- */
-static const unsigned int tpu_to0_pins[] = {
- /* TPU0TO0 */
+/* - TPU -------------------------------------------------------------------- */
+static const unsigned int tpu_to0_a_pins[] = {
+ /* TPU0TO0_A */
RCAR_GP_PIN(2, 8),
};
-static const unsigned int tpu_to0_mux[] = {
- TPU0TO0_MARK,
+static const unsigned int tpu_to0_a_mux[] = {
+ TPU0TO0_A_MARK,
};
-static const unsigned int tpu_to1_pins[] = {
- /* TPU0TO1 */
+static const unsigned int tpu_to1_a_pins[] = {
+ /* TPU0TO1_A */
RCAR_GP_PIN(2, 7),
};
-static const unsigned int tpu_to1_mux[] = {
- TPU0TO1_MARK,
+static const unsigned int tpu_to1_a_mux[] = {
+ TPU0TO1_A_MARK,
};
-static const unsigned int tpu_to2_pins[] = {
- /* TPU0TO2 */
+static const unsigned int tpu_to2_a_pins[] = {
+ /* TPU0TO2_A */
RCAR_GP_PIN(2, 12),
};
-static const unsigned int tpu_to2_mux[] = {
- TPU0TO2_MARK,
+static const unsigned int tpu_to2_a_mux[] = {
+ TPU0TO2_A_MARK,
};
-static const unsigned int tpu_to3_pins[] = {
- /* TPU0TO3 */
+static const unsigned int tpu_to3_a_pins[] = {
+ /* TPU0TO3_A */
RCAR_GP_PIN(2, 13),
};
-static const unsigned int tpu_to3_mux[] = {
- TPU0TO3_MARK,
+static const unsigned int tpu_to3_a_mux[] = {
+ TPU0TO3_A_MARK,
};
-/* - TPU_A ------------------------------------------------------------------- */
-static const unsigned int tpu_to0_a_pins[] = {
- /* TPU0TO0_A */
+static const unsigned int tpu_to0_b_pins[] = {
+ /* TPU0TO0_B */
RCAR_GP_PIN(1, 25),
};
-static const unsigned int tpu_to0_a_mux[] = {
- TPU0TO0_A_MARK,
+static const unsigned int tpu_to0_b_mux[] = {
+ TPU0TO0_B_MARK,
};
-static const unsigned int tpu_to1_a_pins[] = {
- /* TPU0TO1_A */
+static const unsigned int tpu_to1_b_pins[] = {
+ /* TPU0TO1_B */
RCAR_GP_PIN(1, 26),
};
-static const unsigned int tpu_to1_a_mux[] = {
- TPU0TO1_A_MARK,
+static const unsigned int tpu_to1_b_mux[] = {
+ TPU0TO1_B_MARK,
};
-static const unsigned int tpu_to2_a_pins[] = {
- /* TPU0TO2_A */
+static const unsigned int tpu_to2_b_pins[] = {
+ /* TPU0TO2_B */
RCAR_GP_PIN(2, 0),
};
-static const unsigned int tpu_to2_a_mux[] = {
- TPU0TO2_A_MARK,
+static const unsigned int tpu_to2_b_mux[] = {
+ TPU0TO2_B_MARK,
};
-static const unsigned int tpu_to3_a_pins[] = {
- /* TPU0TO3_A */
+static const unsigned int tpu_to3_b_pins[] = {
+ /* TPU0TO3_B */
RCAR_GP_PIN(2, 1),
};
-static const unsigned int tpu_to3_a_mux[] = {
- TPU0TO3_A_MARK,
+static const unsigned int tpu_to3_b_mux[] = {
+ TPU0TO3_B_MARK,
};
/* - TSN0 ------------------------------------------------ */
@@ -2580,8 +2656,8 @@
SH_PFC_PIN_GROUP(canfd2_data),
SH_PFC_PIN_GROUP(canfd3_data),
SH_PFC_PIN_GROUP(canfd4_data),
- SH_PFC_PIN_GROUP(canfd5_data), /* suffix might be updated */
- SH_PFC_PIN_GROUP(canfd5_data_b), /* suffix might be updated */
+ SH_PFC_PIN_GROUP(canfd5_data_a),
+ SH_PFC_PIN_GROUP(canfd5_data_b),
SH_PFC_PIN_GROUP(canfd6_data),
SH_PFC_PIN_GROUP(canfd7_data),
SH_PFC_PIN_GROUP(can_clk),
@@ -2589,21 +2665,21 @@
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
- SH_PFC_PIN_GROUP(hscif1_data), /* suffix might be updated */
- SH_PFC_PIN_GROUP(hscif1_clk), /* suffix might be updated */
- SH_PFC_PIN_GROUP(hscif1_ctrl), /* suffix might be updated */
- SH_PFC_PIN_GROUP(hscif1_data_x), /* suffix might be updated */
- SH_PFC_PIN_GROUP(hscif1_clk_x), /* suffix might be updated */
- SH_PFC_PIN_GROUP(hscif1_ctrl_x), /* suffix might be updated */
+ SH_PFC_PIN_GROUP(hscif1_data_a),
+ SH_PFC_PIN_GROUP(hscif1_clk_a),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_a),
+ SH_PFC_PIN_GROUP(hscif1_data_b),
+ SH_PFC_PIN_GROUP(hscif1_clk_b),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_b),
SH_PFC_PIN_GROUP(hscif2_data),
SH_PFC_PIN_GROUP(hscif2_clk),
SH_PFC_PIN_GROUP(hscif2_ctrl),
- SH_PFC_PIN_GROUP(hscif3_data), /* suffix might be updated */
- SH_PFC_PIN_GROUP(hscif3_clk), /* suffix might be updated */
- SH_PFC_PIN_GROUP(hscif3_ctrl), /* suffix might be updated */
- SH_PFC_PIN_GROUP(hscif3_data_a), /* suffix might be updated */
- SH_PFC_PIN_GROUP(hscif3_clk_a), /* suffix might be updated */
- SH_PFC_PIN_GROUP(hscif3_ctrl_a), /* suffix might be updated */
+ SH_PFC_PIN_GROUP(hscif3_data_a),
+ SH_PFC_PIN_GROUP(hscif3_clk_a),
+ SH_PFC_PIN_GROUP(hscif3_ctrl_a),
+ SH_PFC_PIN_GROUP(hscif3_data_b),
+ SH_PFC_PIN_GROUP(hscif3_clk_b),
+ SH_PFC_PIN_GROUP(hscif3_ctrl_b),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
@@ -2612,6 +2688,18 @@
SH_PFC_PIN_GROUP(i2c4),
SH_PFC_PIN_GROUP(i2c5),
+ SH_PFC_PIN_GROUP(intc_ex_irq0_a),
+ SH_PFC_PIN_GROUP(intc_ex_irq0_b),
+ SH_PFC_PIN_GROUP(intc_ex_irq1_a),
+ SH_PFC_PIN_GROUP(intc_ex_irq1_b),
+ SH_PFC_PIN_GROUP(intc_ex_irq2_a),
+ SH_PFC_PIN_GROUP(intc_ex_irq2_b),
+ SH_PFC_PIN_GROUP(intc_ex_irq3_a),
+ SH_PFC_PIN_GROUP(intc_ex_irq3_b),
+ SH_PFC_PIN_GROUP(intc_ex_irq4_a),
+ SH_PFC_PIN_GROUP(intc_ex_irq4_b),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
+
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
@@ -2665,18 +2753,18 @@
SH_PFC_PIN_GROUP(pcie0_clkreq_n),
SH_PFC_PIN_GROUP(pcie1_clkreq_n),
- SH_PFC_PIN_GROUP(pwm0_a), /* suffix might be updated */
+ SH_PFC_PIN_GROUP(pwm0),
SH_PFC_PIN_GROUP(pwm1_a),
SH_PFC_PIN_GROUP(pwm1_b),
- SH_PFC_PIN_GROUP(pwm2_b), /* suffix might be updated */
+ SH_PFC_PIN_GROUP(pwm2),
SH_PFC_PIN_GROUP(pwm3_a),
SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(pwm4),
SH_PFC_PIN_GROUP(pwm5),
SH_PFC_PIN_GROUP(pwm6),
SH_PFC_PIN_GROUP(pwm7),
- SH_PFC_PIN_GROUP(pwm8_a), /* suffix might be updated */
- SH_PFC_PIN_GROUP(pwm9_a), /* suffix might be updated */
+ SH_PFC_PIN_GROUP(pwm8),
+ SH_PFC_PIN_GROUP(pwm9),
SH_PFC_PIN_GROUP(qspi0_ctrl),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
@@ -2688,18 +2776,18 @@
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
- SH_PFC_PIN_GROUP(scif1_data), /* suffix might be updated */
- SH_PFC_PIN_GROUP(scif1_clk), /* suffix might be updated */
- SH_PFC_PIN_GROUP(scif1_ctrl), /* suffix might be updated */
- SH_PFC_PIN_GROUP(scif1_data_x), /* suffix might be updated */
- SH_PFC_PIN_GROUP(scif1_clk_x), /* suffix might be updated */
- SH_PFC_PIN_GROUP(scif1_ctrl_x), /* suffix might be updated */
- SH_PFC_PIN_GROUP(scif3_data), /* suffix might be updated */
- SH_PFC_PIN_GROUP(scif3_clk), /* suffix might be updated */
- SH_PFC_PIN_GROUP(scif3_ctrl), /* suffix might be updated */
- SH_PFC_PIN_GROUP(scif3_data_a), /* suffix might be updated */
- SH_PFC_PIN_GROUP(scif3_clk_a), /* suffix might be updated */
- SH_PFC_PIN_GROUP(scif3_ctrl_a), /* suffix might be updated */
+ SH_PFC_PIN_GROUP(scif1_data_a),
+ SH_PFC_PIN_GROUP(scif1_clk_a),
+ SH_PFC_PIN_GROUP(scif1_ctrl_a),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_clk_b),
+ SH_PFC_PIN_GROUP(scif1_ctrl_b),
+ SH_PFC_PIN_GROUP(scif3_data_a),
+ SH_PFC_PIN_GROUP(scif3_clk_a),
+ SH_PFC_PIN_GROUP(scif3_ctrl_a),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif3_clk_b),
+ SH_PFC_PIN_GROUP(scif3_ctrl_b),
SH_PFC_PIN_GROUP(scif4_data),
SH_PFC_PIN_GROUP(scif4_clk),
SH_PFC_PIN_GROUP(scif4_ctrl),
@@ -2709,14 +2797,14 @@
SH_PFC_PIN_GROUP(ssi_data),
SH_PFC_PIN_GROUP(ssi_ctrl),
- SH_PFC_PIN_GROUP(tpu_to0), /* suffix might be updated */
- SH_PFC_PIN_GROUP(tpu_to0_a), /* suffix might be updated */
- SH_PFC_PIN_GROUP(tpu_to1), /* suffix might be updated */
- SH_PFC_PIN_GROUP(tpu_to1_a), /* suffix might be updated */
- SH_PFC_PIN_GROUP(tpu_to2), /* suffix might be updated */
- SH_PFC_PIN_GROUP(tpu_to2_a), /* suffix might be updated */
- SH_PFC_PIN_GROUP(tpu_to3), /* suffix might be updated */
- SH_PFC_PIN_GROUP(tpu_to3_a), /* suffix might be updated */
+ SH_PFC_PIN_GROUP(tpu_to0_a),
+ SH_PFC_PIN_GROUP(tpu_to0_b),
+ SH_PFC_PIN_GROUP(tpu_to1_a),
+ SH_PFC_PIN_GROUP(tpu_to1_b),
+ SH_PFC_PIN_GROUP(tpu_to2_a),
+ SH_PFC_PIN_GROUP(tpu_to2_b),
+ SH_PFC_PIN_GROUP(tpu_to3_a),
+ SH_PFC_PIN_GROUP(tpu_to3_b),
SH_PFC_PIN_GROUP(tsn0_link),
SH_PFC_PIN_GROUP(tsn0_phy_int),
@@ -2790,8 +2878,7 @@
};
static const char * const canfd5_groups[] = {
- /* suffix might be updated */
- "canfd5_data",
+ "canfd5_data_a",
"canfd5_data_b",
};
@@ -2814,13 +2901,12 @@
};
static const char * const hscif1_groups[] = {
- /* suffix might be updated */
- "hscif1_data",
- "hscif1_clk",
- "hscif1_ctrl",
- "hscif1_data_x",
- "hscif1_clk_x",
- "hscif1_ctrl_x",
+ "hscif1_data_a",
+ "hscif1_clk_a",
+ "hscif1_ctrl_a",
+ "hscif1_data_b",
+ "hscif1_clk_b",
+ "hscif1_ctrl_b",
};
static const char * const hscif2_groups[] = {
@@ -2830,13 +2916,12 @@
};
static const char * const hscif3_groups[] = {
- /* suffix might be updated */
- "hscif3_data",
- "hscif3_clk",
- "hscif3_ctrl",
"hscif3_data_a",
"hscif3_clk_a",
"hscif3_ctrl_a",
+ "hscif3_data_b",
+ "hscif3_clk_b",
+ "hscif3_ctrl_b",
};
static const char * const i2c0_groups[] = {
@@ -2863,6 +2948,20 @@
"i2c5",
};
+static const char * const intc_ex_groups[] = {
+ "intc_ex_irq0_a",
+ "intc_ex_irq0_b",
+ "intc_ex_irq1_a",
+ "intc_ex_irq1_b",
+ "intc_ex_irq2_a",
+ "intc_ex_irq2_b",
+ "intc_ex_irq3_a",
+ "intc_ex_irq3_b",
+ "intc_ex_irq4_a",
+ "intc_ex_irq4_b",
+ "intc_ex_irq5",
+};
+
static const char * const mmc_groups[] = {
"mmc_data1",
"mmc_data4",
@@ -2933,8 +3032,7 @@
};
static const char * const pwm0_groups[] = {
- /* suffix might be updated */
- "pwm0_a",
+ "pwm0",
};
static const char * const pwm1_groups[] = {
@@ -2943,8 +3041,7 @@
};
static const char * const pwm2_groups[] = {
- /* suffix might be updated */
- "pwm2_b",
+ "pwm2",
};
static const char * const pwm3_groups[] = {
@@ -2969,13 +3066,11 @@
};
static const char * const pwm8_groups[] = {
- /* suffix might be updated */
- "pwm8_a",
+ "pwm8",
};
static const char * const pwm9_groups[] = {
- /* suffix might be updated */
- "pwm9_a",
+ "pwm9",
};
static const char * const qspi0_groups[] = {
@@ -2997,23 +3092,21 @@
};
static const char * const scif1_groups[] = {
- /* suffix might be updated */
- "scif1_data",
- "scif1_clk",
- "scif1_ctrl",
- "scif1_data_x",
- "scif1_clk_x",
- "scif1_ctrl_x",
+ "scif1_data_a",
+ "scif1_clk_a",
+ "scif1_ctrl_a",
+ "scif1_data_b",
+ "scif1_clk_b",
+ "scif1_ctrl_b",
};
static const char * const scif3_groups[] = {
- /* suffix might be updated */
- "scif3_data",
- "scif3_clk",
- "scif3_ctrl",
"scif3_data_a",
"scif3_clk_a",
"scif3_ctrl_a",
+ "scif3_data_b",
+ "scif3_clk_b",
+ "scif3_ctrl_b",
};
static const char * const scif4_groups[] = {
@@ -3036,15 +3129,14 @@
};
static const char * const tpu_groups[] = {
- /* suffix might be updated */
- "tpu_to0",
"tpu_to0_a",
- "tpu_to1",
+ "tpu_to0_b",
"tpu_to1_a",
- "tpu_to2",
+ "tpu_to1_b",
"tpu_to2_a",
- "tpu_to3",
+ "tpu_to2_b",
"tpu_to3_a",
+ "tpu_to3_b",
};
static const char * const tsn0_groups[] = {
@@ -3087,6 +3179,8 @@
SH_PFC_FUNCTION(i2c4),
SH_PFC_FUNCTION(i2c5),
+ SH_PFC_FUNCTION(intc_ex),
+
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(msiof0),
diff --git a/drivers/pinctrl/renesas/pfc-r8a779h0.c b/drivers/pinctrl/renesas/pfc-r8a779h0.c
index 2f09e76..bfabf0c 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779h0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779h0.c
@@ -77,10 +77,10 @@
#define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
#define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
#define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
-#define GPSR0_6 F_(IRQ0, IP0SR0_27_24)
-#define GPSR0_5 F_(IRQ1, IP0SR0_23_20)
-#define GPSR0_4 F_(IRQ2, IP0SR0_19_16)
-#define GPSR0_3 F_(IRQ3, IP0SR0_15_12)
+#define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24)
+#define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20)
+#define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16)
+#define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12)
#define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
#define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
#define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
@@ -261,15 +261,16 @@
#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
+
/* SR0 */
/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -673,16 +674,16 @@
PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),
- PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3),
+ PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A),
PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),
- PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2),
+ PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A),
PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),
- PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1),
+ PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A),
PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),
- PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0),
+ PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A),
PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),
PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),
@@ -1237,6 +1238,30 @@
static const unsigned int avb0_mdio_mux[] = {
AVB0_MDC_MARK, AVB0_MDIO_MARK,
};
+static const unsigned int avb0_mii_pins[] = {
+ /*
+ * AVB0_MII_TD0, AVB0_MII_TD1, AVB0_MII_TD2,
+ * AVB0_MII_TD3, AVB0_MII_RD0, AVB0_MII_RD1,
+ * AVB0_MII_RD2, AVB0_MII_RD3, AVB0_MII_TXC,
+ * AVB0_MII_TX_EN, AVB0_MII_TX_ER, AVB0_MII_RXC,
+ * AVB0_MII_RX_DV, AVB0_MII_RX_ER, AVB0_MII_CRS,
+ * AVB0_MII_COL
+ */
+ RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 6),
+ RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
+ RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 15),
+ RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 19),
+ RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 1),
+ RCAR_GP_PIN(7, 0),
+};
+static const unsigned int avb0_mii_mux[] = {
+ AVB0_MII_TD0_MARK, AVB0_MII_TD1_MARK, AVB0_MII_TD2_MARK,
+ AVB0_MII_TD3_MARK, AVB0_MII_RD0_MARK, AVB0_MII_RD1_MARK,
+ AVB0_MII_RD2_MARK, AVB0_MII_RD3_MARK, AVB0_MII_TXC_MARK,
+ AVB0_MII_TX_EN_MARK, AVB0_MII_TX_ER_MARK, AVB0_MII_RXC_MARK,
+ AVB0_MII_RX_DV_MARK, AVB0_MII_RX_ER_MARK, AVB0_MII_CRS_MARK,
+ AVB0_MII_COL_MARK,
+};
static const unsigned int avb0_rgmii_pins[] = {
/*
* AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
@@ -1315,6 +1340,30 @@
static const unsigned int avb1_mdio_mux[] = {
AVB1_MDC_MARK, AVB1_MDIO_MARK,
};
+static const unsigned int avb1_mii_pins[] = {
+ /*
+ * AVB1_MII_TD0, AVB1_MII_TD1, AVB1_MII_TD2,
+ * AVB1_MII_TD3, AVB1_MII_RD0, AVB1_MII_RD1,
+ * AVB1_MII_RD2, AVB1_MII_RD3, AVB1_MII_TXC,
+ * AVB1_MII_TX_EN, AVB1_MII_TX_ER, AVB1_MII_RXC,
+ * AVB1_MII_RX_DV, AVB1_MII_RX_ER, AVB1_MII_CRS,
+ * AVB1_MII_COL
+ */
+ RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 16),
+ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
+ RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 6),
+ RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 8),
+ RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11),
+ RCAR_GP_PIN(6, 10),
+};
+static const unsigned int avb1_mii_mux[] = {
+ AVB1_MII_TD0_MARK, AVB1_MII_TD1_MARK, AVB1_MII_TD2_MARK,
+ AVB1_MII_TD3_MARK, AVB1_MII_RD0_MARK, AVB1_MII_RD1_MARK,
+ AVB1_MII_RD2_MARK, AVB1_MII_RD3_MARK, AVB1_MII_TXC_MARK,
+ AVB1_MII_TX_EN_MARK, AVB1_MII_TX_ER_MARK, AVB1_MII_RXC_MARK,
+ AVB1_MII_RX_DV_MARK, AVB1_MII_RX_ER_MARK, AVB1_MII_CRS_MARK,
+ AVB1_MII_COL_MARK,
+};
static const unsigned int avb1_rgmii_pins[] = {
/*
* AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
@@ -1510,7 +1559,7 @@
HRTS0_N_MARK, HCTS0_N_MARK,
};
-/* - HSCIF1_A ----------------------------------------------------------------- */
+/* - HSCIF1 ------------------------------------------------------------------- */
static const unsigned int hscif1_data_a_pins[] = {
/* HRX1_A, HTX1_A */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
@@ -1533,7 +1582,6 @@
HRTS1_N_A_MARK, HCTS1_N_A_MARK,
};
-/* - HSCIF1_B ---------------------------------------------------------------- */
static const unsigned int hscif1_data_b_pins[] = {
/* HRX1_B, HTX1_B */
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
@@ -1579,7 +1627,7 @@
HRTS2_N_MARK, HCTS2_N_MARK,
};
-/* - HSCIF3_A ----------------------------------------------------------------- */
+/* - HSCIF3 ------------------------------------------------------------------- */
static const unsigned int hscif3_data_a_pins[] = {
/* HRX3_A, HTX3_A */
RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
@@ -1602,7 +1650,6 @@
HRTS3_N_A_MARK, HCTS3_N_A_MARK,
};
-/* - HSCIF3_B ----------------------------------------------------------------- */
static const unsigned int hscif3_data_b_pins[] = {
/* HRX3_B, HTX3_B */
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
@@ -1661,6 +1708,90 @@
SDA3_MARK, SCL3_MARK,
};
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_a_pins[] = {
+ /* IRQ0_A */
+ RCAR_GP_PIN(0, 6),
+};
+static const unsigned int intc_ex_irq0_a_mux[] = {
+ IRQ0_A_MARK,
+};
+static const unsigned int intc_ex_irq0_b_pins[] = {
+ /* IRQ0_B */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int intc_ex_irq0_b_mux[] = {
+ IRQ0_B_MARK,
+};
+
+static const unsigned int intc_ex_irq1_a_pins[] = {
+ /* IRQ1_A */
+ RCAR_GP_PIN(0, 5),
+};
+static const unsigned int intc_ex_irq1_a_mux[] = {
+ IRQ1_A_MARK,
+};
+static const unsigned int intc_ex_irq1_b_pins[] = {
+ /* IRQ1_B */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int intc_ex_irq1_b_mux[] = {
+ IRQ1_B_MARK,
+};
+
+static const unsigned int intc_ex_irq2_a_pins[] = {
+ /* IRQ2_A */
+ RCAR_GP_PIN(0, 4),
+};
+static const unsigned int intc_ex_irq2_a_mux[] = {
+ IRQ2_A_MARK,
+};
+static const unsigned int intc_ex_irq2_b_pins[] = {
+ /* IRQ2_B */
+ RCAR_GP_PIN(0, 13),
+};
+static const unsigned int intc_ex_irq2_b_mux[] = {
+ IRQ2_B_MARK,
+};
+
+static const unsigned int intc_ex_irq3_a_pins[] = {
+ /* IRQ3_A */
+ RCAR_GP_PIN(0, 3),
+};
+static const unsigned int intc_ex_irq3_a_mux[] = {
+ IRQ3_A_MARK,
+};
+static const unsigned int intc_ex_irq3_b_pins[] = {
+ /* IRQ3_B */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int intc_ex_irq3_b_mux[] = {
+ IRQ3_B_MARK,
+};
+
+static const unsigned int intc_ex_irq4_a_pins[] = {
+ /* IRQ4_A */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int intc_ex_irq4_a_mux[] = {
+ IRQ4_A_MARK,
+};
+static const unsigned int intc_ex_irq4_b_pins[] = {
+ /* IRQ4_B */
+ RCAR_GP_PIN(2, 3),
+};
+static const unsigned int intc_ex_irq4_b_mux[] = {
+ IRQ4_B_MARK,
+};
+
+static const unsigned int intc_ex_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(2, 2),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+ IRQ5_MARK,
+};
+
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data_pins[] = {
/* MMC_SD_D[0:3], MMC_D[4:7] */
@@ -1978,7 +2109,7 @@
PCIE0_CLKREQ_N_MARK,
};
-/* - PWM0_A ------------------------------------------------------------------- */
+/* - PWM0 --------------------------------------------------------------------- */
static const unsigned int pwm0_a_pins[] = {
/* PWM0_A */
RCAR_GP_PIN(1, 15),
@@ -1987,7 +2118,6 @@
PWM0_A_MARK,
};
-/* - PWM0_B ------------------------------------------------------------------- */
static const unsigned int pwm0_b_pins[] = {
/* PWM0_B */
RCAR_GP_PIN(1, 14),
@@ -1996,7 +2126,7 @@
PWM0_B_MARK,
};
-/* - PWM1_A ------------------------------------------------------------------- */
+/* - PWM1 --------------------------------------------------------------------- */
static const unsigned int pwm1_a_pins[] = {
/* PWM1_A */
RCAR_GP_PIN(3, 13),
@@ -2005,7 +2135,6 @@
PWM1_A_MARK,
};
-/* - PWM1_B ------------------------------------------------------------------- */
static const unsigned int pwm1_b_pins[] = {
/* PWM1_B */
RCAR_GP_PIN(2, 13),
@@ -2014,7 +2143,6 @@
PWM1_B_MARK,
};
-/* - PWM1_C ------------------------------------------------------------------- */
static const unsigned int pwm1_c_pins[] = {
/* PWM1_C */
RCAR_GP_PIN(2, 17),
@@ -2023,7 +2151,7 @@
PWM1_C_MARK,
};
-/* - PWM2_A ------------------------------------------------------------------- */
+/* - PWM2 --------------------------------------------------------------------- */
static const unsigned int pwm2_a_pins[] = {
/* PWM2_A */
RCAR_GP_PIN(3, 14),
@@ -2032,7 +2160,6 @@
PWM2_A_MARK,
};
-/* - PWM2_B ------------------------------------------------------------------- */
static const unsigned int pwm2_b_pins[] = {
/* PWM2_B */
RCAR_GP_PIN(2, 14),
@@ -2041,7 +2168,6 @@
PWM2_B_MARK,
};
-/* - PWM2_C ------------------------------------------------------------------- */
static const unsigned int pwm2_c_pins[] = {
/* PWM2_C */
RCAR_GP_PIN(2, 19),
@@ -2050,7 +2176,7 @@
PWM2_C_MARK,
};
-/* - PWM3_A ------------------------------------------------------------------- */
+/* - PWM3 --------------------------------------------------------------------- */
static const unsigned int pwm3_a_pins[] = {
/* PWM3_A */
RCAR_GP_PIN(4, 14),
@@ -2059,7 +2185,6 @@
PWM3_A_MARK,
};
-/* - PWM3_B ------------------------------------------------------------------- */
static const unsigned int pwm3_b_pins[] = {
/* PWM3_B */
RCAR_GP_PIN(2, 15),
@@ -2068,7 +2193,6 @@
PWM3_B_MARK,
};
-/* - PWM3_C ------------------------------------------------------------------- */
static const unsigned int pwm3_c_pins[] = {
/* PWM3_C */
RCAR_GP_PIN(1, 22),
@@ -2145,7 +2269,7 @@
RTS0_N_MARK, CTS0_N_MARK,
};
-/* - SCIF1_A ------------------------------------------------------------------ */
+/* - SCIF1 -------------------------------------------------------------------- */
static const unsigned int scif1_data_a_pins[] = {
/* RX1_A, TX1_A */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
@@ -2168,7 +2292,6 @@
RTS1_N_A_MARK, CTS1_N_A_MARK,
};
-/* - SCIF1_B ------------------------------------------------------------------ */
static const unsigned int scif1_data_b_pins[] = {
/* RX1_B, TX1_B */
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
@@ -2191,7 +2314,7 @@
RTS1_N_B_MARK, CTS1_N_B_MARK,
};
-/* - SCIF3_A ------------------------------------------------------------------ */
+/* - SCIF3 -------------------------------------------------------------------- */
static const unsigned int scif3_data_a_pins[] = {
/* RX3_A, TX3_A */
RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
@@ -2214,7 +2337,6 @@
RTS3_N_A_MARK, CTS3_N_A_MARK,
};
-/* - SCIF3_B ------------------------------------------------------------------ */
static const unsigned int scif3_data_b_pins[] = {
/* RX3_B, TX3_B */
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
@@ -2293,7 +2415,7 @@
SSI_SCK_MARK, SSI_WS_MARK,
};
-/* - TPU_A ------------------------------------------------------------------- */
+/* - TPU --------------------------------------------------------------------- */
static const unsigned int tpu_to0_a_pins[] = {
/* TPU0TO0_A */
RCAR_GP_PIN(2, 8),
@@ -2323,7 +2445,6 @@
TPU0TO3_A_MARK,
};
-/* - TPU_B ------------------------------------------------------------------- */
static const unsigned int tpu_to0_b_pins[] = {
/* TPU0TO0_B */
RCAR_GP_PIN(1, 25),
@@ -2361,6 +2482,7 @@
SH_PFC_PIN_GROUP(avb0_magic),
SH_PFC_PIN_GROUP(avb0_phy_int),
SH_PFC_PIN_GROUP(avb0_mdio),
+ SH_PFC_PIN_GROUP(avb0_mii),
SH_PFC_PIN_GROUP(avb0_rgmii),
SH_PFC_PIN_GROUP(avb0_txcrefclk),
SH_PFC_PIN_GROUP(avb0_avtp_pps),
@@ -2371,6 +2493,7 @@
SH_PFC_PIN_GROUP(avb1_magic),
SH_PFC_PIN_GROUP(avb1_phy_int),
SH_PFC_PIN_GROUP(avb1_mdio),
+ SH_PFC_PIN_GROUP(avb1_mii),
SH_PFC_PIN_GROUP(avb1_rgmii),
SH_PFC_PIN_GROUP(avb1_txcrefclk),
SH_PFC_PIN_GROUP(avb1_avtp_pps),
@@ -2417,6 +2540,18 @@
SH_PFC_PIN_GROUP(i2c2),
SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(intc_ex_irq0_a),
+ SH_PFC_PIN_GROUP(intc_ex_irq0_b),
+ SH_PFC_PIN_GROUP(intc_ex_irq1_a),
+ SH_PFC_PIN_GROUP(intc_ex_irq1_b),
+ SH_PFC_PIN_GROUP(intc_ex_irq2_a),
+ SH_PFC_PIN_GROUP(intc_ex_irq2_b),
+ SH_PFC_PIN_GROUP(intc_ex_irq3_a),
+ SH_PFC_PIN_GROUP(intc_ex_irq3_b),
+ SH_PFC_PIN_GROUP(intc_ex_irq4_a),
+ SH_PFC_PIN_GROUP(intc_ex_irq4_b),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
+
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
@@ -2533,6 +2668,7 @@
"avb0_magic",
"avb0_phy_int",
"avb0_mdio",
+ "avb0_mii",
"avb0_rgmii",
"avb0_txcrefclk",
"avb0_avtp_pps",
@@ -2545,6 +2681,7 @@
"avb1_magic",
"avb1_phy_int",
"avb1_mdio",
+ "avb1_mii",
"avb1_rgmii",
"avb1_txcrefclk",
"avb1_avtp_pps",
@@ -2630,6 +2767,20 @@
"i2c3",
};
+static const char * const intc_ex_groups[] = {
+ "intc_ex_irq0_a",
+ "intc_ex_irq0_b",
+ "intc_ex_irq1_a",
+ "intc_ex_irq1_b",
+ "intc_ex_irq2_a",
+ "intc_ex_irq2_b",
+ "intc_ex_irq3_a",
+ "intc_ex_irq3_b",
+ "intc_ex_irq4_a",
+ "intc_ex_irq4_b",
+ "intc_ex_irq5",
+};
+
static const char * const mmc_groups[] = {
"mmc_data1",
"mmc_data4",
@@ -2814,6 +2965,8 @@
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(intc_ex),
+
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(msiof0),
diff --git a/drivers/pinctrl/tegra/funcmux-tegra30.c b/drivers/pinctrl/tegra/funcmux-tegra30.c
index e31b859..5d3403a 100644
--- a/drivers/pinctrl/tegra/funcmux-tegra30.c
+++ b/drivers/pinctrl/tegra/funcmux-tegra30.c
@@ -33,6 +33,22 @@
break;
}
break;
+ case PERIPH_ID_UART5:
+ switch (config) {
+ case FUNCMUX_UART5_SDMMC1:
+ pinmux_set_func(PMUX_PINGRP_SDMMC1_DAT3_PY4,
+ PMUX_FUNC_UARTE);
+ pinmux_set_func(PMUX_PINGRP_SDMMC1_DAT2_PY5,
+ PMUX_FUNC_UARTE);
+
+ pinmux_set_io(PMUX_PINGRP_SDMMC1_DAT3_PY4, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_SDMMC1_DAT2_PY5, PMUX_PIN_INPUT);
+
+ pinmux_tristate_disable(PMUX_PINGRP_SDMMC1_DAT3_PY4);
+ pinmux_tristate_disable(PMUX_PINGRP_SDMMC1_DAT2_PY5);
+ break;
+ }
+ break;
/* Add other periph IDs here as needed */
diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c
index 9e38e1a..ec3eca1 100644
--- a/drivers/power/axp809.c
+++ b/drivers/power/axp809.c
@@ -93,7 +93,7 @@
return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
AXP809_OUTPUT_CTRL1_DCDC4_EN);
- ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg);
+ ret = pmic_bus_write(AXP809_DCDC4_CTRL, cfg);
if (ret)
return ret;
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 343893b..7c73eb6 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -66,9 +66,24 @@
USB_CTRL_COUNT,
};
+struct tegra_utmip_config {
+ u32 hssync_start_delay;
+ u32 elastic_limit;
+ u32 idle_wait_delay;
+ u32 term_range_adj;
+ bool xcvr_setup_use_fuses;
+ u32 xcvr_setup;
+ u32 xcvr_lsfslew;
+ u32 xcvr_lsrslew;
+ u32 xcvr_hsslew;
+ u32 hssquelch_level;
+ u32 hsdiscon_level;
+};
+
/* Information about a USB port */
struct fdt_usb {
struct ehci_ctrl ehci;
+ struct tegra_utmip_config utmip_config;
struct usb_ctlr *reg; /* address of registers in physical memory */
unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
@@ -192,15 +207,6 @@
{ 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 }
};
-/* UTMIP Idle Wait Delay */
-static const u8 utmip_idle_wait_delay = 17;
-
-/* UTMIP Elastic limit */
-static const u8 utmip_elastic_limit = 16;
-
-/* UTMIP High Speed Sync Start Delay */
-static const u8 utmip_hs_sync_start_delay = 9;
-
struct fdt_usb_controller {
/* flag to determine whether controller supports hostpc register */
u32 has_hostpc:1;
@@ -377,6 +383,7 @@
u32 b_sess_valid_mask, val;
int loop_count;
const unsigned *timing;
+ struct tegra_utmip_config *utmip_config = &config->utmip_config;
struct usb_ctlr *usbctlr = config->reg;
struct clk_rst_ctlr *clkrst;
struct usb_ctlr *usb1ctlr;
@@ -463,16 +470,29 @@
/* Recommended PHY settings for EYE diagram */
val = readl(&usbctlr->utmip_xcvr_cfg0);
- clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
- 0x4 << UTMIP_XCVR_SETUP_SHIFT);
- clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
- 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
- clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
- 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
+
+ if (!utmip_config->xcvr_setup_use_fuses) {
+ clrsetbits_le32(&val, UTMIP_XCVR_SETUP(~0),
+ UTMIP_XCVR_SETUP(utmip_config->xcvr_setup));
+ clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB(~0),
+ UTMIP_XCVR_SETUP_MSB(utmip_config->xcvr_setup));
+ }
+
+ clrsetbits_le32(&val, UTMIP_XCVR_LSFSLEW(~0),
+ UTMIP_XCVR_LSFSLEW(utmip_config->xcvr_lsfslew));
+ clrsetbits_le32(&val, UTMIP_XCVR_LSRSLEW(~0),
+ UTMIP_XCVR_LSRSLEW(utmip_config->xcvr_lsrslew));
+
+ clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW(~0),
+ UTMIP_XCVR_HSSLEW(utmip_config->xcvr_hsslew));
+ clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB(~0),
+ UTMIP_XCVR_HSSLEW_MSB(utmip_config->xcvr_hsslew));
writel(val, &usbctlr->utmip_xcvr_cfg0);
+
clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
- 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
+ utmip_config->term_range_adj <<
+ UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
/* Some registers can be controlled from USB1 only. */
if (config->periph_id != PERIPH_ID_USBD) {
@@ -485,9 +505,11 @@
val = readl(&usb1ctlr->utmip_bias_cfg0);
setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
- 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
+ utmip_config->hsdiscon_level <<
+ UTMIP_HSDISCON_LEVEL_SHIFT);
clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
- 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
+ utmip_config->hssquelch_level <<
+ UTMIP_HSSQUELCH_LEVEL_SHIFT);
writel(val, &usb1ctlr->utmip_bias_cfg0);
/* Miscellaneous setting mentioned in Programming Guide */
@@ -521,7 +543,11 @@
setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
- setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
+
+ if (utmip_config->xcvr_setup_use_fuses)
+ setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
+ else
+ clrbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
/*
* Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
@@ -535,15 +561,16 @@
/* Set PLL enable delay count and Crystal frequency count */
val = readl(&usbctlr->utmip_hsrx_cfg0);
clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
- utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
+ utmip_config->idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
- utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
+ utmip_config->elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
writel(val, &usbctlr->utmip_hsrx_cfg0);
/* Configure the UTMIP_HS_SYNC_START_DLY */
clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
UTMIP_HS_SYNC_START_DLY_MASK,
- utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
+ utmip_config->hssync_start_delay <<
+ UTMIP_HS_SYNC_START_DLY_SHIFT);
/* Preceed the crystal clock disable by >100ns delay. */
udelay(1);
@@ -763,6 +790,69 @@
return 0;
}
+static void fdt_decode_usb_phy(struct udevice *dev)
+{
+ struct fdt_usb *priv = dev_get_priv(dev);
+ struct tegra_utmip_config *utmip_config = &priv->utmip_config;
+ u32 usb_phy_phandle;
+ ofnode usb_phy_node;
+ int ret;
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "nvidia,phy", &usb_phy_phandle);
+ if (ret)
+ log_debug("%s: required usb phy node isn't provided\n", __func__);
+
+ usb_phy_node = ofnode_get_by_phandle(usb_phy_phandle);
+ if (!ofnode_valid(usb_phy_node) || !ofnode_is_enabled(usb_phy_node)) {
+ log_debug("%s: failed to find usb phy node or it is disabled\n", __func__);
+ utmip_config->xcvr_setup_use_fuses = true;
+ } else {
+ utmip_config->xcvr_setup_use_fuses =
+ ofnode_read_bool(usb_phy_node, "nvidia,xcvr-setup-use-fuses");
+ }
+
+ utmip_config->hssync_start_delay =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,hssync-start-delay", 0x9);
+
+ utmip_config->elastic_limit =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,elastic-limit", 0x10);
+
+ utmip_config->idle_wait_delay =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,idle-wait-delay", 0x11);
+
+ utmip_config->term_range_adj =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,term-range-adj", 0x7);
+
+ utmip_config->xcvr_lsfslew =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,xcvr-lsfslew", 0x0);
+
+ utmip_config->xcvr_lsrslew =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,xcvr-lsrslew", 0x3);
+
+ utmip_config->xcvr_hsslew =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,xcvr-hsslew", 0x8);
+
+ utmip_config->hssquelch_level =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,hssquelch-level", 0x2);
+
+ utmip_config->hsdiscon_level =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,hsdiscon-level", 0x1);
+
+ if (!utmip_config->xcvr_setup_use_fuses) {
+ ofnode_read_u32(usb_phy_node, "nvidia,xcvr-setup",
+ &utmip_config->xcvr_setup);
+ }
+}
+
int usb_common_init(struct fdt_usb *config, enum usb_init_type init)
{
int ret = 0;
@@ -850,6 +940,8 @@
priv->type = dev_get_driver_data(dev);
+ fdt_decode_usb_phy(dev);
+
return 0;
}
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6e79694..3c3ceba 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -599,6 +599,15 @@
LCD module found in Microsoft Surface 2. The panel has a FullHD
resolution (1920x1080).
+config VIDEO_LCD_SHARP_LQ101R1SX01
+ tristate "Sharp LQ101R1SX01 2560x1600 DSI video mode panel"
+ depends on PANEL && BACKLIGHT
+ select VIDEO_MIPI_DSI
+ help
+ Say Y here if you want to enable support for Sharp LQ101R1SX01
+ LCD module found in ASUS Transformer TF701T. The panel has a
+ WQXGA resolution (2560x1600).
+
config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
---help---
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index af8b2b2..5a00438 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -64,6 +64,7 @@
obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o
obj-$(CONFIG_VIDEO_LCD_RENESAS_R69328) += renesas-r69328.o
obj-$(CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02) += samsung-ltl106hl02.o
+obj-$(CONFIG_VIDEO_LCD_SHARP_LQ101R1SX01) += sharp-lq101r1sx01.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o
obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o
diff --git a/drivers/video/sharp-lq101r1sx01.c b/drivers/video/sharp-lq101r1sx01.c
new file mode 100644
index 0000000..5d8453f
--- /dev/null
+++ b/drivers/video/sharp-lq101r1sx01.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Sharp LQ101R1SX01 DSI panel driver
+ *
+ * Copyright (C) 2014 NVIDIA Corporation
+ * Copyright (c) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <backlight.h>
+#include <dm.h>
+#include <panel.h>
+#include <log.h>
+#include <mipi_dsi.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+
+struct sharp_lq101r1sx01_priv {
+ struct udevice *backlight;
+ struct udevice *panel_sec;
+ struct udevice *vcc;
+};
+
+static struct display_timing default_timing = {
+ .pixelclock.typ = 278000000,
+ .hactive.typ = 2560,
+ .hfront_porch.typ = 128,
+ .hback_porch.typ = 64,
+ .hsync_len.typ = 64,
+ .vactive.typ = 1600,
+ .vfront_porch.typ = 4,
+ .vback_porch.typ = 8,
+ .vsync_len.typ = 32,
+};
+
+static int sharp_lq101r1sx01_write(struct mipi_dsi_device *dsi,
+ u16 offset, u8 value)
+{
+ u8 payload[3] = { offset >> 8, offset & 0xff, value };
+ int ret;
+
+ ret = mipi_dsi_generic_write(dsi, payload, sizeof(payload));
+ if (ret < 0) {
+ log_debug("%s: failed to write %02x to %04x: %zd\n",
+ __func__, value, offset, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_nop(dsi);
+ if (ret < 0) {
+ log_debug("%s: failed to send DCS nop: %zd\n",
+ __func__, ret);
+ return ret;
+ }
+
+ udelay(20);
+
+ return 0;
+}
+
+static int sharp_setup_symmetrical_split(struct mipi_dsi_device *left,
+ struct mipi_dsi_device *right,
+ struct display_timing *timing)
+{
+ int ret;
+
+ ret = mipi_dsi_dcs_set_column_address(left, 0,
+ timing->hactive.typ / 2 - 1);
+ if (ret < 0) {
+ log_debug("%s: failed to set column address: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_page_address(left, 0, timing->vactive.typ - 1);
+ if (ret < 0) {
+ log_debug("%s: failed to set page address: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_column_address(right, timing->hactive.typ / 2,
+ timing->hactive.typ - 1);
+ if (ret < 0) {
+ log_debug("%s: failed to set column address: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_page_address(right, 0, timing->vactive.typ - 1);
+ if (ret < 0) {
+ log_debug("%s: failed to set page address: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sharp_lq101r1sx01_enable_backlight(struct udevice *dev)
+{
+ struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev);
+
+ if (!priv->panel_sec)
+ return 0;
+
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+ struct mipi_dsi_panel_plat *plat_sec = dev_get_plat(priv->panel_sec);
+ struct mipi_dsi_device *link1 = plat->device;
+ struct mipi_dsi_device *link2 = plat_sec->device;
+ int ret;
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(link1);
+ if (ret < 0) {
+ log_debug("%s: failed to exit sleep mode: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* set left-right mode */
+ ret = sharp_lq101r1sx01_write(link1, 0x1000, 0x2a);
+ if (ret < 0) {
+ log_debug("%s: failed to set left-right mode: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* enable command mode */
+ ret = sharp_lq101r1sx01_write(link1, 0x1001, 0x01);
+ if (ret < 0) {
+ log_debug("%s: failed to enable command mode: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_pixel_format(link1, MIPI_DCS_PIXEL_FMT_24BIT);
+ if (ret < 0) {
+ log_debug("%s: failed to set pixel format: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /*
+ * TODO: The device supports both left-right and even-odd split
+ * configurations, but this driver currently supports only the left-
+ * right split. To support a different mode a mechanism needs to be
+ * put in place to communicate the configuration back to the DSI host
+ * controller.
+ */
+ ret = sharp_setup_symmetrical_split(link1, link2, &default_timing);
+ if (ret < 0) {
+ log_debug("%s: failed to set up symmetrical split: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_display_on(link1);
+ if (ret < 0) {
+ log_debug("%s: failed to set panel on: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(20);
+
+ return 0;
+}
+
+static int sharp_lq101r1sx01_set_backlight(struct udevice *dev, int percent)
+{
+ struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (!priv->panel_sec)
+ return 0;
+
+ ret = backlight_enable(priv->backlight);
+ if (ret)
+ return ret;
+
+ return backlight_set_brightness(priv->backlight, percent);
+}
+
+static int sharp_lq101r1sx01_timings(struct udevice *dev,
+ struct display_timing *timing)
+{
+ memcpy(timing, &default_timing, sizeof(*timing));
+ return 0;
+}
+
+static int sharp_lq101r1sx01_of_to_plat(struct udevice *dev)
+{
+ struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ /* If node has no link2 it is secondary panel */
+ if (!dev_read_bool(dev, "link2"))
+ return 0;
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
+ "link2", &priv->panel_sec);
+ if (ret) {
+ log_debug("%s: cannot get secondary panel: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+ "backlight", &priv->backlight);
+ if (ret) {
+ log_debug("%s: cannot get backlight: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+ "power-supply", &priv->vcc);
+ if (ret) {
+ log_debug("%s: cannot get power-supply: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sharp_lq101r1sx01_hw_init(struct udevice *dev)
+{
+ struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (!priv->panel_sec)
+ return 0;
+
+ ret = regulator_set_enable_if_allowed(priv->vcc, 1);
+ if (ret) {
+ log_debug("%s: enabling power-supply failed (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /*
+ * According to the datasheet, the panel needs around 10 ms to fully
+ * power up. At least another 120 ms is required before exiting sleep
+ * mode to make sure the panel is ready. Throw in another 20 ms for
+ * good measure.
+ */
+ mdelay(150);
+
+ return 0;
+}
+
+static int sharp_lq101r1sx01_probe(struct udevice *dev)
+{
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+
+ /* fill characteristics of DSI data link */
+ plat->lanes = 4;
+ plat->format = MIPI_DSI_FMT_RGB888;
+
+ return sharp_lq101r1sx01_hw_init(dev);
+}
+
+static const struct panel_ops sharp_lq101r1sx01_ops = {
+ .enable_backlight = sharp_lq101r1sx01_enable_backlight,
+ .set_backlight = sharp_lq101r1sx01_set_backlight,
+ .get_display_timing = sharp_lq101r1sx01_timings,
+};
+
+static const struct udevice_id sharp_lq101r1sx01_ids[] = {
+ { .compatible = "sharp,lq101r1sx01" },
+ { }
+};
+
+U_BOOT_DRIVER(sharp_lq101r1sx01) = {
+ .name = "sharp_lq101r1sx01",
+ .id = UCLASS_PANEL,
+ .of_match = sharp_lq101r1sx01_ids,
+ .ops = &sharp_lq101r1sx01_ops,
+ .of_to_plat = sharp_lq101r1sx01_of_to_plat,
+ .probe = sharp_lq101r1sx01_probe,
+ .plat_auto = sizeof(struct mipi_dsi_panel_plat),
+ .priv_auto = sizeof(struct sharp_lq101r1sx01_priv),
+};
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index accabbf..d24aa37 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -26,8 +26,6 @@
#include "tegra-dc.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* Holder of Tegra per-SOC DC differences */
struct tegra_dc_soc_info {
bool has_timer;
diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c
index 35a8e6c..6327266 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -20,6 +20,7 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
#include "tegra-dc.h"
#include "tegra-dsi.h"
@@ -50,6 +51,10 @@
int host_fifo_depth;
u32 version;
+
+ /* for ganged-mode support */
+ struct udevice *master;
+ struct udevice *slave;
};
static void tegra_dc_enable_controller(struct udevice *dev)
@@ -595,6 +600,17 @@
writel(value, &ptiming->dsi_bta_timing);
}
+static void tegra_dsi_ganged_enable(struct udevice *dev, unsigned int start,
+ unsigned int size)
+{
+ struct tegra_dsi_priv *priv = dev_get_priv(dev);
+ struct dsi_ganged_mode_reg *ganged = &priv->dsi->ganged;
+
+ writel(start, &ganged->ganged_mode_start);
+ writel(size << 16 | size, &ganged->ganged_mode_size);
+ writel(DSI_GANGED_MODE_CONTROL_ENABLE, &ganged->ganged_mode_ctrl);
+}
+
static void tegra_dsi_configure(struct udevice *dev,
unsigned long mode_flags)
{
@@ -679,9 +695,19 @@
writel(hact << 16 | hbp, &len->dsi_pkt_len_2_3);
writel(hfp, &len->dsi_pkt_len_4_5);
writel(0x0f0f << 16, &len->dsi_pkt_len_6_7);
+
+ /* set SOL delay (for non-burst mode only) */
+ writel(8 * mul / div, &misc->dsi_sol_delay);
} else {
- /* 1 byte (DCS command) + pixel data */
- value = 1 + timing->hactive.typ * mul / div;
+ if (priv->master || priv->slave) {
+ /*
+ * For ganged mode, assume symmetric left-right mode.
+ */
+ value = 1 + (timing->hactive.typ / 2) * mul / div;
+ } else {
+ /* 1 byte (DCS command) + pixel data */
+ value = 1 + timing->hactive.typ * mul / div;
+ }
writel(0, &len->dsi_pkt_len_0_1);
writel(value << 16, &len->dsi_pkt_len_2_3);
@@ -691,10 +717,40 @@
value = MIPI_DCS_WRITE_MEMORY_START << 8 |
MIPI_DCS_WRITE_MEMORY_CONTINUE;
writel(value, &len->dsi_dcs_cmds);
+
+ /* set SOL delay */
+ if (priv->master || priv->slave) {
+ unsigned long delay, bclk, bclk_ganged;
+ unsigned int lanes = device->lanes;
+ unsigned long htotal = timing->hactive.typ + timing->hfront_porch.typ +
+ timing->hback_porch.typ + timing->hsync_len.typ;
+
+ /* SOL to valid, valid to FIFO and FIFO write delay */
+ delay = 4 + 4 + 2;
+ delay = DIV_ROUND_UP(delay * mul, div * lanes);
+ /* FIFO read delay */
+ delay = delay + 6;
+
+ bclk = DIV_ROUND_UP(htotal * mul, div * lanes);
+ bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
+ value = bclk - bclk_ganged + delay + 20;
+ } else {
+ /* TODO: revisit for non-ganged mode */
+ value = 8 * mul / div;
+ }
+
+ writel(value, &misc->dsi_sol_delay);
}
- /* set SOL delay (for non-burst mode only) */
- writel(8 * mul / div, &misc->dsi_sol_delay);
+ if (priv->slave) {
+ /*
+ * TODO: Support modes other than symmetrical left-right
+ * split.
+ */
+ tegra_dsi_ganged_enable(dev, 0, timing->hactive.typ / 2);
+ tegra_dsi_ganged_enable(priv->slave, timing->hactive.typ / 2,
+ timing->hactive.typ / 2);
+ }
}
static int tegra_dsi_encoder_enable(struct udevice *dev)
@@ -774,6 +830,9 @@
value |= DSI_POWER_CONTROL_ENABLE;
writel(value, &misc->dsi_pwr_ctrl);
+ if (priv->slave)
+ tegra_dsi_encoder_enable(priv->slave);
+
return 0;
}
@@ -803,6 +862,14 @@
unsigned int mul, div;
unsigned long bclk, plld;
+ if (!priv->slave) {
+ /* Change DSIB clock parent to match DSIA */
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+ clrbits_le32(&clkrst->plld2.pll_base, BIT(25)); /* DSIB_CLK_SRC */
+ }
+
tegra_dsi_get_muldiv(device->format, &mul, &div);
bclk = (priv->timing.pixelclock.typ * mul) /
@@ -854,6 +921,24 @@
reset_set_enable(priv->dsi_clk, 0);
}
+static int tegra_dsi_ganged_probe(struct udevice *dev)
+{
+ struct tegra_dsi_priv *mpriv = dev_get_priv(dev);
+ struct udevice *gangster;
+
+ uclass_get_device_by_phandle(UCLASS_PANEL, dev,
+ "nvidia,ganged-mode", &gangster);
+ if (gangster) {
+ /* Ganged mode is set */
+ struct tegra_dsi_priv *spriv = dev_get_priv(gangster);
+
+ mpriv->slave = gangster;
+ spriv->master = dev;
+ }
+
+ return 0;
+}
+
static int tegra_dsi_bridge_probe(struct udevice *dev)
{
struct tegra_dsi_priv *priv = dev_get_priv(dev);
@@ -873,6 +958,8 @@
priv->video_fifo_depth = 1920;
priv->host_fifo_depth = 64;
+ tegra_dsi_ganged_probe(dev);
+
ret = reset_get_by_name(dev, "dsi", &reset_ctl);
if (ret) {
log_debug("%s: reset_get_by_name() failed: %d\n",
diff --git a/drivers/video/tegra20/tegra-dsi.h b/drivers/video/tegra20/tegra-dsi.h
index 69dac4b..683c5e3 100644
--- a/drivers/video/tegra20/tegra-dsi.h
+++ b/drivers/video/tegra20/tegra-dsi.h
@@ -98,9 +98,9 @@
uint dsi_to_tally; /* _DSI_TO_TALLY_0 */
};
-/* DSI PAD control register 0x04b ~ 0x04e */
+/* DSI PAD control register 0x04b ~ 0x052 */
struct dsi_pad_ctrl_reg {
- /* Address 0x04b ~ 0x04e */
+ /* Address 0x04b ~ 0x052 */
uint pad_ctrl; /* _PAD_CONTROL_0 */
uint pad_ctrl_cd; /* _PAD_CONTROL_CD_0 */
uint pad_cd_status; /* _PAD_CD_STATUS_0 */
@@ -111,6 +111,14 @@
uint pad_ctrl_4; /* _PAD_CONTROL_4 */
};
+/* DSI ganged mode register 0x053 ~ 0x04e */
+struct dsi_ganged_mode_reg {
+ /* Address 0x053 ~ 0x055 */
+ uint ganged_mode_ctrl; /* _DSI_GANGED_MODE_CONTROL_0 */
+ uint ganged_mode_start; /* _DSI_GANGED_MODE_START_0 */
+ uint ganged_mode_size; /* _DSI_GANGED_MODE_SIZE_0 */
+};
+
/* Display Serial Interface (DSI_) regs */
struct dsi_ctlr {
struct dsi_syncpt_reg syncpt; /* SYNCPT register 0x000 ~ 0x002 */
@@ -133,6 +141,7 @@
uint reserved5[4]; /* reserved_5[4] */
struct dsi_pad_ctrl_reg pad; /* PAD registers 0x04b ~ 0x04e */
+ struct dsi_ganged_mode_reg ganged; /* GANGED registers 0x053 ~ 0x055 */
};
#define DSI_POWER_CONTROL_ENABLE BIT(0)
@@ -202,6 +211,8 @@
#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
+#define DSI_GANGED_MODE_CONTROL_ENABLE BIT(0)
+
/*
* pixel format as used in the DSI_CONTROL_FORMAT field
*/
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi
index b29ce73..e88c1fb 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi
@@ -914,6 +914,8 @@
dmas = <&dma 48>, <&dma 48>;
dma-names = "rx", "tx";
resets = <&r_ccu RST_R_APB2_I2C>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_i2c_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
index afb49e6..f01ace6 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
@@ -201,12 +201,12 @@
vcc-pi-supply = <®_cldo3>;
};
-&r_rsb {
+&r_i2c {
status = "okay";
- axp717: pmic@3a3 {
+ axp717: pmic@34 {
compatible = "x-powers,axp717";
- reg = <0x3a3>;
+ reg = <0x34>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&nmi_intc>;
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index 71d4727..4c690a1 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -18,64 +18,6 @@
#define FDT_MODULE "apalis-v1.2"
#define FDT_MODULE_V1_0 "apalis"
-/*
- * Custom Distro Boot configuration:
- * 1. 8bit SD port (MMC1)
- * 2. 4bit SD port (MMC2)
- * 3. eMMC (MMC0)
- */
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 1) \
- func(MMC, mmc, 2) \
- func(MMC, mmc, 0) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-
-#define DFU_ALT_EMMC_INFO "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \
- "boot part 0 1 mmcpart 0; " \
- "rootfs part 0 2 mmcpart 0; " \
- "zImage fat 0 1 mmcpart 0; " \
- "tegra124-apalis-eval.dtb fat 0 1 mmcpart 0"
-
-#define UBOOT_UPDATE \
- "uboot_hwpart=1\0" \
- "uboot_blk=0\0" \
- "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
- "setexpr blkcnt ${blkcnt} / 0x200\0" \
- "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
- "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
-
-#define BOARD_EXTRA_ENV_SETTINGS \
- "boot_file=zImage\0" \
- "boot_script_dhcp=boot.scr\0" \
- "console=ttyS0\0" \
- "defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \
- "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \
- "user_debug=30 pcie_aspm=off\0" \
- "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
- "fdt_board=eval\0" \
- "fdt_fixup=;\0" \
- "fdt_module=" FDT_MODULE "\0" \
- UBOOT_UPDATE \
- "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
- "00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \
- "flash_eth.img && source ${loadaddr}\0" \
- "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \
- "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \
- "|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1 " \
- "${loadaddr} flash_blk.img && " \
- "source ${loadaddr}\0" \
- "setup=setenv setupargs igb_mac=${ethaddr} " \
- "consoleblank=0 no_console_suspend=1 console=tty1 " \
- "console=${console},${baudrate}n8 debug_uartport=lsport,0 " \
- "${memargs}\0" \
- "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
- "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
- "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
- "source ${loadaddr}\0" \
- "vidargs=fbcon=map:1\0"
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 80204d7..87a679e 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -22,18 +22,6 @@
*/
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define UBOOT_UPDATE \
- "uboot_hwpart=1\0" \
- "uboot_blk=0\0" \
- "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
- "setexpr blkcnt ${blkcnt} / 0x200\0" \
- "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
- "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
-
-#define BOARD_EXTRA_ENV_SETTINGS \
- UBOOT_UPDATE \
- "boot_script_dhcp=boot.scr\0"
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 82729eb..3412b88 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -13,10 +13,6 @@
/* High-level configuration options */
#define CFG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
-#define BOARD_EXTRA_ENV_SETTINGS \
- "board_name=cardhu-a04\0" \
- "fdtfile=tegra30-cardhu-a04.dtb\0"
-
/* Board-specific serial config */
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index ea7d648..bc616d1 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -13,17 +13,6 @@
/* Board-specific serial config */
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-/* NAND support */
-
-#define UBOOT_UPDATE \
- "update_uboot=nand erase.part u-boot && " \
- "nand write ${loadaddr} u-boot ${filesize}\0" \
-
-/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
-#define BOARD_EXTRA_ENV_SETTINGS \
- "boot_script_dhcp=boot.scr\0" \
- UBOOT_UPDATE
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 7edb2c0..1f47466 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -23,18 +23,6 @@
*/
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define UBOOT_UPDATE \
- "uboot_hwpart=1\0" \
- "uboot_blk=0\0" \
- "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
- "setexpr blkcnt ${blkcnt} / 0x200\0" \
- "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
- "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
-
-#define BOARD_EXTRA_ENV_SETTINGS \
- UBOOT_UPDATE \
- "boot_script_dhcp=boot.scr\0"
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h
index 348078f..33d0021 100644
--- a/include/configs/endeavoru.h
+++ b/include/configs/endeavoru.h
@@ -10,54 +10,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <linux/sizes.h>
-
#include "tegra30-common.h"
/* High-level configuration options */
#define CFG_TEGRA_BOARD_STRING "HTC One X"
-#define ENDEAVORU_FLASH_UBOOT \
- "flash_uboot=echo Preparing RAM;" \
- "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
- "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
- "echo Reading BCT;" \
- "mmc dev 0 1;" \
- "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \
- "echo Reading bootloader;" \
- "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \
- "then echo Calculating bootloader size;" \
- "size mmc 0:1 ${bootloader_file};" \
- "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
- "echo Writing bootloader to eMMC;" \
- "mmc dev 0 1;" \
- "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \
- "mmc dev 0 2;" \
- "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \
- "echo Bootloader written successfully;" \
- "pause 'Press ANY key to reboot device...'; reset;" \
- "else echo Reading bootloader failed;" \
- "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0"
-
-#define ENDEAVORU_BOOTMENU \
- ENDEAVORU_FLASH_UBOOT \
- "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
- "bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
- "bootmenu_2=update bootloader=run flash_uboot\0" \
- "bootmenu_3=reboot RCM=enterrcm\0" \
- "bootmenu_4=reboot=reset\0" \
- "bootmenu_5=power off=poweroff\0" \
- "bootmenu_delay=-1\0"
-
-#define BOARD_EXTRA_ENV_SETTINGS \
- "boot_block_size_r=0x200000\0" \
- "boot_block_size=0x1000\0" \
- "bootloader_file=u-boot-dtb-tegra.bin\0" \
- "button_cmd_0_name=Volume Down\0" \
- "button_cmd_0=bootmenu\0" \
- "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
- ENDEAVORU_BOOTMENU
-
/* Board-specific serial config */
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
diff --git a/include/configs/grouper.h b/include/configs/grouper.h
index 8064b88..b6ef6ff 100644
--- a/include/configs/grouper.h
+++ b/include/configs/grouper.h
@@ -6,56 +6,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <linux/sizes.h>
-
#include "tegra30-common.h"
/* High-level configuration options */
#define CFG_TEGRA_BOARD_STRING "ASUS Google Nexus 7 (2012)"
-#define GROUPER_FLASH_UBOOT \
- "flash_uboot=echo Preparing RAM;" \
- "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
- "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
- "echo Reading BCT;" \
- "mmc dev 0 1;" \
- "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \
- "echo Reading bootloader;" \
- "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \
- "then echo Calculating bootloader size;" \
- "size mmc 0:1 ${bootloader_file};" \
- "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
- "echo Writing bootloader to eMMC;" \
- "mmc dev 0 1;" \
- "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \
- "mmc dev 0 2;" \
- "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \
- "echo Bootloader written successfully;" \
- "pause 'Press ANY key to reboot device...'; reset;" \
- "else echo Reading bootloader failed;" \
- "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0"
-
-#define GROUPER_BOOTMENU \
- GROUPER_FLASH_UBOOT \
- "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
- "bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
- "bootmenu_2=update bootloader=run flash_uboot\0" \
- "bootmenu_3=reboot RCM=enterrcm\0" \
- "bootmenu_4=reboot=reset\0" \
- "bootmenu_5=power off=poweroff\0" \
- "bootmenu_delay=-1\0"
-
-#define BOARD_EXTRA_ENV_SETTINGS \
- "boot_block_size_r=0x200000\0" \
- "boot_block_size=0x1000\0" \
- "bootloader_file=u-boot-dtb-tegra.bin\0" \
- "button_cmd_0_name=Volume Down\0" \
- "button_cmd_0=bootmenu\0" \
- "button_cmd_1_name=Lid\0" \
- "button_cmd_1=poweroff\0" \
- "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
- GROUPER_BOOTMENU
-
/* Board-specific serial config */
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
diff --git a/include/configs/ideapad-yoga-11.h b/include/configs/ideapad-yoga-11.h
index 12c7649..c4e6b2a 100644
--- a/include/configs/ideapad-yoga-11.h
+++ b/include/configs/ideapad-yoga-11.h
@@ -11,64 +11,6 @@
/* High-level configuration options */
#define CFG_TEGRA_BOARD_STRING "Lenovo Ideapad Yoga 11"
-#define IDEAPAD_FLASH_UBOOT \
- "flash_uboot=sf probe 0:1;" \
- "echo Dumping current SPI flash content ...;" \
- "sf read ${kernel_addr_r} 0x0 ${spi_size};" \
- "if fatwrite mmc 1:1 ${kernel_addr_r} spi-flash-backup.bin ${spi_size};" \
- "then echo SPI flash content was successfully written into spi-flash-backup.bin;" \
- "echo Reading SPI flash binary;" \
- "if load mmc 1:1 ${kernel_addr_r} repart-block.bin;" \
- "then echo Writing bootloader into SPI flash;" \
- "sf probe 0:1;" \
- "sf update ${kernel_addr_r} 0x0 ${spi_size};" \
- "echo Bootloader SUCCESSFULLY written into SPI flash;" \
- "pause 'Press ANY key to reboot...'; reset;" \
- "else echo Preparing RAM;" \
- "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
- "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
- "echo Reading BCT;" \
- "sf read ${kernel_addr_r} 0x0 ${boot_block_size_r};" \
- "echo Reading bootloader;" \
- "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \
- "then echo Calculating bootloader size;" \
- "size mmc 1:1 ${bootloader_file};" \
- "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
- "echo Writing bootloader into SPI flash;" \
- "sf probe 0:1;" \
- "sf update ${kernel_addr_r} 0x0 ${boot_block_size_r};" \
- "sf update ${ramdisk_addr_r} ${boot_block_size_r} ${boot_block_size_r};" \
- "echo Bootloader written SUCCESSFULLY;" \
- "pause 'Press ANY key to reboot...'; reset;" \
- "else echo Reading bootloader failed;" \
- "pause 'Press ANY key to reboot...'; reset; fi;" \
- "fi;" \
- "else echo SPI flash backup FAILED! Aborting ...;" \
- "pause 'Press ANY key to reboot...'; reset; fi\0"
-
-#define IDEAPAD_BOOTMENU \
- IDEAPAD_FLASH_UBOOT \
- "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
- "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \
- "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
- "bootmenu_3=update bootloader=run flash_uboot\0" \
- "bootmenu_4=reboot RCM=enterrcm\0" \
- "bootmenu_5=reboot=reset\0" \
- "bootmenu_6=power off=poweroff\0" \
- "bootmenu_delay=-1\0"
-
-#define BOARD_EXTRA_ENV_SETTINGS \
- "spi_size=0x400000\0" \
- "boot_block_size_r=0x200000\0" \
- "boot_block_size=0x1000\0" \
- "bootloader_file=u-boot-dtb-tegra.bin\0" \
- "button_cmd_0_name=Volume Down\0" \
- "button_cmd_0=bootmenu\0" \
- "button_cmd_1_name=Lid sensor\0" \
- "button_cmd_1=poweroff\0" \
- "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
- IDEAPAD_BOOTMENU
-
/* Board-specific serial config */
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h
index e409cc3..fc1b7c0 100644
--- a/include/configs/p2771-0000.h
+++ b/include/configs/p2771-0000.h
@@ -15,26 +15,6 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define BOARD_EXTRA_ENV_SETTINGS \
- "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \
- "ramdisk_addr_r\0" \
- "kernel_addr_r_align=00200000\0" \
- "kernel_addr_r_offset=00080000\0" \
- "kernel_addr_r_size=02000000\0" \
- "kernel_addr_r_aliases=loadaddr\0" \
- "fdt_addr_r_align=00200000\0" \
- "fdt_addr_r_offset=00000000\0" \
- "fdt_addr_r_size=00200000\0" \
- "scriptaddr_align=00200000\0" \
- "scriptaddr_offset=00000000\0" \
- "scriptaddr_size=00200000\0" \
- "pxefile_addr_r_align=00200000\0" \
- "pxefile_addr_r_offset=00000000\0" \
- "pxefile_addr_r_size=00200000\0" \
- "ramdisk_addr_r_align=00200000\0" \
- "ramdisk_addr_r_offset=00000000\0" \
- "ramdisk_addr_r_size=02000000\0"
-
#include "tegra-common-post.h"
#endif
diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h
index e60f42e..1138c1d 100644
--- a/include/configs/p3450-0000.h
+++ b/include/configs/p3450-0000.h
@@ -15,19 +15,6 @@
/* Board-specific serial config */
-/* Only MMC/PXE/DHCP for now, add USB back in later when supported */
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 1) \
- func(MMC, mmc, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-
-#define BOARD_EXTRA_ENV_SETTINGS \
- "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
- "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
- "source ${scriptaddr}; " \
- "fi\0"
-
/* General networking support */
#include "tegra-common-post.h"
diff --git a/include/configs/qc750.h b/include/configs/qc750.h
index ce6665d..ad9f914 100644
--- a/include/configs/qc750.h
+++ b/include/configs/qc750.h
@@ -15,48 +15,6 @@
/* High-level configuration options */
#define CFG_TEGRA_BOARD_STRING "Wexler QC750"
-#define QC750_FLASH_UBOOT \
- "flash_uboot=echo Preparing RAM;" \
- "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
- "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
- "echo Reading BCT;" \
- "mmc dev 0 1;" \
- "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \
- "echo Reading bootloader;" \
- "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \
- "then echo Calculating bootloader size;" \
- "size mmc 1:1 ${bootloader_file};" \
- "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
- "echo Writing bootloader to eMMC;" \
- "mmc dev 0 1;" \
- "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \
- "mmc dev 0 2;" \
- "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \
- "echo Bootloader written successfully;" \
- "pause 'Press ANY key to reboot device...'; reset;" \
- "else echo Reading bootloader failed;" \
- "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0"
-
-#define QC750_BOOTMENU \
- QC750_FLASH_UBOOT \
- "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
- "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \
- "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
- "bootmenu_3=update bootloader=run flash_uboot\0" \
- "bootmenu_4=reboot RCM=enterrcm\0" \
- "bootmenu_5=reboot=reset\0" \
- "bootmenu_6=power off=poweroff\0" \
- "bootmenu_delay=-1\0"
-
-#define BOARD_EXTRA_ENV_SETTINGS \
- "boot_block_size_r=0x200000\0" \
- "boot_block_size=0x1000\0" \
- "bootloader_file=u-boot-dtb-tegra.bin\0" \
- "button_cmd_0_name=Volume Down\0" \
- "button_cmd_0=bootmenu\0" \
- "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
- QC750_BOOTMENU
-
/* Board-specific serial config */
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
diff --git a/include/configs/surface-rt.h b/include/configs/surface-rt.h
index 30f6450..1f0837e 100644
--- a/include/configs/surface-rt.h
+++ b/include/configs/surface-rt.h
@@ -13,24 +13,6 @@
/* High-level configuration options */
#define CFG_TEGRA_BOARD_STRING "Microsoft Surface RT"
-#define SURFACE_RT_BOOTMENU \
- "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
- "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \
- "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
- "bootmenu_3=boot from USB=usb reset; usb start; bootflow scan\0" \
- "bootmenu_4=reboot RCM=enterrcm\0" \
- "bootmenu_5=reboot=reset\0" \
- "bootmenu_6=power off=poweroff\0" \
- "bootmenu_delay=-1\0"
-
-#define BOARD_EXTRA_ENV_SETTINGS \
- "button_cmd_0_name=Volume Down\0" \
- "button_cmd_0=bootmenu\0" \
- "button_cmd_1_name=Hall Sensor\0" \
- "button_cmd_1=poweroff\0" \
- "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
- SURFACE_RT_BOOTMENU
-
/* Board-specific serial config */
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
diff --git a/include/configs/transformer-common.h b/include/configs/transformer-common.h
deleted file mode 100644
index bb6817c..0000000
--- a/include/configs/transformer-common.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2022, Svyatoslav Ryhel <clamor95@gmail.com>.
- */
-
-#ifndef __TRANSFORMER_COMMON_H
-#define __TRANSFORMER_COMMON_H
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "ASUS Transformer"
-
-#define TRANSFORMER_FLASH_UBOOT \
- "flash_uboot=echo Preparing RAM;" \
- "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
- "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
- "echo Reading BCT;" \
- "mmc dev 0 1;" \
- "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \
- "echo Reading bootloader;" \
- "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \
- "then echo Calculating bootloader size;" \
- "size mmc 1:1 ${bootloader_file};" \
- "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
- "echo Writing bootloader to eMMC;" \
- "mmc dev 0 1;" \
- "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \
- "mmc dev 0 2;" \
- "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \
- "echo Bootloader written successfully;" \
- "pause 'Press ANY key to reboot device...'; reset;" \
- "else echo Reading bootloader failed;" \
- "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0"
-
-#define TRANSFORMER_FLASH_SPI \
- "update_spi=sf probe 0:1;" \
- "echo Dumping current SPI flash content ...;" \
- "sf read ${kernel_addr_r} 0x0 ${spi_size};" \
- "if fatwrite mmc 1:1 ${kernel_addr_r} spi-flash-backup.bin ${spi_size};" \
- "then echo SPI flash content was successfully written into spi-flash-backup.bin;" \
- "echo Reading SPI flash binary;" \
- "if load mmc 1:1 ${kernel_addr_r} repart-block.bin;" \
- "then echo Writing bootloader into SPI flash;" \
- "sf probe 0:1;" \
- "sf update ${kernel_addr_r} 0x0 ${spi_size};" \
- "poweroff;" \
- "else echo Preparing RAM;" \
- "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
- "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
- "echo Reading BCT;" \
- "sf read ${kernel_addr_r} 0x0 ${boot_block_size_r};" \
- "echo Reading bootloader;" \
- "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \
- "then echo Calculating bootloader size;" \
- "size mmc 1:1 ${bootloader_file};" \
- "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
- "echo Writing bootloader into SPI flash;" \
- "sf probe 0:1;" \
- "sf update ${kernel_addr_r} 0x0 ${boot_block_size_r};" \
- "sf update ${ramdisk_addr_r} ${boot_block_size_r} ${boot_block_size_r};" \
- "echo Bootloader written successfully; poweroff;" \
- "else echo Reading bootloader failed;" \
- "poweroff; fi;" \
- "fi;" \
- "else echo SPI flash backup FAILED! Aborting ...;" \
- "poweroff; fi\0"
-
-#define TRANSFORMER_BOOTMENU \
- TRANSFORMER_FLASH_UBOOT \
- TRANSFORMER_FLASH_SPI \
- "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
- "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \
- "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
- "bootmenu_3=update bootloader=run flash_uboot\0" \
- "bootmenu_4=reboot RCM=enterrcm\0" \
- "bootmenu_5=reboot=reset\0" \
- "bootmenu_6=power off=poweroff\0" \
- "bootmenu_delay=-1\0"
-
-#define BOARD_EXTRA_ENV_SETTINGS \
- "spi_size=0x400000\0" \
- "boot_block_size_r=0x200000\0" \
- "boot_block_size=0x1000\0" \
- "bootloader_file=u-boot-dtb-tegra.bin\0" \
- "button_cmd_0_name=Volume Down\0" \
- "button_cmd_0=bootmenu\0" \
- "button_cmd_1_name=Lid sensor\0" \
- "button_cmd_1=poweroff\0" \
- "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
- TRANSFORMER_BOOTMENU
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/transformer-t20.h b/include/configs/transformer-t20.h
index ca1e70c..6a3d9b2 100644
--- a/include/configs/transformer-t20.h
+++ b/include/configs/transformer-t20.h
@@ -11,7 +11,9 @@
#define __CONFIG_H
#include "tegra20-common.h"
-#include "transformer-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING "ASUS Transformer"
/* Board-specific serial config */
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h
index d2a16f12..792b958 100644
--- a/include/configs/transformer-t30.h
+++ b/include/configs/transformer-t30.h
@@ -10,10 +10,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <linux/sizes.h>
-
#include "tegra30-common.h"
-#include "transformer-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING "ASUS Transformer"
/* Board-specific serial config */
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h
index 78a2012..c152af9 100644
--- a/include/configs/x3-t30.h
+++ b/include/configs/x3-t30.h
@@ -10,55 +10,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <linux/sizes.h>
-
#include "tegra30-common.h"
/* High-level configuration options */
#define CFG_TEGRA_BOARD_STRING "LG X3 Board"
-#define X3_FLASH_UBOOT \
- "flash_uboot=echo Preparing RAM;" \
- "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
- "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
- "echo Reading BCT;" \
- "mmc dev 0 1;" \
- "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \
- "echo Reading bootloader;" \
- "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \
- "then echo Calculating bootloader size;" \
- "size mmc 0:1 ${bootloader_file};" \
- "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
- "echo Writing bootloader to eMMC;" \
- "mmc dev 0 1;" \
- "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \
- "mmc dev 0 2;" \
- "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \
- "echo Bootloader written successfully;" \
- "pause 'Press ANY key to reboot device...'; reset;" \
- "else echo Reading bootloader failed;" \
- "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0"
-
-#define X3_BOOTMENU \
- X3_FLASH_UBOOT \
- "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
- "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \
- "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
- "bootmenu_3=update bootloader=run flash_uboot\0" \
- "bootmenu_4=reboot RCM=enterrcm\0" \
- "bootmenu_5=reboot=reset\0" \
- "bootmenu_6=power off=poweroff\0" \
- "bootmenu_delay=-1\0"
-
-#define BOARD_EXTRA_ENV_SETTINGS \
- "boot_block_size_r=0x200000\0" \
- "boot_block_size=0x1000\0" \
- "bootloader_file=u-boot-dtb-tegra.bin\0" \
- "button_cmd_0_name=Volume Down\0" \
- "button_cmd_0=bootmenu\0" \
- "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
- X3_BOOTMENU
-
/* Board-specific serial config */
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h
deleted file mode 100644
index 6f8f01e..0000000
--- a/include/dt-bindings/clock/sun50i-h616-ccu.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (C) 2020 Arm Ltd.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_
-#define _DT_BINDINGS_CLK_SUN50I_H616_H_
-
-#define CLK_PLL_PERIPH0 4
-
-#define CLK_CPUX 21
-
-#define CLK_APB1 26
-
-#define CLK_DE 29
-#define CLK_BUS_DE 30
-#define CLK_DEINTERLACE 31
-#define CLK_BUS_DEINTERLACE 32
-#define CLK_G2D 33
-#define CLK_BUS_G2D 34
-#define CLK_GPU0 35
-#define CLK_BUS_GPU 36
-#define CLK_GPU1 37
-#define CLK_CE 38
-#define CLK_BUS_CE 39
-#define CLK_VE 40
-#define CLK_BUS_VE 41
-#define CLK_BUS_DMA 42
-#define CLK_BUS_HSTIMER 43
-#define CLK_AVS 44
-#define CLK_BUS_DBG 45
-#define CLK_BUS_PSI 46
-#define CLK_BUS_PWM 47
-#define CLK_BUS_IOMMU 48
-
-#define CLK_MBUS_DMA 50
-#define CLK_MBUS_VE 51
-#define CLK_MBUS_CE 52
-#define CLK_MBUS_TS 53
-#define CLK_MBUS_NAND 54
-#define CLK_MBUS_G2D 55
-
-#define CLK_NAND0 57
-#define CLK_NAND1 58
-#define CLK_BUS_NAND 59
-#define CLK_MMC0 60
-#define CLK_MMC1 61
-#define CLK_MMC2 62
-#define CLK_BUS_MMC0 63
-#define CLK_BUS_MMC1 64
-#define CLK_BUS_MMC2 65
-#define CLK_BUS_UART0 66
-#define CLK_BUS_UART1 67
-#define CLK_BUS_UART2 68
-#define CLK_BUS_UART3 69
-#define CLK_BUS_UART4 70
-#define CLK_BUS_UART5 71
-#define CLK_BUS_I2C0 72
-#define CLK_BUS_I2C1 73
-#define CLK_BUS_I2C2 74
-#define CLK_BUS_I2C3 75
-#define CLK_BUS_I2C4 76
-#define CLK_SPI0 77
-#define CLK_SPI1 78
-#define CLK_BUS_SPI0 79
-#define CLK_BUS_SPI1 80
-#define CLK_EMAC_25M 81
-#define CLK_BUS_EMAC0 82
-#define CLK_BUS_EMAC1 83
-#define CLK_TS 84
-#define CLK_BUS_TS 85
-#define CLK_BUS_THS 86
-#define CLK_SPDIF 87
-#define CLK_BUS_SPDIF 88
-#define CLK_DMIC 89
-#define CLK_BUS_DMIC 90
-#define CLK_AUDIO_CODEC_1X 91
-#define CLK_AUDIO_CODEC_4X 92
-#define CLK_BUS_AUDIO_CODEC 93
-#define CLK_AUDIO_HUB 94
-#define CLK_BUS_AUDIO_HUB 95
-#define CLK_USB_OHCI0 96
-#define CLK_USB_PHY0 97
-#define CLK_USB_OHCI1 98
-#define CLK_USB_PHY1 99
-#define CLK_USB_OHCI2 100
-#define CLK_USB_PHY2 101
-#define CLK_USB_OHCI3 102
-#define CLK_USB_PHY3 103
-#define CLK_BUS_OHCI0 104
-#define CLK_BUS_OHCI1 105
-#define CLK_BUS_OHCI2 106
-#define CLK_BUS_OHCI3 107
-#define CLK_BUS_EHCI0 108
-#define CLK_BUS_EHCI1 109
-#define CLK_BUS_EHCI2 110
-#define CLK_BUS_EHCI3 111
-#define CLK_BUS_OTG 112
-#define CLK_BUS_KEYADC 113
-#define CLK_HDMI 114
-#define CLK_HDMI_SLOW 115
-#define CLK_HDMI_CEC 116
-#define CLK_BUS_HDMI 117
-#define CLK_BUS_TCON_TOP 118
-#define CLK_TCON_TV0 119
-#define CLK_TCON_TV1 120
-#define CLK_BUS_TCON_TV0 121
-#define CLK_BUS_TCON_TV1 122
-#define CLK_TVE0 123
-#define CLK_BUS_TVE_TOP 124
-#define CLK_BUS_TVE0 125
-#define CLK_HDCP 126
-#define CLK_BUS_HDCP 127
-#define CLK_PLL_SYSTEM_32K 128
-
-#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */
diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h
deleted file mode 100644
index 1bd8bb0..0000000
--- a/include/dt-bindings/reset/sun50i-h616-ccu.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (C) 2020 Arm Ltd.
- */
-
-#ifndef _DT_BINDINGS_RESET_SUN50I_H616_H_
-#define _DT_BINDINGS_RESET_SUN50I_H616_H_
-
-#define RST_MBUS 0
-#define RST_BUS_DE 1
-#define RST_BUS_DEINTERLACE 2
-#define RST_BUS_GPU 3
-#define RST_BUS_CE 4
-#define RST_BUS_VE 5
-#define RST_BUS_DMA 6
-#define RST_BUS_HSTIMER 7
-#define RST_BUS_DBG 8
-#define RST_BUS_PSI 9
-#define RST_BUS_PWM 10
-#define RST_BUS_IOMMU 11
-#define RST_BUS_DRAM 12
-#define RST_BUS_NAND 13
-#define RST_BUS_MMC0 14
-#define RST_BUS_MMC1 15
-#define RST_BUS_MMC2 16
-#define RST_BUS_UART0 17
-#define RST_BUS_UART1 18
-#define RST_BUS_UART2 19
-#define RST_BUS_UART3 20
-#define RST_BUS_UART4 21
-#define RST_BUS_UART5 22
-#define RST_BUS_I2C0 23
-#define RST_BUS_I2C1 24
-#define RST_BUS_I2C2 25
-#define RST_BUS_I2C3 26
-#define RST_BUS_I2C4 27
-#define RST_BUS_SPI0 28
-#define RST_BUS_SPI1 29
-#define RST_BUS_EMAC0 30
-#define RST_BUS_EMAC1 31
-#define RST_BUS_TS 32
-#define RST_BUS_THS 33
-#define RST_BUS_SPDIF 34
-#define RST_BUS_DMIC 35
-#define RST_BUS_AUDIO_CODEC 36
-#define RST_BUS_AUDIO_HUB 37
-#define RST_USB_PHY0 38
-#define RST_USB_PHY1 39
-#define RST_USB_PHY2 40
-#define RST_USB_PHY3 41
-#define RST_BUS_OHCI0 42
-#define RST_BUS_OHCI1 43
-#define RST_BUS_OHCI2 44
-#define RST_BUS_OHCI3 45
-#define RST_BUS_EHCI0 46
-#define RST_BUS_EHCI1 47
-#define RST_BUS_EHCI2 48
-#define RST_BUS_EHCI3 49
-#define RST_BUS_OTG 50
-#define RST_BUS_HDMI 51
-#define RST_BUS_HDMI_SUB 52
-#define RST_BUS_TCON_TOP 53
-#define RST_BUS_TCON_TV0 54
-#define RST_BUS_TCON_TV1 55
-#define RST_BUS_TVE_TOP 56
-#define RST_BUS_TVE0 57
-#define RST_BUS_HDCP 58
-#define RST_BUS_KEYADC 59
-
-#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
diff --git a/include/env/nvidia/prod_upd.env b/include/env/nvidia/prod_upd.env
new file mode 100644
index 0000000..f4e3819
--- /dev/null
+++ b/include/env/nvidia/prod_upd.env
@@ -0,0 +1,60 @@
+boot_block_size_r=0x200000
+boot_block_size=0x1000
+bootloader_file=u-boot-dtb-tegra.bin
+spi_size=0x400000
+boot_dev=0
+
+flash_uboot=echo Preparing RAM;
+ mw ${kernel_addr_r} 0 ${boot_block_size_r};
+ mw ${ramdisk_addr_r} 0 ${boot_block_size_r};
+ echo Reading BCT;
+ mmc dev 0 1;
+ mmc read ${kernel_addr_r} 0 ${boot_block_size};
+ echo Reading bootloader;
+ if load mmc ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file};
+ then echo Calculating bootloader size;
+ size mmc ${boot_dev}:1 ${bootloader_file};
+ ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};
+ echo Writing bootloader to eMMC;
+ mmc dev 0 1;
+ mmc write ${kernel_addr_r} 0 ${boot_block_size};
+ mmc dev 0 2;
+ mmc write ${ramdisk_addr_r} 0 ${boot_block_size};
+ echo Bootloader written successfully;
+ pause 'Press ANY key to reboot device...'; reset;
+ else echo Reading bootloader failed;
+ pause 'Press ANY key to return to bootmenu...'; bootmenu; fi
+
+update_spi=sf probe 0:1;
+ echo Dumping current SPI flash content ...;
+ sf read ${kernel_addr_r} 0x0 ${spi_size};
+ if fatwrite mmc 1:1 ${kernel_addr_r} spi-flash-backup.bin ${spi_size};
+ then echo SPI flash content was successfully written into spi-flash-backup.bin;
+ echo Reading SPI flash binary;
+ if load mmc 1:1 ${kernel_addr_r} repart-block.bin;
+ then echo Writing bootloader into SPI flash;
+ sf probe 0:1;
+ sf update ${kernel_addr_r} 0x0 ${spi_size};
+ echo Bootloader SUCCESSFULLY written into SPI flash;
+ pause 'Press ANY key to reboot...'; reset;
+ else echo Preparing RAM;
+ mw ${kernel_addr_r} 0 ${boot_block_size_r};
+ mw ${ramdisk_addr_r} 0 ${boot_block_size_r};
+ echo Reading BCT;
+ sf read ${kernel_addr_r} 0x0 ${boot_block_size_r};
+ echo Reading bootloader;
+ if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};
+ then echo Calculating bootloader size;
+ size mmc 1:1 ${bootloader_file};
+ ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};
+ echo Writing bootloader into SPI flash;
+ sf probe 0:1;
+ sf update ${kernel_addr_r} 0x0 ${boot_block_size_r};
+ sf update ${ramdisk_addr_r} ${boot_block_size_r} ${boot_block_size_r};
+ echo Bootloader written SUCCESSFULLY;
+ pause 'Press ANY key to reboot...'; reset;
+ else echo Reading bootloader failed;
+ pause 'Press ANY key to reboot...'; reset; fi;
+ fi;
+ else echo SPI flash backup FAILED! Aborting ...;
+ pause 'Press ANY key to reboot...'; reset; fi
diff --git a/include/spl_gpio.h b/include/spl_gpio.h
index e39ac3f..b33261a 100644
--- a/include/spl_gpio.h
+++ b/include/spl_gpio.h
@@ -59,4 +59,23 @@
*/
int spl_gpio_input(void *regs, uint gpio);
+/**
+ * spl_gpio_get_value() - Get GPIO value
+ *
+ * @regs: Pointer to GPIO registers
+ * @gpio: GPIO to adjust (SoC-specific)
+ * Return: return GPIO value if OK, -ve on error
+ */
+int spl_gpio_get_value(void *regs, uint gpio);
+
+/**
+ * spl_gpio_set_value() - Set value on GPIO
+ *
+ * @regs: Pointer to GPIO registers
+ * @gpio: GPIO to adjust (SoC-specific)
+ * @value: 0 to set the output low, 1 to set it high
+ * Return: return 0 if OK, -ve on error
+ */
+int spl_gpio_set_value(void *regs, uint gpio, int value);
+
#endif /* __SPL_GPIO_H */
diff --git a/tools/binman/etype/nxp_imx8mcst.py b/tools/binman/etype/nxp_imx8mcst.py
index 8221517..a7d8db4 100644
--- a/tools/binman/etype/nxp_imx8mcst.py
+++ b/tools/binman/etype/nxp_imx8mcst.py
@@ -23,7 +23,9 @@
MAGIC_NXP_IMX_IVT = 0x412000d1
MAGIC_FITIMAGE = 0xedfe0dd0
-csf_config_template = """
+KEY_NAME = 'sha256_4096_65537_v3_usr_crt'
+
+CSF_CONFIG_TEMPLATE = f'''
[Header]
Version = 4.3
Hash Algorithm = sha256
@@ -36,8 +38,11 @@
File = "SRK_1_2_3_4_table.bin"
Source index = 0
+[Install NOCAK]
+ File = "SRK1_{KEY_NAME}.pem"
+
[Install CSFK]
- File = "CSF1_1_sha256_4096_65537_v3_usr_crt.pem"
+ File = "CSF1_1_{KEY_NAME}.pem"
[Authenticate CSF]
@@ -48,12 +53,12 @@
[Install Key]
Verification index = 0
Target Index = 2
- File = "IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
+ File = "IMG1_1_{KEY_NAME}.pem"
[Authenticate Data]
Verification index = 2
Blocks = 0x1234 0x78 0xabcd "data.bin"
-"""
+'''
class Entry_nxp_imx8mcst(Entry_mkimage):
"""NXP i.MX8M CST .cfg file generator and cst invoker
@@ -69,9 +74,22 @@
def ReadNode(self):
super().ReadNode()
self.loader_address = fdt_util.GetInt(self._node, 'nxp,loader-address')
- self.srk_table = os.getenv('SRK_TABLE', fdt_util.GetString(self._node, 'nxp,srk-table', 'SRK_1_2_3_4_table.bin'))
- self.csf_crt = os.getenv('CSF_KEY', fdt_util.GetString(self._node, 'nxp,csf-crt', 'CSF1_1_sha256_4096_65537_v3_usr_crt.pem'))
- self.img_crt = os.getenv('IMG_KEY', fdt_util.GetString(self._node, 'nxp,img-crt', 'IMG1_1_sha256_4096_65537_v3_usr_crt.pem'))
+ self.srk_table = os.getenv(
+ 'SRK_TABLE', fdt_util.GetString(self._node, 'nxp,srk-table',
+ 'SRK_1_2_3_4_table.bin'))
+ self.fast_auth = fdt_util.GetBool(self._node, 'nxp,fast-auth')
+ if not self.fast_auth:
+ self.csf_crt = os.getenv(
+ 'CSF_KEY', fdt_util.GetString(self._node, 'nxp,csf-crt',
+ f'CSF1_1_{KEY_NAME}.pem'))
+ self.img_crt = os.getenv(
+ 'IMG_KEY', fdt_util.GetString(self._node, 'nxp,img-crt',
+ f'IMG1_1_{KEY_NAME}.pem'))
+ else:
+ self.srk_crt = os.getenv(
+ 'SRK_KEY', fdt_util.GetString(self._node, 'nxp,srk-crt',
+ f'SRK1_{KEY_NAME}.pem'))
+
self.unlock = fdt_util.GetBool(self._node, 'nxp,unlock')
self.ReadEntries()
@@ -118,16 +136,26 @@
tools.write_file(output_dname, data)
# Generate CST configuration file used to sign payload
- cfg_fname = tools.get_output_filename('nxp.csf-config-txt.%s' % uniq)
+ cfg_fname = tools.get_output_filename(f'nxp.csf-config-txt.{uniq}')
config = configparser.ConfigParser()
# Do not make key names lowercase
config.optionxform = str
# Load configuration template and modify keys of interest
- config.read_string(csf_config_template)
- config['Install SRK']['File'] = '"' + self.srk_table + '"'
- config['Install CSFK']['File'] = '"' + self.csf_crt + '"'
- config['Install Key']['File'] = '"' + self.img_crt + '"'
- config['Authenticate Data']['Blocks'] = hex(signbase) + ' 0 ' + hex(len(data)) + ' "' + str(output_dname) + '"'
+ config.read_string(CSF_CONFIG_TEMPLATE)
+ config['Install SRK']['File'] = f'"{self.srk_table}"'
+ if not self.fast_auth:
+ config.remove_section('Install NOCAK')
+ config['Install CSFK']['File'] = f'"{self.csf_crt}"'
+ config['Install Key']['File'] = f'"{self.img_crt}"'
+ else:
+ config.remove_section('Install CSFK')
+ config.remove_section('Install Key')
+ config['Install NOCAK']['File'] = f'"{self.srk_crt}"'
+ config['Authenticate Data']['Verification index'] = '0'
+
+ config['Authenticate Data']['Blocks'] = \
+ f'{signbase:#x} 0 {len(data):#x} "{output_dname}"'
+
if not self.unlock:
config.remove_section('Unlock')
with open(cfg_fname, 'w') as cfgf: