diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index ff73596..ed89011 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -84,7 +84,7 @@
 static void check_erratum_a4580(uint32_t svr)
 {
 	const serdes_corenet_t __iomem *srds_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+		(void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
 	unsigned int lane;
 
 	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 432d4b1..49a1aac 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -98,7 +98,7 @@
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 	if (SVR_SOC_VER(svr) == SVR_T4080) {
 		ccsr_rcpm_t *rcpm =
-			(void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+			(void __iomem *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
 
 		setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
 			     FSL_CORENET_DEVDISR2_DTSEC1_9);
@@ -540,16 +540,16 @@
 	for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
 		switch (i) {
 		case 0:
-			ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+			ddr[i] = (void *)CFG_SYS_FSL_DDR_ADDR;
 			break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
 		case 1:
-			ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+			ddr[i] = (void *)CFG_SYS_FSL_DDR2_ADDR;
 			break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
 		case 2:
-			ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+			ddr[i] = (void *)CFG_SYS_FSL_DDR3_ADDR;
 			break;
 #endif
 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 9fb7802..47bea51 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -160,7 +160,7 @@
 {
 	int i;
 
-	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+	cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
 
 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
@@ -217,7 +217,7 @@
 	char cpc_subarg[16];
 	bool have_hwconfig = false;
 	int cpc_args = 0;
-	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+	cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
 
 	/* Extract hwconfig from environment */
 	ret = env_get_f("hwconfig", buffer, sizeof(buffer));
@@ -271,7 +271,7 @@
 static void invalidate_cpc(void)
 {
 	int i;
-	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+	cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
 
 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 		/* skip CPC when it used as all SRAM */
@@ -300,7 +300,7 @@
 static void corenet_tb_init(void)
 {
 	volatile ccsr_rcpm_t *rcpm =
-		(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+		(void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
 	volatile ccsr_pic_t *pic =
 		(void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 	u32 whoami = in_be32(&pic->whoami);
@@ -476,7 +476,7 @@
 	do {
 		int j, cluster_valid = 0;
 
-		l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+		l2cache = (void __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
 
 		cluster = in_be32(&gur->tp_cluster[i].lower);
 
@@ -518,7 +518,7 @@
 #ifdef CONFIG_L2_CACHE
 	ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
-	struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
+	struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2;
 #endif
 
 	puts ("L2:    ");
@@ -664,7 +664,7 @@
 	const char *spin;
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
-	ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
 #endif
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 811e6d6..1161938 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -164,7 +164,7 @@
 static inline void ft_fixup_l3cache(void *blob, int off)
 {
 	u32 line_size, num_ways, size, num_sets;
-	cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
+	cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR;
 	u32 cfg0 = in_be32(&cpc->cpccfg0);
 
 	size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
@@ -299,7 +299,7 @@
 	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 #else
 	struct ccsr_cluster_l2 *l2cache =
-		(struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
+		(struct ccsr_cluster_l2 __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2);
 	u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
 #endif
 	u32 size, line_size, num_ways, num_sets;
@@ -466,11 +466,11 @@
 
 	get_sys_info(&sysinfo);
 #ifdef CONFIG_SYS_DPAA_FMAN
-	ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
+	ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET,
 			sysinfo.freq_fman[0]);
 
 #if (CONFIG_SYS_NUM_FMAN == 2)
-	ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
+	ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET,
 			sysinfo.freq_fman[1]);
 #endif
 #endif
@@ -611,7 +611,7 @@
 	else {
 		ccsr_sec_t __iomem *sec;
 
-		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+		sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
 		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 	}
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 1a30395..3a6ce32 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -21,10 +21,10 @@
 #ifdef CONFIG_SYS_FSL_SRDS_2
 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
 static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 
@@ -104,13 +104,13 @@
 
 	ret |= serdes2_prtcl_map[device];
 #endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
 	if (!serdes3_prtcl_map[NONE])
 		fsl_serdes_init();
 
 	ret |= serdes3_prtcl_map[device];
 #endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
 	if (!serdes4_prtcl_map[NONE])
 		fsl_serdes_init();
 
@@ -139,13 +139,13 @@
 		cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 		break;
 #endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
 	case FSL_SRDS_3:
 		cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
 		cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
 		break;
 #endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
 	case FSL_SRDS_4:
 		cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
 		cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
@@ -351,28 +351,28 @@
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	serdes_init(FSL_SRDS_1,
-		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+		    CFG_SYS_FSL_CORENET_SERDES_ADDR,
 		    FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
 		    FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
 		    serdes1_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes_init(FSL_SRDS_2,
-		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+		    CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
 		    FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
 		    FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
 		    serdes2_prtcl_map);
 #endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
 	serdes_init(FSL_SRDS_3,
-		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+		    CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
 		    FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
 		    FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
 		    serdes3_prtcl_map);
 #endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
 	serdes_init(FSL_SRDS_4,
-		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+		    CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
 		    FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
 		    FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
 		    serdes4_prtcl_map);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 1d35733..437ecde 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -109,7 +109,7 @@
 int serdes_lane_enabled(int lane)
 {
 	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-	serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
 
 	int bank = lanes[lane].bank;
 	int word = lanes[lane].lpd / 32;
@@ -257,7 +257,7 @@
 	if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
 		return;
 
-	regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	regs = (typeof(regs))CFG_SYS_FSL_CORENET_SERDES_ADDR;
 	prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
 
 	__serdes_reset_rx(regs, prtcl, device);
@@ -466,7 +466,7 @@
 static void wait_for_rstdone(unsigned int bank)
 {
 	serdes_corenet_t *srds_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+		(void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
 	unsigned long long end_tick;
 	u32 rstctl;
 
@@ -527,7 +527,7 @@
 	if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
 		return;
 
-	srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+	srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
 	cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
 	debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
 
@@ -601,7 +601,7 @@
 		serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
 		break;
 	default:
-		srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+		srds2_regs = (void *)CFG_SYS_FSL_CORENET_SERDES2_ADDR;
 
 		/* We don't need bank 4, so power it down */
 		setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 34974c9..9ad48d4 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -76,7 +76,7 @@
 
 static void setup_sec_liodn_base(void)
 {
-	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
 	u32 base;
 
 	if (!IS_E_PROCESSOR(get_svr()))
@@ -101,12 +101,12 @@
 
 	switch(dev) {
 	case FSL_HW_PORTAL_FMAN1:
-		fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+		fm = (void *)CFG_SYS_FSL_FM1_ADDR;
 		break;
 
 #if (CONFIG_SYS_NUM_FMAN == 2)
 	case FSL_HW_PORTAL_FMAN2:
-		fm = (void *)CONFIG_SYS_FSL_FM2_ADDR;
+		fm = (void *)CFG_SYS_FSL_FM2_ADDR;
 		break;
 #endif
 	default:
@@ -130,7 +130,7 @@
 static void setup_pme_liodn_base(void)
 {
 #ifdef CONFIG_SYS_DPAA_PME
-	ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+	ccsr_pme_t *pme = (void *)CFG_SYS_FSL_CORENET_PME_ADDR;
 	u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) |
 			liodn_bases[FSL_HW_PORTAL_PME].id[1];
 
@@ -141,7 +141,7 @@
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 static void setup_raide_liodn_base(void)
 {
-	struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR;
+	struct ccsr_raide *raide = (void *)CFG_SYS_FSL_RAID_ENGINE_ADDR;
 
 	/* setup raid engine liodn base for data/desc ; both set to 47 */
 	u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) |
@@ -155,7 +155,7 @@
 static void set_rman_liodn(struct liodn_id_table *tbl, int size)
 {
 	int i;
-	struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
+	struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
 
 	for (i = 0; i < size; i++) {
 		/* write the RMan block number */
@@ -168,7 +168,7 @@
 static void setup_rman_liodn_base(struct liodn_id_table *tbl, int size)
 {
 	int i;
-	struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
+	struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
 	u32 base = liodn_bases[FSL_HW_PORTAL_RMAN].id[0];
 
 	out_be32(&rman->mmliodnbr, base);
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index e1469eb..f109ecb 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -265,8 +265,8 @@
 	struct law_entry e;
 
 	gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-	ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
-	rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+	ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR);
+	rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
 	pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 
 	whoami = in_be32(&pic->whoami);
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index a7004a6..31d0481 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -26,14 +26,14 @@
 {
 	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_FSL_CORENET
-	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+	volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR);
 	unsigned int cpu;
 #ifdef CONFIG_HETROGENOUS_CLUSTERS
 	unsigned int dsp_cpu;
 	uint rcw_tmp1, rcw_tmp2;
 #endif
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
-	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+	int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
 #endif
 	__maybe_unused u32 svr;
 
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 024414e..5341756 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -966,7 +966,7 @@
 	erratum_set_dcsr 0xb0e38 0xe0400000
 	erratum_set_dcsr 0xb0008 0x00900000
 	erratum_set_dcsr 0xb0e40 0xe00a0000
-	erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+	erratum_set_ccsr 0x18600 CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 #ifdef  CONFIG_RAMBOOT_PBL
 	erratum_set_ccsr 0x10f00 0x495e5000
 #else
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 4e3f900..dd27416 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -20,7 +20,7 @@
 #define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
 
 #ifdef CONFIG_FSL_CORENET
-#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
+#define LAW_BASE (CFG_SYS_FSL_CORENET_CCM_ADDR)
 #define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
 #define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
 #define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 62524a2..c815d19 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -79,9 +79,9 @@
 	int idx, first, last;
 	u32 i;
 	unsigned long long end_tick;
-	struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+	struct ccsr_rio *srio_regs = (void *)CFG_SYS_FSL_SRIO_ADDR;
 
-	srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+	srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
 	conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
 			>> (12 - port * 4)) & 0x3;
 	init_lane = (in_be32((void *)&srio_regs->lp_serial
@@ -291,7 +291,7 @@
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 void srio_boot_master(int port)
 {
-	struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+	struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
 
 	/* set port accept-all */
 	out_be32((void *)&srio->impl.port[port - 1].ptaacr,
@@ -343,7 +343,7 @@
 
 void srio_boot_master_release_slave(int port)
 {
-	struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+	struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
 	u32 escsr;
 	debug("SRIOBOOT - MASTER: "
 			"Check the port status and release slave core ...\n");
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d3d4e9c..25d1b48 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -17,10 +17,10 @@
 #include <fsl_ddrc_version.h>
 
 #if defined(CONFIG_ARCH_MPC8548)
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+#define CFG_SYS_FSL_SRIO_MAX_PORTS	1
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_ARCH_P1010)
 #define CONFIG_FSL_SDHC_V2_3
@@ -59,30 +59,30 @@
 #define QE_NUM_OF_SNUM			28
 
 #elif defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+#define CFG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P3041)
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
 #define CONFIG_SYS_NUM_FMAN		2
@@ -91,11 +91,11 @@
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 
 #elif defined(CONFIG_ARCH_P5040)
 #define CONFIG_SYS_NUM_FMAN		2
@@ -104,7 +104,7 @@
 #define CONFIG_SYS_NUM_FM2_DTSEC	5
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_BSC9131)
 #define CONFIG_FSL_SDHC_V2_3
@@ -118,7 +118,7 @@
 
 #elif defined(CONFIG_ARCH_T4240)
 #ifdef CONFIG_ARCH_T4240
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	8
 #define CONFIG_SYS_NUM_FM1_10GEC	2
 #define CONFIG_SYS_NUM_FM2_DTSEC	8
@@ -131,17 +131,17 @@
 #endif
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_FSL_SRDS_3
-#define CONFIG_SYS_FSL_SRDS_4
+#define CFG_SYS_FSL_SRDS_3
+#define CFG_SYS_FSL_SRDS_4
 #define CONFIG_SYS_NUM_FMAN		2
 #define CONFIG_SYS_PME_CLK		0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FM1_CLK		3
 #define CONFIG_SYS_FM2_CLK		3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
 #define CONFIG_SYS_FSL_SRDS_1
@@ -154,21 +154,21 @@
 #ifdef CONFIG_ARCH_B4860
 #define CONFIG_MAX_DSP_CPUS		12
 #define CONFIG_NUM_DSP_CPUS		6
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	6
 #define CONFIG_SYS_NUM_FM1_10GEC	2
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #else
 #define CONFIG_MAX_DSP_CPUS		2
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	4
 #define CONFIG_SYS_NUM_FM1_10GEC	0
 #endif
 
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
@@ -184,8 +184,7 @@
 #define QE_NUM_OF_SNUM			28
 
 #elif defined(CONFIG_ARCH_T1024)
-#define CONFIG_SYS_FSL_NUM_CC_PLL	2
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	4
@@ -202,15 +201,15 @@
 
 #elif defined(CONFIG_ARCH_T2080)
 #define CONFIG_SYS_NUM_FMAN		1
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 #define CONFIG_SYS_FSL_SRDS_1
 #if defined(CONFIG_ARCH_T2080)
 #define CONFIG_SYS_NUM_FM1_DTSEC	8
 #define CONFIG_SYS_NUM_FM1_10GEC	4
 #define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #endif
 #define CONFIG_PME_PLAT_CLK_DIV		1
 #define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
@@ -224,7 +223,7 @@
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_TSECV2_1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
-#define CONFIG_SYS_FSL_SEC_IDX_OFFSET	0x20000
+#define CFG_SYS_FSL_SEC_IDX_OFFSET	0x20000
 
 #endif
 
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index be55f99..de85bcf 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -33,7 +33,7 @@
 	{ .id = { id_a }, .num_ids = 1, .portid = port, \
 	  .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
 		+ (port - 1) * 0x200 \
-		+ CONFIG_SYS_FSL_SRIO_ADDR, \
+		+ CFG_SYS_FSL_SRIO_ADDR, \
 	}
 
 struct liodn_id_table {
@@ -130,29 +130,29 @@
 #define SET_QMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,qman", liodn, \
 		offsetof(struct ccsr_qman, liodnr) + \
-		CONFIG_SYS_FSL_QMAN_OFFSET, \
-		CONFIG_SYS_FSL_QMAN_OFFSET)
+		CFG_SYS_FSL_QMAN_OFFSET, \
+		CFG_SYS_FSL_QMAN_OFFSET)
 
 #define SET_BMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,bman", liodn, \
 		offsetof(struct ccsr_bman, liodnr) + \
-		CONFIG_SYS_FSL_BMAN_OFFSET, \
-		CONFIG_SYS_FSL_BMAN_OFFSET)
+		CFG_SYS_FSL_BMAN_OFFSET, \
+		CFG_SYS_FSL_BMAN_OFFSET)
 
 #define SET_PME_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
-		CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
-		CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+		CFG_SYS_FSL_CORENET_PME_OFFSET, \
+		CFG_SYS_FSL_CORENET_PME_OFFSET)
 
 #define SET_PMAN_LIODN(num, liodn) \
 	SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
 		offsetof(struct ccsr_pman, ppa1) + \
-		CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
-		CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
+		CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
+		CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
 
 /* -1 from portID due to how immap has the registers */
 #define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
-	CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
+	CFG_SYS_FSL_FM##fmNum##_OFFSET + \
 	offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
 
 #ifdef CONFIG_SYS_FMAN_V3
@@ -160,31 +160,31 @@
 #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
 	SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
 		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
-		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+		CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
 
 /* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
 #define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
 	SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
 		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
-		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+		CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
 
 /* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
 #define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
 	SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
 		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
-		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+		CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
 #else
 /* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
 #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
 	SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \
 		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
-		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+		CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
 
 /* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
 #define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
 	SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \
 		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
-		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+		CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
 #endif
 /*
  * handle both old and new versioned SEC properties:
@@ -193,44 +193,44 @@
 #define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
 	SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
 		offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
+		CFG_SYS_FSL_SEC_OFFSET, \
+		CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
 	SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
 		offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
+		CFG_SYS_FSL_SEC_OFFSET, \
+		CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
 
 /* This is a bit evil since we treat rtic param as both a string & hex value */
 #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
 	SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
 		liodnA,	\
 		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+		CFG_SYS_FSL_SEC_OFFSET, \
+		CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
 	SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
 		liodnA,	\
 		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+		CFG_SYS_FSL_SEC_OFFSET, \
+		CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
 
 #define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
 	SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
 		offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, 0)
+		CFG_SYS_FSL_SEC_OFFSET, 0)
 
 #define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
 	SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
 	liodnA, \
 	offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
-	CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \
+	CFG_SYS_FSL_RAID_ENGINE_OFFSET, \
 	offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
-	CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
+	CFG_SYS_FSL_RAID_ENGINE_OFFSET)
 
 #define SET_RMAN_LIODN(ibNum, liodn) \
 	SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
 		offsetof(struct ccsr_rman, mmitdr) + \
-		CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \
-		CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
+		CFG_SYS_FSL_CORENET_RMAN_OFFSET, \
+		CFG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
 
 extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
 extern struct liodn_id_table raide_liodn_tbl[];
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 0bf5b9c..8e18202 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -862,7 +862,7 @@
 };
 
 #define CFG_SYS_MPC8xxx_DDR_OFFSET	(0x2000)
-#define CONFIG_SYS_FSL_DDR_ADDR \
+#define CFG_SYS_FSL_DDR_ADDR \
 			(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
 #define CFG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
 #define CFG_SYS_MPC83xx_DMA_ADDR \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7a7a7f2..c9ced54 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -963,7 +963,7 @@
 	u32	prtoccsr;	/* Port Response Time-out CCSR */
 	u8	res1[20];
 	u32	pgccsr;	/* Port General CSR */
-	struct rio_lp_serial_port	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+	struct rio_lp_serial_port	port[CFG_SYS_FSL_SRIO_MAX_PORTS];
 };
 
 /* Logical error reporting registers */
@@ -993,7 +993,7 @@
 
 /* Physical error reporting registers */
 struct rio_phys_err {
-	struct rio_phys_err_port	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+	struct rio_phys_err_port	port[CFG_SYS_FSL_SRIO_MAX_PORTS];
 };
 
 /* Implementation Space: General Port-Common */
@@ -1033,7 +1033,7 @@
 /* Implementation Space: register */
 struct rio_implement {
 	struct rio_impl_common	com;
-	struct rio_impl_port_spec	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+	struct rio_impl_port_spec	port[CFG_SYS_FSL_SRIO_MAX_PORTS];
 };
 
 /* Revision Control Register */
@@ -1061,13 +1061,13 @@
 
 /* ATMU window registers */
 struct rio_atmu_win {
-	struct rio_atmu_row	outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
+	struct rio_atmu_row	outbw[CFG_SYS_FSL_SRIO_OB_WIN_NUM];
 	u8	res0[64];
-	struct rio_atmu_riw	inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
+	struct rio_atmu_riw	inbw[CFG_SYS_FSL_SRIO_IB_WIN_NUM];
 };
 
 struct rio_atmu {
-	struct rio_atmu_win	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+	struct rio_atmu_win	port[CFG_SYS_FSL_SRIO_MAX_PORTS];
 };
 
 #ifdef CONFIG_SYS_FSL_RMU
@@ -1154,7 +1154,7 @@
 	struct rio_atmu	atmu;
 #ifdef CONFIG_SYS_FSL_RMU
 	u8	res5[8192];
-	struct rio_msg	msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
+	struct rio_msg	msg[CFG_SYS_FSL_SRIO_MSG_UNIT_NUM];
 	u8	res6[512];
 	struct rio_dbell	dbell;
 	u8	res7[100];
@@ -1162,7 +1162,7 @@
 #endif
 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
 	u8	res5[8192];
-	struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+	struct rio_liodn liodn[CFG_SYS_FSL_SRIO_MAX_PORTS];
 #endif
 };
 #endif
@@ -2431,17 +2431,17 @@
 #endif
 
 #ifdef CONFIG_FSL_CORENET
-#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
+#define CFG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
 #ifdef CONFIG_SYS_PMAN
-#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET	0x4000
-#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET	0x5000
-#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET	0x6000
+#define CFG_SYS_FSL_CORENET_PMAN1_OFFSET	0x4000
+#define CFG_SYS_FSL_CORENET_PMAN2_OFFSET	0x5000
+#define CFG_SYS_FSL_CORENET_PMAN3_OFFSET	0x6000
 #endif
 #define CFG_SYS_MPC8xxx_DDR_OFFSET		0x8000
 #define CFG_SYS_MPC8xxx_DDR2_OFFSET		0x9000
 #define CFG_SYS_MPC8xxx_DDR3_OFFSET		0xA000
-#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
-#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
+#define CFG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
+#define CFG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0
 /* In SFPv3, OSPR register is now at offset 0x200.
  *  * So directly mapping sfp register map to this address */
@@ -2450,13 +2450,13 @@
 #else
 #define CONFIG_SYS_SFP_OFFSET                   0xE8000
 #endif
-#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
-#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
-#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET	0xEC000
-#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET	0xED000
-#define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
-#define CONFIG_SYS_FSL_SCFG_OFFSET		0xFC000
-#define CONFIG_SYS_FSL_PAMU_OFFSET		0x20000
+#define CFG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
+#define CFG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
+#define CFG_SYS_FSL_CORENET_SERDES3_OFFSET	0xEC000
+#define CFG_SYS_FSL_CORENET_SERDES4_OFFSET	0xED000
+#define CFG_SYS_FSL_CPC_OFFSET		0x10000
+#define CFG_SYS_FSL_SCFG_OFFSET		0xFC000
+#define CFG_SYS_FSL_PAMU_OFFSET		0x20000
 #define CFG_SYS_MPC85xx_DMA1_OFFSET		0x100000
 #define CFG_SYS_MPC85xx_DMA2_OFFSET		0x101000
 #define CFG_SYS_MPC85xx_DMA3_OFFSET		0x102000
@@ -2468,7 +2468,7 @@
 #define CFG_SYS_MPC85xx_GPIO_OFFSET		0x130000
 #define CFG_SYS_MPC85xx_TDM_OFFSET		0x185000
 #define CFG_SYS_MPC85xx_QE_OFFSET		0x140000
-#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
+#define CFG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
 	!defined(CONFIG_ARCH_B4420)
 #define CFG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
@@ -2487,33 +2487,33 @@
 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
 #define CFG_SYS_MPC85xx_SATA1_OFFSET		0x220000
 #define CFG_SYS_MPC85xx_SATA2_OFFSET		0x221000
-#define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
-#define CONFIG_SYS_FSL_JR0_OFFSET		0x301000
+#define CFG_SYS_FSL_SEC_OFFSET		0x300000
+#define CFG_SYS_FSL_JR0_OFFSET		0x301000
 #define CONFIG_SYS_SEC_MON_OFFSET		0x314000
-#define CONFIG_SYS_FSL_CORENET_PME_OFFSET	0x316000
-#define CONFIG_SYS_FSL_QMAN_OFFSET		0x318000
-#define CONFIG_SYS_FSL_BMAN_OFFSET		0x31a000
-#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET	0x320000
-#define CONFIG_SYS_FSL_FM1_OFFSET		0x400000
-#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x488000
-#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x489000
-#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0x48a000
-#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0x48b000
-#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0x48c000
-#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET	0x48d000
-#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET	0x490000
-#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET	0x491000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x4e0000
-#define CONFIG_SYS_FSL_FM2_OFFSET		0x500000
-#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET	0x588000
-#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET	0x589000
-#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET	0x58a000
-#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET	0x58b000
-#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET	0x58c000
-#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET	0x58d000
-#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET	0x590000
-#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET	0x591000
-#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET	0xC20000
+#define CFG_SYS_FSL_CORENET_PME_OFFSET	0x316000
+#define CFG_SYS_FSL_QMAN_OFFSET		0x318000
+#define CFG_SYS_FSL_BMAN_OFFSET		0x31a000
+#define CFG_SYS_FSL_RAID_ENGINE_OFFSET	0x320000
+#define CFG_SYS_FSL_FM1_OFFSET		0x400000
+#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET	0x488000
+#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET	0x489000
+#define CFG_SYS_FSL_FM1_RX2_1G_OFFSET	0x48a000
+#define CFG_SYS_FSL_FM1_RX3_1G_OFFSET	0x48b000
+#define CFG_SYS_FSL_FM1_RX4_1G_OFFSET	0x48c000
+#define CFG_SYS_FSL_FM1_RX5_1G_OFFSET	0x48d000
+#define CFG_SYS_FSL_FM1_RX0_10G_OFFSET	0x490000
+#define CFG_SYS_FSL_FM1_RX1_10G_OFFSET	0x491000
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET	0x4e0000
+#define CFG_SYS_FSL_FM2_OFFSET		0x500000
+#define CFG_SYS_FSL_FM2_RX0_1G_OFFSET	0x588000
+#define CFG_SYS_FSL_FM2_RX1_1G_OFFSET	0x589000
+#define CFG_SYS_FSL_FM2_RX2_1G_OFFSET	0x58a000
+#define CFG_SYS_FSL_FM2_RX3_1G_OFFSET	0x58b000
+#define CFG_SYS_FSL_FM2_RX4_1G_OFFSET	0x58c000
+#define CFG_SYS_FSL_FM2_RX5_1G_OFFSET	0x58d000
+#define CFG_SYS_FSL_FM2_RX0_10G_OFFSET	0x590000
+#define CFG_SYS_FSL_FM2_RX1_10G_OFFSET	0x591000
+#define CFG_SYS_FSL_CLUSTER_1_L2_OFFSET	0xC20000
 #else
 #define CFG_SYS_MPC85xx_ECM_OFFSET		0x0000
 #define CFG_SYS_MPC8xxx_DDR_OFFSET		0x2000
@@ -2551,57 +2551,57 @@
 #define CONFIG_SYS_MDIO1_OFFSET			0x24000
 #define CFG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
 #if defined(CONFIG_ARCH_C29X)
-#define CONFIG_SYS_FSL_SEC_OFFSET		0x80000
-#define CONFIG_SYS_FSL_JR0_OFFSET               0x81000
+#define CFG_SYS_FSL_SEC_OFFSET		0x80000
+#define CFG_SYS_FSL_JR0_OFFSET               0x81000
 #else
-#define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
-#define CONFIG_SYS_FSL_JR0_OFFSET               0x31000
+#define CFG_SYS_FSL_SEC_OFFSET		0x30000
+#define CFG_SYS_FSL_JR0_OFFSET               0x31000
 #endif
 #define CFG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CFG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_SEC_MON_OFFSET		0xE6000
 #define CONFIG_SYS_SFP_OFFSET			0xE7000
-#define CONFIG_SYS_FSL_QMAN_OFFSET		0x88000
-#define CONFIG_SYS_FSL_BMAN_OFFSET		0x8a000
-#define CONFIG_SYS_FSL_FM1_OFFSET		0x100000
-#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x188000
-#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x189000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x1e0000
+#define CFG_SYS_FSL_QMAN_OFFSET		0x88000
+#define CFG_SYS_FSL_BMAN_OFFSET		0x8a000
+#define CFG_SYS_FSL_FM1_OFFSET		0x100000
+#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET	0x188000
+#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET	0x189000
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET	0x1e0000
 #endif
 
 #define CFG_SYS_MPC85xx_PIC_OFFSET		0x40000
 #define CFG_SYS_MPC85xx_GUTS_OFFSET		0xE0000
-#define CONFIG_SYS_FSL_SRIO_OFFSET		0xC0000
+#define CFG_SYS_FSL_SRIO_OFFSET		0xC0000
 
-#define CONFIG_SYS_FSL_CPC_ADDR	\
-	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
-#define CONFIG_SYS_FSL_SCFG_ADDR	\
-	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
-#define CONFIG_SYS_FSL_QMAN_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
-#define CONFIG_SYS_FSL_BMAN_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
-#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
+#define CFG_SYS_FSL_CPC_ADDR	\
+	(CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
+#define CFG_SYS_FSL_SCFG_ADDR	\
+	(CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
+#define CFG_SYS_FSL_QMAN_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET)
+#define CFG_SYS_FSL_BMAN_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_BMAN_OFFSET)
+#define CFG_SYS_FSL_CORENET_PME_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_PME_OFFSET)
+#define CFG_SYS_FSL_RAID_ENGINE_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_RAID_ENGINE_OFFSET)
+#define CFG_SYS_FSL_CORENET_RMAN_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RMAN_OFFSET)
 #define CFG_SYS_MPC85xx_GUTS_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
+#define CFG_SYS_FSL_CORENET_CCM_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CCM_OFFSET)
+#define CFG_SYS_FSL_CORENET_CLK_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CLK_OFFSET)
+#define CFG_SYS_FSL_CORENET_RCPM_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RCPM_OFFSET)
 #define CFG_SYS_MPC85xx_ECM_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET)
-#define CONFIG_SYS_FSL_DDR_ADDR \
+#define CFG_SYS_FSL_DDR_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_FSL_DDR2_ADDR \
+#define CFG_SYS_FSL_DDR2_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
-#define CONFIG_SYS_FSL_DDR3_ADDR \
+#define CFG_SYS_FSL_DDR3_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
 #define CONFIG_SYS_LBC_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
@@ -2631,14 +2631,14 @@
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET)
 #define CFG_SYS_MPC85xx_SERDES2_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES2_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES3_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES3_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES4_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES4_OFFSET)
 #define CFG_SYS_MPC85xx_USB1_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET)
 #define CFG_SYS_MPC85xx_USB2_ADDR \
@@ -2647,20 +2647,20 @@
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET)
 #define CFG_SYS_MPC85xx_USB2_PHY_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET)
-#define CONFIG_SYS_FSL_SEC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_FM1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
-#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
-#define CONFIG_SYS_FSL_FM2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
-#define CONFIG_SYS_FSL_SRIO_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_FM1_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CFG_SYS_FSL_FM2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET)
+#define CFG_SYS_FSL_SRIO_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET)
 #define CONFIG_SYS_PAMU_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
 
 #define CONFIG_SYS_PCI1_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET)
@@ -2739,8 +2739,8 @@
 	u32 l2erraddr;	/* 0xe54 L2 cache error address */
 	u32 l2errctl;	/* 0xe58 L2 cache error control */
 };
-#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
+#define CFG_SYS_FSL_CLUSTER_1_L2 \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET)
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
 #define	CONFIG_SYS_DCSR_DCFG_OFFSET	0X20000