tree 8c9506f950d5f409413970d08f7b697e65c961fe
parent ec1576804b7a746d2572fc9ec63e11b06dc6e3c9
author Peng Fan <peng.fan@nxp.com> 1462346870 +0800
committer Tom Rini <trini@konsulko.com> 1462545819 -0400

imx6: cache: disable L2 before touching Auxiliary Control Register

According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"

So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>