mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modes
According to the AM654x Data Manual[1], the setup timing in lower speed
modes can only be met if the controller uses a falling edge data launch.
To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be
cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25
speed modes.
Use the sdhci writeb callback to implement this condition.
[1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 14d7913..f8ea921 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -526,6 +526,7 @@
depends on MMC_SDHCI
depends on DM_MMC && OF_CONTROL && BLK
depends on REGMAP
+ select MMC_SDHCI_IO_ACCESSORS
help
Support for Secure Digital Host Controller Interface (SDHCI)
controllers present on TI's AM654 SOCs.