diff --git a/board/kontron/sl28/Kconfig b/board/kontron/sl28/Kconfig
new file mode 100644
index 0000000..cdec39b
--- /dev/null
+++ b/board/kontron/sl28/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SL28
+
+config SYS_BOARD
+	default "sl28"
+
+config SYS_VENDOR
+	default "kontron"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "kontron_sl28"
+
+config SYS_TEXT_BASE
+	default 0x96000000
+
+endif
diff --git a/board/kontron/sl28/MAINTAINERS b/board/kontron/sl28/MAINTAINERS
new file mode 100644
index 0000000..a7b0fbb
--- /dev/null
+++ b/board/kontron/sl28/MAINTAINERS
@@ -0,0 +1,7 @@
+Kontron SMARC-sAL28 board
+M:	Michael Walle <michael@walle.cc>
+S:	Maintained
+F:	arch/arm/dts/fsl-ls1028a-kontron-sl28-*
+F:	board/kontron/sl28/
+F:	configs/kontron_sl28_defconfig
+F:	include/configs/kontron_sl28.h
diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile
new file mode 100644
index 0000000..0f1866c
--- /dev/null
+++ b/board/kontron/sl28/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+ifndef CONFIG_SPL_BUILD
+obj-y += sl28.o
+endif
+
+obj-y += common.o ddr.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c
new file mode 100644
index 0000000..14704f7
--- /dev/null
+++ b/board/kontron/sl28/common.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+
+int board_early_init_f(void)
+{
+	fsl_lsch3_early_init_f();
+	return 0;
+}
diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c
new file mode 100644
index 0000000..d111b6d
--- /dev/null
+++ b/board/kontron/sl28/ddr.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DCFG_GPPORCR1 0x20
+
+#define GPPORCR1_MEM_MASK		(0x7 << 5)
+#define GPPORCR1_MEM_512MB_CS0		(0x0 << 5)
+#define GPPORCR1_MEM_1GB_CS0		(0x1 << 5)
+#define GPPORCR1_MEM_2GB_CS0		(0x2 << 5)
+#define GPPORCR1_MEM_4GB_CS0_1		(0x3 << 5)
+#define GPPORCR1_MEM_4GB_CS0_2		(0x4 << 5)
+#define GPPORCR1_MEM_8GB_CS0_1_2_3	(0x5 << 5)
+#define GPPORCR1_MEM_8GB_CS0_1		(0x6 << 5)
+
+static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
+	.cs[0].bnds		= 0x0000007f,
+	.cs[0].config		= 0x80044402,
+	.cs[1].bnds		= 0x008000ff,
+	.cs[1].config		= 0x80004402,
+
+	.timing_cfg_0		= 0x9011010c,
+	.timing_cfg_3		= 0x010c1000,
+	.timing_cfg_1		= 0xbcb48c66,
+	.timing_cfg_2		= 0x0fc0d118,
+	.ddr_sdram_cfg		= 0xe70c000c,
+	.ddr_sdram_cfg_2	= 0x24401111,
+	.ddr_sdram_mode		= 0x00441c70,
+	.ddr_sdram_mode_3	= 0x00001c70,
+	.ddr_sdram_mode_5	= 0x00001c70,
+	.ddr_sdram_mode_7	= 0x00001c70,
+	.ddr_sdram_mode_2	= 0x00180000,
+	.ddr_sdram_mode_4	= 0x00180000,
+	.ddr_sdram_mode_6	= 0x00180000,
+	.ddr_sdram_mode_8	= 0x00180000,
+
+	.ddr_sdram_interval	= 0x0c30030c,
+	.ddr_data_init		= 0xdeadbeef,
+
+	.ddr_sdram_clk_cntl	= 0x02400000,
+
+	.timing_cfg_4		= 0x00000001,
+	.timing_cfg_5		= 0x04401400,
+
+	.ddr_zq_cntl		= 0x89080600,
+	.ddr_wrlvl_cntl		= 0x8675f606,
+	.ddr_wrlvl_cntl_2	= 0x04080700,
+	.ddr_wrlvl_cntl_3	= 0x00000009,
+
+	.ddr_cdr1		= 0x80040000,
+	.ddr_cdr2		= 0x0000bc01,
+};
+
+int fsl_initdram(void)
+{
+	u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1);
+	phys_size_t dram_size;
+
+	switch (gpporcr1 & GPPORCR1_MEM_MASK) {
+	case GPPORCR1_MEM_2GB_CS0:
+		dram_size = 0x80000000;
+		ddr_cfg_regs.cs[1].bnds = 0;
+		ddr_cfg_regs.cs[1].config = 0;
+		ddr_cfg_regs.cs[1].config_2 = 0;
+		break;
+	case GPPORCR1_MEM_4GB_CS0_1:
+		dram_size = 0x100000000ULL;
+		break;
+	case GPPORCR1_MEM_512MB_CS0:
+		dram_size = 0x20000000;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_1GB_CS0:
+		dram_size = 0x40000000;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_4GB_CS0_2:
+		dram_size = 0x100000000ULL;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_8GB_CS0_1:
+	case GPPORCR1_MEM_8GB_CS0_1_2_3:
+		dram_size = 0x200000000ULL;
+		fallthrough; /* for now */
+	default:
+		panic("Unsupported memory configuration (%08x)\n",
+		      gpporcr1 & GPPORCR1_MEM_MASK);
+		break;
+	}
+
+	if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD))
+		fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
new file mode 100644
index 0000000..b18127c
--- /dev/null
+++ b/board/kontron/sl28/sl28.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fsl_ddr.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <env_internal.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <i2c.h>
+#include <asm/arch/soc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+
+#include <fdtdec.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	if (CONFIG_IS_ENABLED(FSL_CAAM))
+		sec_init();
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int checkboard(void)
+{
+	printf("EL:    %d\n", current_el());
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+	int nbanks = CONFIG_NR_DRAM_BANKS;
+	int i;
+
+	ft_cpu_setup(blob, bd);
+
+	/* fixup DT for the two GPP DDR banks */
+	for (i = 0; i < nbanks; i++) {
+		base[i] = gd->bd->bi_dram[i].start;
+		size[i] = gd->bd->bi_dram[i].size;
+	}
+
+	fdt_fixup_memory_banks(blob, base, size, nbanks);
+
+	fdt_fixup_icid(blob);
+
+	return 0;
+}
diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c
new file mode 100644
index 0000000..fa5829e
--- /dev/null
+++ b/board/kontron/sl28/spl.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/spl.h>
+
+#define DCFG_RCWSR25 0x160
+#define GPINFO_HW_VARIANT_MASK 0xff
+
+int sl28_variant(void)
+{
+	return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	int variant = sl28_variant();
+
+	switch (variant) {
+	case 3:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var3");
+	case 4:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var4");
+	default:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28");
+	}
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+}