clk: imx: Pass struct udevice into imx_clk_composite*()
Pass struct udevice * into imx_clk_composite*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut <marex@denx.de>
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index a8ccc97..18621fc 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -297,57 +297,57 @@
base + 0x8000, 0, 3));
clk_dm(IMX8MN_CLK_AHB,
- imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
+ imx8m_clk_composite_critical(dev, "ahb", imx8mn_ahb_sels,
base + 0x9000));
clk_dm(IMX8MN_CLK_IPG_ROOT,
imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
clk_dm(IMX8MN_CLK_ENET_AXI,
- imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
+ imx8m_clk_composite(dev, "enet_axi", imx8mn_enet_axi_sels,
base + 0x8880));
clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
- imx8m_clk_composite_critical("nand_usdhc_bus",
+ imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
imx8mn_nand_usdhc_sels,
base + 0x8900));
clk_dm(IMX8MN_CLK_USB_BUS,
- imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
+ imx8m_clk_composite(dev, "usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
/* IP */
clk_dm(IMX8MN_CLK_USDHC1,
- imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
+ imx8m_clk_composite(dev, "usdhc1", imx8mn_usdhc1_sels,
base + 0xac00));
clk_dm(IMX8MN_CLK_USDHC2,
- imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
+ imx8m_clk_composite(dev, "usdhc2", imx8mn_usdhc2_sels,
base + 0xac80));
clk_dm(IMX8MN_CLK_I2C1,
- imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
+ imx8m_clk_composite(dev, "i2c1", imx8mn_i2c1_sels, base + 0xad00));
clk_dm(IMX8MN_CLK_I2C2,
- imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
+ imx8m_clk_composite(dev, "i2c2", imx8mn_i2c2_sels, base + 0xad80));
clk_dm(IMX8MN_CLK_I2C3,
- imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
+ imx8m_clk_composite(dev, "i2c3", imx8mn_i2c3_sels, base + 0xae00));
clk_dm(IMX8MN_CLK_I2C4,
- imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
+ imx8m_clk_composite(dev, "i2c4", imx8mn_i2c4_sels, base + 0xae80));
clk_dm(IMX8MN_CLK_UART1,
- imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00));
+ imx8m_clk_composite(dev, "uart1", imx8mn_uart1_sels, base + 0xaf00));
clk_dm(IMX8MN_CLK_UART2,
- imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80));
+ imx8m_clk_composite(dev, "uart2", imx8mn_uart2_sels, base + 0xaf80));
clk_dm(IMX8MN_CLK_UART3,
- imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000));
+ imx8m_clk_composite(dev, "uart3", imx8mn_uart3_sels, base + 0xb000));
clk_dm(IMX8MN_CLK_UART4,
- imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080));
+ imx8m_clk_composite(dev, "uart4", imx8mn_uart4_sels, base + 0xb080));
clk_dm(IMX8MN_CLK_WDOG,
- imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
+ imx8m_clk_composite(dev, "wdog", imx8mn_wdog_sels, base + 0xb900));
clk_dm(IMX8MN_CLK_USDHC3,
- imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
+ imx8m_clk_composite(dev, "usdhc3", imx8mn_usdhc3_sels,
base + 0xbc80));
clk_dm(IMX8MN_CLK_NAND,
- imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00));
+ imx8m_clk_composite(dev, "nand", imx8mn_nand_sels, base + 0xab00));
clk_dm(IMX8MN_CLK_QSPI,
- imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
+ imx8m_clk_composite(dev, "qspi", imx8mn_qspi_sels, base + 0xab80));
clk_dm(IMX8MN_CLK_USB_CORE_REF,
- imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
+ imx8m_clk_composite(dev, "usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
clk_dm(IMX8MN_CLK_USB_PHY_REF,
- imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
+ imx8m_clk_composite(dev, "usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
clk_dm(IMX8MN_CLK_I2C1_ROOT,
imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
@@ -393,25 +393,25 @@
/* clks not needed in SPL stage */
#ifndef CONFIG_XPL_BUILD
clk_dm(IMX8MN_CLK_ENET_REF,
- imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
+ imx8m_clk_composite(dev, "enet_ref", imx8mn_enet_ref_sels,
base + 0xa980));
clk_dm(IMX8MN_CLK_ENET_TIMER,
- imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
+ imx8m_clk_composite(dev, "enet_timer", imx8mn_enet_timer_sels,
base + 0xaa00));
clk_dm(IMX8MN_CLK_ENET_PHY_REF,
- imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
+ imx8m_clk_composite(dev, "enet_phy", imx8mn_enet_phy_sels,
base + 0xaa80));
clk_dm(IMX8MN_CLK_ENET1_ROOT,
imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
base + 0x40a0, 0));
clk_dm(IMX8MN_CLK_PWM1,
- imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380));
+ imx8m_clk_composite(dev, "pwm1", imx8mn_pwm1_sels, base + 0xb380));
clk_dm(IMX8MN_CLK_PWM2,
- imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400));
+ imx8m_clk_composite(dev, "pwm2", imx8mn_pwm2_sels, base + 0xb400));
clk_dm(IMX8MN_CLK_PWM3,
- imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480));
+ imx8m_clk_composite(dev, "pwm3", imx8mn_pwm3_sels, base + 0xb480));
clk_dm(IMX8MN_CLK_PWM4,
- imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500));
+ imx8m_clk_composite(dev, "pwm4", imx8mn_pwm4_sels, base + 0xb500));
clk_dm(IMX8MN_CLK_PWM1_ROOT,
imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
clk_dm(IMX8MN_CLK_PWM2_ROOT,
@@ -424,11 +424,11 @@
#if CONFIG_IS_ENABLED(DM_SPI)
clk_dm(IMX8MN_CLK_ECSPI1,
- imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
+ imx8m_clk_composite(dev, "ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MN_CLK_ECSPI2,
- imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
+ imx8m_clk_composite(dev, "ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
clk_dm(IMX8MN_CLK_ECSPI3,
- imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
+ imx8m_clk_composite(dev, "ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
clk_dm(IMX8MN_CLK_ECSPI2_ROOT,