commit 3665d6bfbf2ecf1a6009476e3e1dcd17713afe08
author Neil Armstrong <narmstrong@baylibre.com> Wed May 05 09:52:08 2021 +0200
committer Neil Armstrong <narmstrong@baylibre.com> Fri May 14 17:43:09 2021 +0200
tree af08aaa9f6833f9f6887a15bf2dee18aef729ef1
parent f2a1bed0103a9efd216d7e2ef3c54f58a61a5022

net: dwmac_meson8b: do not set TX delay in TXID & RXID

When the PHY interface is set as TXID & RXID, the delays should be taken from DT,
but first they should not be hardcoded since the PHY driver will set them.

Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

drivers/net/dwmac_meson8b.c

diff --git a/drivers/net/dwmac_meson8b.c b/drivers/net/dwmac_meson8b.c
index c0b6ef4..40cd837 100644
--- a/drivers/net/dwmac_meson8b.c
+++ b/drivers/net/dwmac_meson8b.c
@@ -59,8 +59,6 @@
 	switch (edata->phy_interface) {
 	case PHY_INTERFACE_MODE_RGMII:
 	case PHY_INTERFACE_MODE_RGMII_ID:
-	case PHY_INTERFACE_MODE_RGMII_RXID:
-	case PHY_INTERFACE_MODE_RGMII_TXID:
 		/* Set RGMII mode */
 		setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
 						     AXG_ETH_REG_0_TX_PHASE(1) |
@@ -69,6 +67,15 @@
 						     AXG_ETH_REG_0_CLK_EN);
 		break;
 
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		/* TOFIX: handle amlogic,tx-delay-ns & rx-internal-delay-ps from DT */
+		setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
+						     AXG_ETH_REG_0_TX_RATIO(4) |
+						     AXG_ETH_REG_0_PHY_CLK_EN |
+						     AXG_ETH_REG_0_CLK_EN);
+		break;
+
 	case PHY_INTERFACE_MODE_RMII:
 		/* Set RMII mode */
 		out_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
@@ -90,8 +97,6 @@
 	switch (edata->phy_interface) {
 	case PHY_INTERFACE_MODE_RGMII:
 	case PHY_INTERFACE_MODE_RGMII_ID:
-	case PHY_INTERFACE_MODE_RGMII_RXID:
-	case PHY_INTERFACE_MODE_RGMII_TXID:
 		/* Set RGMII mode */
 		setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
 						     GX_ETH_REG_0_TX_PHASE(1) |
@@ -101,6 +106,16 @@
 
 		break;
 
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		/* TOFIX: handle amlogic,tx-delay-ns & rx-internal-delay-ps from DT */
+		setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
+						     GX_ETH_REG_0_TX_RATIO(4) |
+						     GX_ETH_REG_0_PHY_CLK_EN |
+						     GX_ETH_REG_0_CLK_EN);
+
+		break;
+
 	case PHY_INTERFACE_MODE_RMII:
 		/* Set RMII mode */
 		out_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |