diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 3514250..e26436b 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -532,7 +532,7 @@
 	int nodeoff;
 	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
-#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
+#define CFG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
 #if defined(CONFIG_ARCH_T2080)
 	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 				    FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
@@ -554,7 +554,7 @@
 	case 16:
 #endif
 		nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
-							CONFIG_SYS_ELO3_DMA3);
+							CFG_SYS_ELO3_DMA3);
 		if (nodeoff > 0)
 			fdt_status_disabled(blob, nodeoff);
 		else
@@ -616,11 +616,11 @@
 
 	fdt_add_enet_stashing(blob);
 
-#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
-#define CONFIG_FSL_TBCLK_EXTRA_DIV 1
+#ifndef CFG_FSL_TBCLK_EXTRA_DIV
+#define CFG_FSL_TBCLK_EXTRA_DIV 1
 #endif
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-		"timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
+		"timebase-frequency", get_tbclk() / CFG_FSL_TBCLK_EXTRA_DIV,
 		1);
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"bus-frequency", bd->bi_busfreq, 1);