pinctrl: tegra: adjust default values of pins
The current default pin and drive values were more of temporary
placeholders. They have to be replaced with accurate default values as
specified in the TRM and header file.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index e6b957f..b04be16 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -23,18 +23,18 @@
return;
}
- drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", 0);
- drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", 0);
- drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", 0);
- drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", 0);
+ drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", PMUX_SLWF_NONE);
+ drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", PMUX_SLWR_NONE);
+ drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", PMUX_DRVUP_NONE);
+ drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", PMUX_DRVDN_NONE);
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
- drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", 0);
+ drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", PMUX_LPMD_NONE);
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
- drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
+ drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", PMUX_SCHMT_NONE);
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
- drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
+ drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", PMUX_HSM_NONE);
#endif
for (i = 1; i < drvcnt; i++)
@@ -142,31 +142,31 @@
pinmux_group[0].func = i;
- pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", 0);
- pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", 0);
+ pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", PMUX_PULL_NORMAL);
+ pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", PMUX_TRI_TRISTATE);
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
- pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", 0);
+ pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", PMUX_PIN_NONE);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
- pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", 0);
+ pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", PMUX_PIN_LOCK_DEFAULT);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
- pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", 0);
+ pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", PMUX_PIN_OD_DEFAULT);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
- pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", 0);
+ pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", PMUX_PIN_IO_RESET_DEFAULT);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
- pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", 0);
+ pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", PMUX_PIN_RCV_SEL_DEFAULT);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
- pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", 0);
+ pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", PMUX_PIN_E_IO_HV_DEFAULT);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
- pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
+ pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", PMUX_SCHMT_NONE);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_HSM
- pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
+ pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", PMUX_HSM_NONE);
#endif
for (i = 1; i < pincnt; i++)