Merge tag 'u-boot-stm32-20231113' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
Introduce STM32MP2 SoCs family support
Add STM32MP257F-EV1 board
[trini: Adjust some includes]
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6009b7d..a6f0018 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1944,7 +1944,7 @@
select REGMAP
select SYSCON
select SYSRESET
- select SYS_THUMB_BUILD
+ select SYS_THUMB_BUILD if !ARM64
imply SPL_SYSRESET
imply CMD_DM
imply CMD_POWEROFF
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 55aceb5..e0a0d43 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1352,6 +1352,9 @@
stm32mp15xx-dhcor-drc-compact.dtb \
stm32mp15xx-dhcor-testbench.dtb
+dtb-$(CONFIG_STM32MP25X) += \
+ stm32mp257f-ev1.dtb
+
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-base-board.dtb \
k3-am654-r5-base-board.dtb \
diff --git a/arch/arm/dts/stm32mp25-pinctrl.dtsi b/arch/arm/dts/stm32mp25-pinctrl.dtsi
new file mode 100644
index 0000000..d34a1d5
--- /dev/null
+++ b/arch/arm/dts/stm32mp25-pinctrl.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+&pinctrl {
+ usart2_pins_a: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_a: usart2-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_a: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp25-u-boot.dtsi b/arch/arm/dts/stm32mp25-u-boot.dtsi
new file mode 100644
index 0000000..f4f26ad
--- /dev/null
+++ b/arch/arm/dts/stm32mp25-u-boot.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2023
+ */
+
+/ {
+ aliases {
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ gpio25 = &gpioz;
+ pinctrl0 = &pinctrl;
+ pinctrl1 = &pinctrl_z;
+ };
+
+ firmware {
+ optee {
+ bootph-all;
+ };
+ };
+
+ /* need PSCI for sysreset during board_f */
+ psci {
+ bootph-all;
+ };
+
+ soc@0 {
+ bootph-all;
+ };
+};
+
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
+&gpioj {
+ bootph-all;
+};
+
+&gpiok {
+ bootph-all;
+};
+
+&gpioz {
+ bootph-all;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&rifsc {
+ bootph-all;
+};
+
+&scmi_clk {
+ bootph-all;
+};
+
+&syscfg {
+ bootph-all;
+};
diff --git a/arch/arm/dts/stm32mp251.dtsi b/arch/arm/dts/stm32mp251.dtsi
new file mode 100644
index 0000000..cf2f28d
--- /dev/null
+++ b/arch/arm/dts/stm32mp251.dtsi
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a35";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a35-pmu";
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ interrupt-parent = <&intc>;
+ };
+
+ arm_wdt: watchdog {
+ compatible = "arm,smc-wdt";
+ arm,smc-id = <0xb200005a>;
+ status = "disabled";
+ };
+
+ clocks {
+ ck_flexgen_08: ck-flexgen-08 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ ck_flexgen_51: ck-flexgen-51 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+
+ ck_icn_ls_mcu: ck-icn-ls-mcu {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ scmi {
+ compatible = "linaro,scmi-optee";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linaro,optee-channel-id = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
+ intc: interrupt-controller@4ac00000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ interrupt-controller;
+ reg = <0x0 0x4ac10000 0x0 0x1000>,
+ <0x0 0x4ac20000 0x0 0x2000>,
+ <0x0 0x4ac40000 0x0 0x2000>,
+ <0x0 0x4ac60000 0x0 0x2000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ always-on;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges = <0x0 0x0 0x0 0x80000000>;
+
+ rifsc: rifsc-bus@42080000 {
+ compatible = "simple-bus";
+ reg = <0x42080000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usart2: serial@400e0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x400e0000 0x400>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ck_flexgen_08>;
+ status = "disabled";
+ };
+ };
+
+ syscfg: syscon@44230000 {
+ compatible = "st,stm32mp25-syscfg", "syscon";
+ reg = <0x44230000 0x10000>;
+ };
+
+ pinctrl: pinctrl@44240000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp257-pinctrl";
+ ranges = <0 0x44240000 0xa0400>;
+ pins-are-numbered;
+
+ gpioa: gpio@44240000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOA";
+ status = "disabled";
+ };
+
+ gpiob: gpio@44250000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x10000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOB";
+ status = "disabled";
+ };
+
+ gpioc: gpio@44260000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x20000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOC";
+ status = "disabled";
+ };
+
+ gpiod: gpio@44270000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x30000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOD";
+ status = "disabled";
+ };
+
+ gpioe: gpio@44280000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOE";
+ status = "disabled";
+ };
+
+ gpiof: gpio@44290000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x50000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOF";
+ status = "disabled";
+ };
+
+ gpiog: gpio@442a0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x60000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOG";
+ status = "disabled";
+ };
+
+ gpioh: gpio@442b0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x70000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOH";
+ status = "disabled";
+ };
+
+ gpioi: gpio@442c0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x80000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOI";
+ status = "disabled";
+ };
+
+ gpioj: gpio@442d0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x90000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOJ";
+ status = "disabled";
+ };
+
+ gpiok: gpio@442e0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa0000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOK";
+ status = "disabled";
+ };
+ };
+
+ pinctrl_z: pinctrl@46200000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp257-z-pinctrl";
+ ranges = <0 0x46200000 0x400>;
+ pins-are-numbered;
+
+ gpioz: gpio@46200000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ status = "disabled";
+ };
+
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp253.dtsi b/arch/arm/dts/stm32mp253.dtsi
new file mode 100644
index 0000000..af48e82
--- /dev/null
+++ b/arch/arm/dts/stm32mp253.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp251.dtsi"
+
+/ {
+ cpus {
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a35";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+};
diff --git a/arch/arm/dts/stm32mp255.dtsi b/arch/arm/dts/stm32mp255.dtsi
new file mode 100644
index 0000000..e6fa596
--- /dev/null
+++ b/arch/arm/dts/stm32mp255.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp253.dtsi"
+
+/ {
+};
diff --git a/arch/arm/dts/stm32mp257.dtsi b/arch/arm/dts/stm32mp257.dtsi
new file mode 100644
index 0000000..5c5000d
--- /dev/null
+++ b/arch/arm/dts/stm32mp257.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp255.dtsi"
+
+/ {
+};
diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
new file mode 100644
index 0000000..a35a9b9
--- /dev/null
+++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ */
+
+#include "stm32mp25-u-boot.dtsi"
+
+&usart2 {
+ bootph-all;
+};
+
+&usart2_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
diff --git a/arch/arm/dts/stm32mp257f-ev1.dts b/arch/arm/dts/stm32mp257f-ev1.dts
new file mode 100644
index 0000000..a88494e
--- /dev/null
+++ b/arch/arm/dts/stm32mp257f-ev1.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp257.dtsi"
+#include "stm32mp25xf.dtsi"
+#include "stm32mp25-pinctrl.dtsi"
+#include "stm32mp25xxai-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
+ compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
+
+ aliases {
+ serial0 = &usart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x1 0x0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ fw@80000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x80000000 0x0 0x4000000>;
+ no-map;
+ };
+ };
+};
+
+&arm_wdt {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&usart2 {
+ pinctrl-names = "default", "idle", "sleep";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_idle_pins_a>;
+ pinctrl-2 = <&usart2_sleep_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/stm32mp25xc.dtsi b/arch/arm/dts/stm32mp25xc.dtsi
new file mode 100644
index 0000000..5e83a69
--- /dev/null
+++ b/arch/arm/dts/stm32mp25xc.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+};
diff --git a/arch/arm/dts/stm32mp25xf.dtsi b/arch/arm/dts/stm32mp25xf.dtsi
new file mode 100644
index 0000000..5e83a69
--- /dev/null
+++ b/arch/arm/dts/stm32mp25xf.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+};
diff --git a/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi
new file mode 100644
index 0000000..abdbc7a
--- /dev/null
+++ b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AI>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@442d0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@442e0000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
diff --git a/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi
new file mode 100644
index 0000000..2e0d4d3
--- /dev/null
+++ b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AK>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
diff --git a/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
new file mode 100644
index 0000000..2406e97
--- /dev/null
+++ b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AL>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 0eae857..43f7503 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -513,14 +513,6 @@
};
#endif
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
-#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
-#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
-#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
-#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
-#endif
-
/* Size of an MMU section */
enum {
#ifdef CONFIG_ARMV7_LPAE
@@ -578,6 +570,14 @@
#endif /* CONFIG_ARM64 */
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
+#endif
+
#ifndef __ASSEMBLY__
/**
* save_boot_params() - Save boot parameters before starting reset sequence
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index db47bab..5fc92d0 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -76,6 +76,30 @@
STM32MP157, STM32MP153 or STM32MP151
STMicroelectronics MPU with core ARMv7
dual core A7 for STM32MP157/3, monocore for STM32MP151
+
+config STM32MP25X
+ bool "Support STMicroelectronics STM32MP25x Soc"
+ select ARM64
+ select CLK_STM32MP25
+ select OF_BOARD
+ select PINCTRL_STM32
+ select STM32_RCC
+ select STM32_RESET
+ select STM32_SERIAL
+ select SYS_ARCH_TIMER
+ select TFABOOT
+ imply CLK_SCMI
+ imply CMD_NVEDIT_INFO
+ imply DM_REGULATOR
+ imply DM_REGULATOR_SCMI
+ imply OPTEE
+ imply RESET_SCMI
+ imply SYSRESET_PSCI
+ imply TEE
+ imply VERSION_VARIABLE
+ help
+ Support of STMicroelectronics SOC STM32MP25x family
+ STMicroelectronics MPU with 2 * A53 core and 1 M33 core
endchoice
config NR_DRAM_BANKS
@@ -128,6 +152,6 @@
source "arch/arm/mach-stm32mp/Kconfig.13x"
source "arch/arm/mach-stm32mp/Kconfig.15x"
-
+source "arch/arm/mach-stm32mp/Kconfig.25x"
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
endif
diff --git a/arch/arm/mach-stm32mp/Kconfig.25x b/arch/arm/mach-stm32mp/Kconfig.25x
new file mode 100644
index 0000000..2c0f691
--- /dev/null
+++ b/arch/arm/mach-stm32mp/Kconfig.25x
@@ -0,0 +1,43 @@
+if STM32MP25X
+
+choice
+ prompt "STM32MP25x board select"
+ optional
+
+config TARGET_ST_STM32MP25X
+ bool "STMicroelectronics STM32MP25x boards"
+ imply BOOTSTAGE
+ imply CMD_BOOTSTAGE
+ help
+ target the STMicroelectronics board with SOC STM32MP25x
+ managed by board/st/stm32mp2
+ The difference between board are managed with devicetree
+
+endchoice
+
+config TEXT_BASE
+ default 0x84000000
+
+config PRE_CON_BUF_ADDR
+ default 0x84800000
+
+config PRE_CON_BUF_SZ
+ default 4096
+
+config BOOTSTAGE_STASH_ADDR
+ default 0x87000000
+
+if DEBUG_UART
+
+config DEBUG_UART_BOARD_INIT
+ default y
+
+# debug on USART2 by default
+config DEBUG_UART_BASE
+ default 0x400e0000
+
+endif
+
+source "board/st/stm32mp2/Kconfig"
+
+endif
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index a19b279..00dc25b 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -3,24 +3,17 @@
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
#
-obj-y += cpu.o
obj-y += dram_init.o
obj-y += syscon.o
obj-y += bsec.o
-obj-$(CONFIG_STM32MP13x) += stm32mp13x.o
-obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
+obj-$(CONFIG_STM32MP15x) += stm32mp1/
+obj-$(CONFIG_STM32MP13x) += stm32mp1/
+obj-$(CONFIG_STM32MP25X) += stm32mp2/
obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-obj-y += tzc400.o
-else
+ifndef CONFIG_SPL_BUILD
obj-y += cmd_stm32prog/
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
-obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-$(CONFIG_TFABOOT) += boot_params.o
endif
-
-obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o
-obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
index 599e63a..28a8280 100644
--- a/arch/arm/mach-stm32mp/bsec.c
+++ b/arch/arm/mach-stm32mp/bsec.c
@@ -110,7 +110,7 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_lock(u32 address, u32 otp)
+static bool bsec_read_lock(void __iomem *address, u32 otp)
{
u32 bit;
u32 bank;
@@ -118,7 +118,7 @@
bit = 1 << (otp & OTP_LOCK_MASK);
bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
- return !!(readl(address + bank) & bit);
+ return !!(readl((address + bank)) & bit);
}
/**
@@ -127,7 +127,7 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error, -EAGAIN or -ENOTSUPP
*/
-static u32 bsec_check_error(u32 base, u32 otp)
+static u32 bsec_check_error(void __iomem *base, u32 otp)
{
u32 bit;
u32 bank;
@@ -149,7 +149,7 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_SR_lock(u32 base, u32 otp)
+static bool bsec_read_SR_lock(void __iomem *base, u32 otp)
{
return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
}
@@ -160,7 +160,7 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_SP_lock(u32 base, u32 otp)
+static bool bsec_read_SP_lock(void __iomem *base, u32 otp)
{
return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
}
@@ -171,7 +171,7 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_SW_lock(u32 base, u32 otp)
+static bool bsec_read_SW_lock(void __iomem *base, u32 otp)
{
return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
}
@@ -182,7 +182,7 @@
* @power: true to power up , false to power down
* Return: 0 if succeed
*/
-static int bsec_power_safmem(u32 base, bool power)
+static int bsec_power_safmem(void __iomem *base, bool power)
{
u32 val;
u32 mask;
@@ -208,7 +208,7 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
+static int bsec_shadow_register(struct udevice *dev, void __iomem *base, u32 otp)
{
u32 val;
int ret;
@@ -253,7 +253,8 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
+static int bsec_read_shadow(struct udevice *dev, void __iomem *base, u32 *val,
+ u32 otp)
{
*val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
@@ -268,7 +269,7 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
+static int bsec_write_shadow(struct udevice *dev, void __iomem *base, u32 val, u32 otp)
{
/* check if programming of otp is locked */
if (bsec_read_SW_lock(base, otp))
@@ -288,7 +289,7 @@
* after the function the otp data is not refreshed in shadow
* Return: 0 if no error
*/
-static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
+static int bsec_program_otp(struct udevice *dev, void __iomem *base, u32 val, u32 otp)
{
u32 ret;
bool power_up = false;
@@ -338,7 +339,7 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
+static int bsec_permanent_lock_otp(struct udevice *dev, void __iomem *base, uint32_t otp)
{
int ret;
bool power_up = false;
@@ -392,7 +393,7 @@
/* BSEC MISC driver *******************************************************/
struct stm32mp_bsec_plat {
- u32 base;
+ void __iomem *base;
};
struct stm32mp_bsec_priv {
@@ -724,7 +725,7 @@
{
struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
- plat->base = (u32)dev_read_addr_ptr(dev);
+ plat->base = dev_read_addr_ptr(dev);
return 0;
}
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 7f37b0d..fb1208f 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -24,8 +24,11 @@
int ret;
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- log_debug("RAM init failed: %d\n", ret);
+ /* in case there is no RAM driver, retrieve DDR size from DT */
+ if (ret == -ENODEV) {
+ return fdtdec_setup_mem_size_base();
+ } else if (ret) {
+ log_err("RAM init failed: %d\n", ret);
return ret;
}
ret = ram_get_info(dev, &ram);
@@ -33,7 +36,7 @@
log_debug("Cannot get RAM size: %d\n", ret);
return ret;
}
- log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+ log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size);
gd->ram_size = ram.size;
@@ -49,9 +52,15 @@
if (!total_size)
return gd->ram_top;
+ /*
+ * make sure U-Boot uses address space below 4GB boundaries even
+ * if the effective available memory is bigger
+ */
+ gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
+
/* found enough not-reserved memory to relocated U-Boot */
lmb_init(&lmb);
- lmb_add(&lmb, gd->ram_base, get_effective_memsize());
+ lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base);
boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
/* add 8M for reserved memory for display, fdt, gd,... */
size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index 1cdc5e3..b31e4a5 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -6,14 +6,69 @@
#ifndef _MACH_STM32_H_
#define _MACH_STM32_H_
+#include <linux/sizes.h>
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
+
+enum boot_device {
+ BOOT_FLASH_SD = 0x10,
+ BOOT_FLASH_SD_1 = 0x11,
+ BOOT_FLASH_SD_2 = 0x12,
+ BOOT_FLASH_SD_3 = 0x13,
+
+ BOOT_FLASH_EMMC = 0x20,
+ BOOT_FLASH_EMMC_1 = 0x21,
+ BOOT_FLASH_EMMC_2 = 0x22,
+ BOOT_FLASH_EMMC_3 = 0x23,
+
+ BOOT_FLASH_NAND = 0x30,
+ BOOT_FLASH_NAND_FMC = 0x31,
+
+ BOOT_FLASH_NOR = 0x40,
+ BOOT_FLASH_NOR_QSPI = 0x41,
+
+ BOOT_SERIAL_UART = 0x50,
+ BOOT_SERIAL_UART_1 = 0x51,
+ BOOT_SERIAL_UART_2 = 0x52,
+ BOOT_SERIAL_UART_3 = 0x53,
+ BOOT_SERIAL_UART_4 = 0x54,
+ BOOT_SERIAL_UART_5 = 0x55,
+ BOOT_SERIAL_UART_6 = 0x56,
+ BOOT_SERIAL_UART_7 = 0x57,
+ BOOT_SERIAL_UART_8 = 0x58,
+
+ BOOT_SERIAL_USB = 0x60,
+ BOOT_SERIAL_USB_OTG = 0x62,
+
+ BOOT_FLASH_SPINAND = 0x70,
+ BOOT_FLASH_SPINAND_1 = 0x71,
+};
+
+#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
+#define TAMP_BOOT_MODE_SHIFT 8
+#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
+#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
+#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
+#define TAMP_BOOT_DEBUG_ON BIT(16)
+
+enum forced_boot_mode {
+ BOOT_NORMAL = 0x00,
+ BOOT_FASTBOOT = 0x01,
+ BOOT_RECOVERY = 0x02,
+ BOOT_STM32PROG = 0x03,
+ BOOT_UMS_MMC0 = 0x10,
+ BOOT_UMS_MMC1 = 0x11,
+ BOOT_UMS_MMC2 = 0x12,
+};
+
#endif
/*
* Peripheral memory map
* only address used before device tree parsing
*/
+
+#if defined(CONFIG_STM32MP15x) || defined(CONFIG_STM32MP13x)
#define STM32_RCC_BASE 0x50000000
#define STM32_PWR_BASE 0x50001000
#define STM32_SYSCFG_BASE 0x50020000
@@ -58,12 +113,6 @@
#define STM32_DDR_SIZE SZ_1G
#ifndef __ASSEMBLY__
-/* enumerated used to identify the SYSCON driver instance */
-enum {
- STM32MP_SYSCON_UNKNOWN,
- STM32MP_SYSCON_SYSCFG,
-};
-
/*
* enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
* - boot device = bit 8:4
@@ -74,40 +123,6 @@
#define BOOT_INSTANCE_MASK 0x0F
#define BOOT_INSTANCE_SHIFT 0
-enum boot_device {
- BOOT_FLASH_SD = 0x10,
- BOOT_FLASH_SD_1 = 0x11,
- BOOT_FLASH_SD_2 = 0x12,
- BOOT_FLASH_SD_3 = 0x13,
-
- BOOT_FLASH_EMMC = 0x20,
- BOOT_FLASH_EMMC_1 = 0x21,
- BOOT_FLASH_EMMC_2 = 0x22,
- BOOT_FLASH_EMMC_3 = 0x23,
-
- BOOT_FLASH_NAND = 0x30,
- BOOT_FLASH_NAND_FMC = 0x31,
-
- BOOT_FLASH_NOR = 0x40,
- BOOT_FLASH_NOR_QSPI = 0x41,
-
- BOOT_SERIAL_UART = 0x50,
- BOOT_SERIAL_UART_1 = 0x51,
- BOOT_SERIAL_UART_2 = 0x52,
- BOOT_SERIAL_UART_3 = 0x53,
- BOOT_SERIAL_UART_4 = 0x54,
- BOOT_SERIAL_UART_5 = 0x55,
- BOOT_SERIAL_UART_6 = 0x56,
- BOOT_SERIAL_UART_7 = 0x57,
- BOOT_SERIAL_UART_8 = 0x58,
-
- BOOT_SERIAL_USB = 0x60,
- BOOT_SERIAL_USB_OTG = 0x62,
-
- BOOT_FLASH_SPINAND = 0x70,
- BOOT_FLASH_SPINAND_1 = 0x71,
-};
-
/* TAMP registers */
#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
@@ -123,7 +138,6 @@
#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0)
#define TAMP_FWU_BOOT_IDX_OFFSET 0
-
#define TAMP_COPRO_STATE_OFF 0
#define TAMP_COPRO_STATE_INIT 1
#define TAMP_COPRO_STATE_CRUN 2
@@ -137,21 +151,23 @@
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30)
#endif
-#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
-#define TAMP_BOOT_MODE_SHIFT 8
-#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
-#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
-#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */
-enum forced_boot_mode {
- BOOT_NORMAL = 0x00,
- BOOT_FASTBOOT = 0x01,
- BOOT_RECOVERY = 0x02,
- BOOT_STM32PROG = 0x03,
- BOOT_UMS_MMC0 = 0x10,
- BOOT_UMS_MMC1 = 0x11,
- BOOT_UMS_MMC2 = 0x12,
-};
+#if CONFIG_STM32MP25X
+#define STM32_RCC_BASE 0x44200000
+#define STM32_TAMP_BASE 0x46010000
+
+#define STM32_DDR_BASE 0x80000000
+
+#define STM32_DDR_SIZE SZ_4G
+
+/* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */
+#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * (x))
+
+/* TAMP registers zone 3 RIF 1 (RW) at 96*/
+#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96)
+#endif /* STM32MP25X */
/* offset used for BSEC driver: misc_read and misc_write */
#define STM32_BSEC_SHADOW_OFFSET 0x0
@@ -175,6 +191,20 @@
#define BSEC_OTP_MAC 57
#define BSEC_OTP_BOARD 60
#endif
+#ifdef CONFIG_STM32MP25X
+#define BSEC_OTP_SERIAL 5
+#define BSEC_OTP_RPN 9
+#define BSEC_OTP_PKG 246
+#endif
-#endif /* __ASSEMBLY__ */
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* enumerated used to identify the SYSCON driver instance */
+enum {
+ STM32MP_SYSCON_UNKNOWN,
+ STM32MP_SYSCON_SYSCFG,
+};
+#endif /* __ASSEMBLY__*/
+
#endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
index 83fb32a..7b2df09 100644
--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -30,11 +30,30 @@
#define CPU_STM32MP131Fxx 0x05010EC8
#define CPU_STM32MP131Dxx 0x05010EC9
+/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */
+#define CPU_STM32MP257Cxx 0x00002000
+#define CPU_STM32MP255Cxx 0x00082000
+#define CPU_STM32MP253Cxx 0x000B2004
+#define CPU_STM32MP251Cxx 0x000B3065
+#define CPU_STM32MP257Axx 0x40002E00
+#define CPU_STM32MP255Axx 0x40082E00
+#define CPU_STM32MP253Axx 0x400B2E04
+#define CPU_STM32MP251Axx 0x400B3E65
+#define CPU_STM32MP257Fxx 0x80002000
+#define CPU_STM32MP255Fxx 0x80082000
+#define CPU_STM32MP253Fxx 0x800B2004
+#define CPU_STM32MP251Fxx 0x800B3065
+#define CPU_STM32MP257Dxx 0xC0002E00
+#define CPU_STM32MP255Dxx 0xC0082E00
+#define CPU_STM32MP253Dxx 0xC00B2E04
+#define CPU_STM32MP251Dxx 0xC00B3E65
+
/* return CPU_STMP32MP...Xxx constants */
u32 get_cpu_type(void);
#define CPU_DEV_STM32MP15 0x500
#define CPU_DEV_STM32MP13 0x501
+#define CPU_DEV_STM32MP25 0x505
/* return CPU_DEV constants */
u32 get_cpu_dev(void);
@@ -59,6 +78,13 @@
#define STM32MP15_PKG_AD_TFBGA257 1
#define STM32MP15_PKG_UNKNOWN 0
+/* package used for STM32MP25x */
+#define STM32MP25_PKG_CUSTOM 0
+#define STM32MP25_PKG_AL_TBGA361 3
+#define STM32MP25_PKG_AK_TBGA424 4
+#define STM32MP25_PKG_AI_TBGA436 5
+#define STM32MP25_PKG_UNKNOWN 7
+
/* Get SOC name */
#define SOC_NAME_SIZE 20
void get_soc_name(char name[SOC_NAME_SIZE]);
diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile
new file mode 100644
index 0000000..94c7724
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+
+obj-y += cpu.o
+
+obj-$(CONFIG_STM32MP13x) += stm32mp13x.o
+obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
+
+obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += tzc400.o
+else
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
+endif
+
+obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o
+obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
similarity index 100%
rename from arch/arm/mach-stm32mp/cpu.c
rename to arch/arm/mach-stm32mp/stm32mp1/cpu.c
diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c
similarity index 100%
rename from arch/arm/mach-stm32mp/fdt.c
rename to arch/arm/mach-stm32mp/stm32mp1/fdt.c
diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c
similarity index 100%
rename from arch/arm/mach-stm32mp/psci.c
rename to arch/arm/mach-stm32mp/stm32mp1/psci.c
diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c
similarity index 100%
rename from arch/arm/mach-stm32mp/pwr_regulator.c
rename to arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c
similarity index 100%
rename from arch/arm/mach-stm32mp/spl.c
rename to arch/arm/mach-stm32mp/stm32mp1/spl.c
diff --git a/arch/arm/mach-stm32mp/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c
similarity index 100%
rename from arch/arm/mach-stm32mp/stm32mp13x.c
rename to arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c
diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
similarity index 100%
rename from arch/arm/mach-stm32mp/stm32mp15x.c
rename to arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
diff --git a/arch/arm/mach-stm32mp/tzc400.c b/arch/arm/mach-stm32mp/stm32mp1/tzc400.c
similarity index 100%
rename from arch/arm/mach-stm32mp/tzc400.c
rename to arch/arm/mach-stm32mp/stm32mp1/tzc400.c
diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile
new file mode 100644
index 0000000..b579ce5
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+#
+# Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+#
+
+obj-y += cpu.o
+obj-y += arm64-mmu.o
+obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
+obj-$(CONFIG_STM32MP25X) += stm32mp25x.o
diff --git a/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c
new file mode 100644
index 0000000..36c631e
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+#include <mach/stm32.h>
+
+#define MP2_MEM_MAP_MAX 10
+
+#if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \
+ (CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE))
+#error "invalid CONFIG_TEXT_BASE value"
+#endif
+
+struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = {
+ {
+ /* PCIe */
+ .virt = 0x10000000UL,
+ .phys = 0x10000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */
+ .virt = 0x20000000UL,
+ .phys = 0x20000000UL,
+ .size = 0x00200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Peripherals: alias1 */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* OSPI and FMC: memory-map area */
+ .virt = 0x60000000UL,
+ .phys = 0x60000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /*
+ * DDR = STM32_DDR_BASE / STM32_DDR_SIZE
+ * the beginning of DDR (before CONFIG_TEXT_BASE) is not
+ * mapped, protected by RIF and reserved for other firmware
+ * (OP-TEE / TF-M / Cube M33)
+ */
+ .virt = CONFIG_TEXT_BASE,
+ .phys = CONFIG_TEXT_BASE,
+ .size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE),
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = stm32mp2_mem_map;
diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c
new file mode 100644
index 0000000..f43d1aa
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <clk.h>
+#include <cpu_func.h>
+#include <debug_uart.h>
+#include <env_internal.h>
+#include <init.h>
+#include <misc.h>
+#include <wdt.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/system.h>
+#include <dm/device.h>
+#include <dm/lists.h>
+#include <dm/uclass.h>
+
+/*
+ * early TLB into the .data section so that it not get cleared
+ * with 16kB alignment
+ */
+#define EARLY_TLB_SIZE 0xA000
+u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000);
+
+/*
+ * initialize the MMU and activate cache in U-Boot pre-reloc stage
+ * MMU/TLB is updated in enable_caches() for U-Boot after relocation
+ */
+static void early_enable_caches(void)
+{
+ if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
+ gd->arch.tlb_size = EARLY_TLB_SIZE;
+ gd->arch.tlb_addr = (unsigned long)&early_tlb;
+ }
+ /* enable MMU (default configuration) */
+ dcache_enable();
+}
+
+/*
+ * Early system init
+ */
+int arch_cpu_init(void)
+{
+ icache_enable();
+ early_enable_caches();
+
+ return 0;
+}
+
+void enable_caches(void)
+{
+ /* deactivate the data cache, early enabled in arch_cpu_init() */
+ dcache_disable();
+ /*
+ * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr
+ * to update the TLB location udpated in board_f.c::reserve_mmu
+ */
+ gd->arch.tlb_fillptr = 0;
+ dcache_enable();
+}
+
+/* used when CONFIG_DISPLAY_CPUINFO is activated */
+int print_cpuinfo(void)
+{
+ char name[SOC_NAME_SIZE];
+
+ get_soc_name(name);
+ printf("CPU: %s\n", name);
+
+ return 0;
+}
+
+int arch_misc_init(void)
+{
+ return 0;
+}
+
+/*
+ * Force data-section, as .bss will not be valid
+ * when save_boot_params is invoked.
+ */
+static uintptr_t nt_fw_dtb __section(".data");
+
+uintptr_t get_stm32mp_bl2_dtb(void)
+{
+ return nt_fw_dtb;
+}
+
+/*
+ * Save the FDT address provided by TF-A in r2 at boot time
+ * This function is called from start.S
+ */
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3)
+{
+ nt_fw_dtb = r2;
+
+ save_boot_params_ret();
+}
diff --git a/arch/arm/mach-stm32mp/stm32mp2/fdt.c b/arch/arm/mach-stm32mp/stm32mp2/fdt.c
new file mode 100644
index 0000000..31b127b
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp2/fdt.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <asm/u-boot.h>
+
+/*
+ * This function is called right before the kernel is booted. "blob" is the
+ * device tree that will be passed to the kernel.
+ */
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ return 0;
+}
+
diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c
new file mode 100644
index 0000000..4b2f70a
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <log.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+
+/* SYSCFG register */
+#define SYSCFG_DEVICEID_OFFSET 0x6400
+#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
+#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
+#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16)
+#define SYSCFG_DEVICEID_REV_ID_SHIFT 16
+
+/* Device Part Number (RPN) = OTP9 */
+#define RPN_SHIFT 0
+#define RPN_MASK GENMASK(31, 0)
+
+/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
+ * - 000: Custom package
+ * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
+ * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm
+ * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
+ * - others: Reserved
+ */
+#define PKG_SHIFT 0
+#define PKG_MASK GENMASK(2, 0)
+
+static u32 read_deviceid(void)
+{
+ void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+ return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
+}
+
+u32 get_cpu_dev(void)
+{
+ return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
+}
+
+u32 get_cpu_rev(void)
+{
+ return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT;
+}
+
+/* Get Device Part Number (RPN) from OTP */
+u32 get_cpu_type(void)
+{
+ return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
+}
+
+/* Get Package options from OTP */
+u32 get_cpu_package(void)
+{
+ return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
+}
+
+int get_eth_nb(void)
+{
+ int nb_eth;
+
+ switch (get_cpu_type()) {
+ case CPU_STM32MP257Fxx:
+ fallthrough;
+ case CPU_STM32MP257Dxx:
+ fallthrough;
+ case CPU_STM32MP257Cxx:
+ fallthrough;
+ case CPU_STM32MP257Axx:
+ nb_eth = 5; /* dual ETH with TSN support */
+ break;
+ case CPU_STM32MP253Fxx:
+ fallthrough;
+ case CPU_STM32MP253Dxx:
+ fallthrough;
+ case CPU_STM32MP253Cxx:
+ fallthrough;
+ case CPU_STM32MP253Axx:
+ nb_eth = 2; /* dual ETH */
+ break;
+ case CPU_STM32MP251Fxx:
+ fallthrough;
+ case CPU_STM32MP251Dxx:
+ fallthrough;
+ case CPU_STM32MP251Cxx:
+ fallthrough;
+ case CPU_STM32MP251Axx:
+ nb_eth = 1; /* single ETH */
+ break;
+ default:
+ nb_eth = 0;
+ break;
+ }
+
+ return nb_eth;
+}
+
+void get_soc_name(char name[SOC_NAME_SIZE])
+{
+ char *cpu_s, *cpu_r, *package;
+
+ cpu_s = "????";
+ cpu_r = "?";
+ package = "??";
+ if (get_cpu_dev() == CPU_DEV_STM32MP25) {
+ switch (get_cpu_type()) {
+ case CPU_STM32MP257Fxx:
+ cpu_s = "257F";
+ break;
+ case CPU_STM32MP257Dxx:
+ cpu_s = "257D";
+ break;
+ case CPU_STM32MP257Cxx:
+ cpu_s = "257C";
+ break;
+ case CPU_STM32MP257Axx:
+ cpu_s = "257A";
+ break;
+ case CPU_STM32MP255Fxx:
+ cpu_s = "255F";
+ break;
+ case CPU_STM32MP255Dxx:
+ cpu_s = "255D";
+ break;
+ case CPU_STM32MP255Cxx:
+ cpu_s = "255C";
+ break;
+ case CPU_STM32MP255Axx:
+ cpu_s = "255A";
+ break;
+ case CPU_STM32MP253Fxx:
+ cpu_s = "253F";
+ break;
+ case CPU_STM32MP253Dxx:
+ cpu_s = "253D";
+ break;
+ case CPU_STM32MP253Cxx:
+ cpu_s = "253C";
+ break;
+ case CPU_STM32MP253Axx:
+ cpu_s = "253A";
+ break;
+ case CPU_STM32MP251Fxx:
+ cpu_s = "251F";
+ break;
+ case CPU_STM32MP251Dxx:
+ cpu_s = "251D";
+ break;
+ case CPU_STM32MP251Cxx:
+ cpu_s = "251C";
+ break;
+ case CPU_STM32MP251Axx:
+ cpu_s = "251A";
+ break;
+ default:
+ cpu_s = "25??";
+ break;
+ }
+ /* REVISION */
+ switch (get_cpu_rev()) {
+ case CPU_REV1:
+ cpu_r = "A";
+ break;
+ default:
+ break;
+ }
+ /* PACKAGE */
+ switch (get_cpu_package()) {
+ case STM32MP25_PKG_CUSTOM:
+ package = "XX";
+ break;
+ case STM32MP25_PKG_AL_TBGA361:
+ package = "AL";
+ break;
+ case STM32MP25_PKG_AK_TBGA424:
+ package = "AK";
+ break;
+ case STM32MP25_PKG_AI_TBGA436:
+ package = "AI";
+ break;
+ default:
+ break;
+ }
+ }
+
+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r);
+}
diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c
index a0e8e1d..a2e351d 100644
--- a/arch/arm/mach-stm32mp/syscon.c
+++ b/arch/arm/mach-stm32mp/syscon.c
@@ -10,8 +10,8 @@
#include <asm/arch/stm32.h>
static const struct udevice_id stm32mp_syscon_ids[] = {
- { .compatible = "st,stm32mp157-syscfg",
- .data = STM32MP_SYSCON_SYSCFG },
+ { .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG },
+ { .compatible = "st,stm32mp25-syscfg", .data = STM32MP_SYSCON_SYSCFG},
{ }
};