clk: renesas: Handle CLK_TYPE_GEN4_MDSEL in gen3_clk_get_rate64()
Add support of CLK_TYPE_GEN4_MDSEL clock type to gen3_clk_get_rate64()
function. In particular, this type of clock is used by Renesas R-Car
Gen4 watchdog. It operates similarly to CLK_TYPE_GEN3_MDSEL clock.
Signed-off-by: Shmuel Leib Melamud <smelamud@redhat.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Stefan Roese <sr@denx.de>
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 375cc4a..5745acf 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -68,7 +68,7 @@
if (ret)
return ret;
- if (core->type == CLK_TYPE_GEN3_MDSEL) {
+ if (core->type == CLK_TYPE_GEN3_MDSEL || core->type == CLK_TYPE_GEN4_MDSEL) {
shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
parent->dev = clk->dev;
parent->id = core->parent >> shift;
@@ -318,6 +318,8 @@
"FIXED");
case CLK_TYPE_GEN3_MDSEL:
+ fallthrough;
+ case CLK_TYPE_GEN4_MDSEL:
shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
div = (core->div >> shift) & 0xffff;
rate = gen3_clk_get_rate64(&parent) / div;