| commit | 73e31f497a229e20d2bca6450dbe66e8d9882b98 | [log] [tgz] |
|---|---|---|
| author | Tom Rini <trini@konsulko.com> | Mon Mar 31 11:06:14 2025 -0600 |
| committer | Tom Rini <trini@konsulko.com> | Mon Mar 31 17:04:20 2025 -0600 |
| tree | ac77a681297895fe2325086a5610390361797e45 | |
| parent | 155d2a0a0276b3a3aa81b1e2a70e84565ec3dfbd [diff] | |
| parent | c3e397b55e60a2a0472a903aad191b6b94190ac3 [diff] |
Merge patch series "Add WDT support for J7200 SOC" Udit Kumar <u-kumar1@ti.com> says: This enables the ESMs and the associated PMIC. Programming these bits is a requirement to make the watchdog actually reset the board. After DT sync nodes bucka1 and main_esm has bootph property added in pmic nodes. RFC was sent https://lore.kernel.org/all/20241126063543.2678052-1-u-kumar1@ti.com/ With current patch boot logs https://gist.github.com/uditkumarti/adb647f86e6d166ea2d0ac98dceb7a9b reset: https://gist.github.com/uditkumarti/adb647f86e6d166ea2d0ac98dceb7a9b#file-gistfile1-txt-L2344 Link: https://lore.kernel.org/r/20250314110411.2781732-1-u-kumar1@ti.com