Patch by TsiChung Liew, 23 Sep 2004:
- add support for MPC8220 CPU
- Add support for Alaska and Yukon boards
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index e3ff631..b12fe3a 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -50,6 +50,14 @@
unsigned long ipb_clk;
unsigned long pci_clk;
#endif
+#if defined(CONFIG_MPC8220)
+ unsigned long bExtUart;
+ unsigned long inp_clk;
+ unsigned long pci_clk;
+ unsigned long vco_clk;
+ unsigned long pev_clk;
+ unsigned long flb_clk;
+#endif
unsigned long ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long reset_status; /* reset status register at boot */
diff --git a/include/asm-ppc/immap_8220.h b/include/asm-ppc/immap_8220.h
new file mode 100644
index 0000000..f9595f4
--- /dev/null
+++ b/include/asm-ppc/immap_8220.h
@@ -0,0 +1,246 @@
+/*
+ * MPC8220 Internal Memory Map
+ * Copyright (c) 2004 TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * The Internal Memory Map of the 8220.
+ *
+ */
+#ifndef __IMMAP_MPC8220__
+#define __IMMAP_MPC8220__
+
+/*
+ * System configuration registers.
+ */
+typedef struct sys_conf {
+ u16 mbar; /* 0x00 */
+ u16 res1;
+
+ u16 res2; /* 0x04 */
+ u16 sdramds;
+
+ u32 res3[6]; /* 0x08 */
+
+ u32 cscfg[6]; /* 0x20 */
+
+ u32 res4[2]; /* 0x38 */
+
+ u8 res5[3]; /* 0x40 */
+ u8 rstctrl;
+
+ u8 res6[3]; /* 0x44 */
+ u8 rststat;
+
+ u32 res7[2]; /* 0x48 */
+
+ u32 jtagid; /* 0x50 */
+} sysconf8220_t;
+
+
+/*
+ * Memory controller registers.
+ */
+typedef struct mem_ctlr {
+ ushort mode; /* 0x100 */
+ ushort res1;
+ u32 ctrl; /* 0x104 */
+ u32 cfg1; /* 0x108 */
+ u32 cfg2; /* 0x10c */
+} memctl8220_t;
+
+/*
+ * XLB Arbitration registers
+ */
+typedef struct xlb_arb
+{
+ uint res1[16]; /* 0x200 */
+ uint config; /* 0x240 */
+ uint version; /* 0x244 */
+ uint status; /* 0x248 */
+ uint intEnable; /* 0x24c */
+ uint addrCap; /* 0x250 */
+ uint busSigCap; /* 0x254 */
+ uint addrTenTimeOut; /* 0x258 */
+ uint dataTenTimeOut; /* 0x25c */
+ uint busActTimeOut; /* 0x260 */
+ uint mastPriEn; /* 0x264 */
+ uint mastPriority; /* 0x268 */
+ uint baseAddr; /* 0x26c */
+} xlbarb8220_t;
+
+/*
+ * Flexbus registers
+ */
+typedef struct flexbus
+{
+ ushort csar0; /* 0x00 */
+ ushort res1;
+ uint csmr0; /* 0x04 */
+ uint cscr0; /* 0x08 */
+
+ ushort csar1; /* 0x0c */
+ ushort res2;
+ uint csmr1; /* 0x10 */
+ uint cscr1; /* 0x14 */
+
+ ushort csar2; /* 0x18 */
+ ushort res3;
+ uint csmr2; /* 0x1c */
+ uint cscr2; /* 0x20 */
+
+ ushort csar3; /* 0x24 */
+ ushort res4;
+ uint csmr3; /* 0x28 */
+ uint cscr3; /* 0x2c */
+
+ ushort csar4; /* 0x30 */
+ ushort res5;
+ uint csmr4; /* 0x34 */
+ uint cscr4; /* 0x38 */
+
+ ushort csar5; /* 0x3c */
+ ushort res6;
+ uint csmr5; /* 0x40 */
+ uint cscr5; /* 0x44 */
+} flexbus8220_t;
+
+/*
+ * GPIO registers
+ */
+typedef struct gpio
+{
+ u32 out; /* 0x00 */
+ u32 obs; /* 0x04 */
+ u32 obc; /* 0x08 */
+ u32 obt; /* 0x0c */
+ u32 en; /* 0x10 */
+ u32 ebs; /* 0x14 */
+ u32 ebc; /* 0x18 */
+ u32 ebt; /* 0x1c */
+ u32 mc; /* 0x20 */
+ u32 st; /* 0x24 */
+ u32 intr; /* 0x28 */
+} gpio8220_t;
+
+/*
+ * General Purpose Timer registers
+ */
+typedef struct gptimer
+{
+ u8 OCPW;
+ u8 OctIct;
+ u8 Control;
+ u8 Mode;
+
+ u16 Prescl; /* Prescale */
+ u16 Count; /* Count */
+
+ u16 PwmWid; /* PWM Width */
+ u8 PwmOp; /* Output Polarity */
+ u8 PwmLd; /* Immediate Update */
+
+ u16 Capture; /* Capture internal counter */
+ u8 OvfPin; /* Ovf and Pin */
+ u8 Int; /* Interrupts */
+} gptmr8220_t;
+
+/*
+ * PSC registers
+ */
+typedef struct psc
+{
+ u32 mr1_2; /* 0x00 Mode reg 1 & 2 */
+ u32 sr_csr; /* 0x04 Status/Clock Select reg */
+ u32 cr; /* 0x08 Command reg */
+ u8 xmitbuf[4]; /* 0x0c Receive/Transmit Buffer */
+ u32 ipcr_acr; /* 0x10 Input Port Change/Auxiliary Control reg */
+ u32 isr_imr; /* 0x14 Interrupt Status/Mask reg */
+ u32 ctur; /* 0x18 Counter Timer Upper reg */
+ u32 ctlr; /* 0x1c Counter Timer Lower reg */
+ u32 rsvd1[4]; /* 0x20 ... 0x2c */
+ u32 ivr; /* 0x30 Interrupt Vector reg */
+ u32 ipr; /* 0x34 Input Port reg */
+ u32 opsetr; /* 0x38 Output Port Set reg */
+ u32 opresetr; /* 0x3c Output Port Reset reg */
+ u32 sicr; /* 0x40 PSC/IrDA control reg */
+ u32 ircr1; /* 0x44 IrDA control reg 1*/
+ u32 ircr2; /* 0x48 IrDA control reg 2*/
+ u32 irsdr; /* 0x4c IrDA SIR Divide reg */
+ u32 irmdr; /* 0x50 IrDA MIR Divide reg */
+ u32 irfdr; /* 0x54 PSC IrDA FIR Divide reg */
+ u32 rfnum; /* 0x58 RX-FIFO counter */
+ u32 txnum; /* 0x5c TX-FIFO counter */
+ u32 rfdata; /* 0x60 RX-FIFO data */
+ u32 rfstat; /* 0x64 RX-FIFO status */
+ u32 rfcntl; /* 0x68 RX-FIFO control */
+ u32 rfalarm; /* 0x6c RX-FIFO alarm */
+ u32 rfrptr; /* 0x70 RX-FIFO read pointer */
+ u32 rfwptr; /* 0x74 RX-FIFO write pointer */
+ u32 rflfrptr; /* 0x78 RX-FIFO last read frame pointer */
+ u32 rflfwptr; /* 0x7c RX-FIFO last write frame pointer */
+
+ u32 tfdata; /* 0x80 TX-FIFO data */
+ u32 tfstat; /* 0x84 TX-FIFO status */
+ u32 tfcntl; /* 0x88 TX-FIFO control */
+ u32 tfalarm; /* 0x8c TX-FIFO alarm */
+ u32 tfrptr; /* 0x90 TX-FIFO read pointer */
+ u32 tfwptr; /* 0x94 TX-FIFO write pointer */
+ u32 tflfrptr; /* 0x98 TX-FIFO last read frame pointer */
+ u32 tflfwptr; /* 0x9c TX-FIFO last write frame pointer */
+} psc8220_t;
+
+/*
+ * Interrupt Controller registers
+ */
+typedef struct interrupt_controller {
+} intctl8220_t;
+
+
+/* Fast controllers
+*/
+
+/*
+ * I2C registers
+ */
+typedef struct i2c
+{
+ u8 adr; /* 0x00 */
+ u8 res1[3];
+ u8 fdr; /* 0x04 */
+ u8 res2[3];
+ u8 cr; /* 0x08 */
+ u8 res3[3];
+ u8 sr; /* 0x0C */
+ u8 res4[3];
+ u8 dr; /* 0x10 */
+ u8 res5[3];
+ u32 reserved0; /* 0x14 */
+ u32 reserved1; /* 0x18 */
+ u32 reserved2; /* 0x1c */
+ u8 icr; /* 0x20 */
+ u8 res6[3];
+} i2c8220_t;
+
+/*
+ * Port Configuration Registers
+ */
+typedef struct pcfg
+{
+ uint pcfg0; /* 0x00 */
+ uint pcfg1; /* 0x04 */
+ uint pcfg2; /* 0x08 */
+ uint pcfg3; /* 0x0c */
+} pcfg8220_t;
+
+/* ...and the whole thing wrapped up....
+*/
+typedef struct immap {
+ sysconf8220_t im_sysconf; /* System Configuration */
+ memctl8220_t im_memctl; /* Memory Controller */
+ xlbarb8220_t im_xlbarb; /* XLB Arbitration */
+ psc8220_t im_psc; /* PSC controller */
+ flexbus8220_t im_fb; /* FlexBus Controller */
+ i2c8220_t im_i2c; /* I2C control/status */
+ pcfg8220_t im_pcfg; /* Port configuration */
+} immap_t;
+
+#endif /* __IMMAP_MPC8220__ */
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 4608a28..72eabb4 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -45,6 +45,14 @@
#if defined(CONFIG_MPC5xxx)
unsigned long bi_mbar_base; /* base of internal registers */
#endif
+#if defined(CONFIG_MPC8220)
+ unsigned long bi_mbar_base; /* base of internal registers */
+ unsigned long bi_inpfreq; /* Input Freq, In MHz */
+ unsigned long bi_pcifreq; /* PCI Freq, in MHz */
+ unsigned long bi_pevfreq; /* PEV Freq, in MHz */
+ unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */
+ unsigned long bi_vcofreq; /* VCO Freq, in MHz */
+#endif
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
diff --git a/include/common.h b/include/common.h
index 353a15a..697bd7d 100644
--- a/include/common.h
+++ b/include/common.h
@@ -63,6 +63,8 @@
#endif
#elif defined(CONFIG_5xx)
#include <asm/5xx_immap.h>
+#elif defined(CONFIG_MPC8220)
+#include <asm/immap_8220.h>
#elif defined(CONFIG_8260)
#if defined(CONFIG_MPC8247) \
|| defined(CONFIG_MPC8248) \
@@ -355,6 +357,7 @@
defined (CONFIG_74x) || \
defined (CONFIG_75x) || \
defined (CONFIG_74xx) || \
+ defined (CONFIG_MPC8220) || \
defined(CONFIG_MPC85xx)
unsigned char in8(unsigned int);
void out8(unsigned int, unsigned char);
@@ -399,6 +402,9 @@
#if defined(CONFIG_MPC5xxx)
int prt_mpc5xxx_clks (void);
#endif
+#if defined(CONFIG_MPC8220)
+int prt_mpc8220_clks (void);
+#endif
#ifdef CONFIG_4xx
ulong get_OPB_freq (void);
ulong get_PCI_freq (void);
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
new file mode 100644
index 0000000..5cf2a04
--- /dev/null
+++ b/include/configs/Alaska8220.h
@@ -0,0 +1,309 @@
+/*
+ * (C) Copyright 2004
+ * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC8220 1
+#define CONFIG_ALASKA8220 1 /* ... on Alaska board */
+
+/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
+ determine the CPU speed. */
+#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC */
+#define CONFIG_EXTUART_CONSOLE 1
+
+#ifdef CONFIG_EXTUART_CONSOLE
+# define CFG_NS16550
+# define CFG_NS16550_REG_SIZE 1
+# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008)
+#endif
+
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Supported commands
+ */
+/* CONFIG_CMD_DFL includes CFG_CMD_BDI (bdinfo), CFG_CMD_LOADS (loads),
+ CFG_CMD_LOADB (loadb), CFG_CMD_IMI (iminfo), CFG_CMD_FLASH
+ (flinfo, erase, protect), CFG_CMD_MEMORY (md, mm, nm, mw, cp, cmp,
+ crc, base, loop, mtest), CFG_CMD_ENV (printenv, setenv, saveenv),
+ CFG_CMD_BOOTD (bootd), CFG_CMD_CONSOLE (coninfo), CFG_CMD_NET (bootp,
+ tftpboot, rarpboot), CFG_CMD_RUN, CFG_CMD_MISC (sleep, etc),
+ CFG_CMD_BSP, CFG_CMD_IMLS, CFG_CMD_FPGA */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_BOOTD | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_NET | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM \
+ )
+/* CFG_CMD_DHCP | \ */
+/* CFG_CMD_MII | \ */
+/* CFG_CMD_PCI | \ */
+/* CFG_CMD_USB */
+
+# define CONFIG_NET_MULTI
+/*#if (CONFIG_COMMANDS & CFG_CMD_NET)
+# define CONFIG_NET_MULTI
+#else
+# undef CONFIG_NET_MULTI
+#endif*/
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOTARGS "root=/dev/ram rw"
+#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
+#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
+#define CONFIG_IPADDR 192.162.1.2
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_SERVERIP 192.162.1.1
+#define CONFIG_GATEWAYIP 192.162.1.1
+#define CONFIG_HOSTNAME Alaska
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1
+#define CFG_I2C_MODULE 1
+
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
+/*
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_OFFSET 0
+#define CFG_ENV_SIZE 256
+*/
+
+/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
+ else undefined it will boot from Intel Strata flash */
+#define CFG_AMD_BOOT 1
+
+/*
+ * Flexbus Chipselect configuration
+ */
+#if defined (CFG_AMD_BOOT)
+#define CFG_CS0_BASE 0xfff0
+#define CFG_CS0_MASK 0x00080000 /* 512 KB */
+#define CFG_CS0_CTRL 0x003f0d40
+
+#define CFG_CS1_BASE 0xfe00
+#define CFG_CS1_MASK 0x01000000 /* 16 MB */
+#define CFG_CS1_CTRL 0x003f1540
+#else
+#define CFG_CS0_BASE 0xff00
+#define CFG_CS0_MASK 0x01000000 /* 16 MB */
+#define CFG_CS0_CTRL 0x003f1540
+
+#define CFG_CS1_BASE 0xfe08
+#define CFG_CS1_MASK 0x00080000 /* 512 KB */
+#define CFG_CS1_CTRL 0x003f0d40
+#endif
+
+#define CFG_CS2_BASE 0xf100
+#define CFG_CS2_MASK 0x00040000
+#define CFG_CS2_CTRL 0x003f1140
+
+#define CFG_CS3_BASE 0xf200
+#define CFG_CS3_MASK 0x00040000
+#define CFG_CS3_CTRL 0x003f1100
+
+
+#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
+#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16)
+
+#if defined (CFG_AMD_BOOT)
+#define CFG_AMD_BASE CFG_FLASH0_BASE
+#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000
+#define CFG_FLASH_BASE CFG_AMD_BASE
+#else
+#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000
+#define CFG_AMD_BASE CFG_FLASH1_BASE
+#define CFG_FLASH_BASE CFG_INTEL_BASE
+#endif
+
+#define CFG_CPLD_BASE (CFG_CS2_BASE << 16)
+#define CFG_FPGA_BASE (CFG_CS3_BASE << 16)
+
+
+#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
+#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+
+#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
+#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
+
+#define CFG_FLASH_CHECKSUM
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#if defined (CFG_AMD_BOOT)
+#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
+#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
+#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
+#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
+#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
+#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
+#else
+#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
+#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE
+#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
+#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
+#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE
+#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
+#endif
+
+#define CONFIG_ENV_OVERWRITE 1
+
+#if defined CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#endif
+
+#ifndef CFG_JFFS2_FIRST_SECTOR
+#define CFG_JFFS2_FIRST_SECTOR 0
+#endif
+#ifndef CFG_JFFS2_FIRST_BANK
+#define CFG_JFFS2_FIRST_BANK 0
+#endif
+#ifndef CFG_JFFS2_NUM_BANKS
+#define CFG_JFFS2_NUM_BANKS 1
+#endif
+#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+#define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
+#define CFG_SRAM_SIZE 0x8000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
+#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT 1
+#endif
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC8220_FEC 1
+#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
+#define CONFIG_PHY_ADDR 0x18
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+
+#endif /* __CONFIG_H */
diff --git a/include/mpc8220.h b/include/mpc8220.h
new file mode 100644
index 0000000..fe22b8e
--- /dev/null
+++ b/include/mpc8220.h
@@ -0,0 +1,551 @@
+/*
+ * include/mpc8220.h
+ *
+ * Prototypes, etc. for the Motorola MPC8220
+ * embedded cpu chips
+ *
+ * 2004 (c) Freescale, Inc.
+ * Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __MPC8220_H__
+#define __MPC8220_H__
+
+/* Processor name */
+#if defined(CONFIG_MPC8220)
+#define CPU_ID_STR "MPC8220"
+#endif
+
+/* Exception offsets (PowerPC standard) */
+#define EXC_OFF_SYS_RESET 0x0100
+
+/* Internal memory map */
+/* MPC8220 Internal Register MMAP */
+#define MMAP_MBAR (CFG_MBAR + 0x00000000) /* chip selects */
+#define MMAP_MEMCTL (CFG_MBAR + 0x00000100) /* sdram controller */
+#define MMAP_XLBARB (CFG_MBAR + 0x00000200) /* xlb arbitration control */
+#define MMAP_CDM (CFG_MBAR + 0x00000300) /* clock distribution module */
+#define MMAP_VDOPLL (CFG_MBAR + 0x00000400) /* video PLL */
+#define MMAP_FB (CFG_MBAR + 0x00000500) /* flex bus controller */
+#define MMAP_PCFG (CFG_MBAR + 0x00000600) /* port config */
+#define MMAP_ICTL (CFG_MBAR + 0x00000700) /* interrupt controller */
+#define MMAP_GPTMR (CFG_MBAR + 0x00000800) /* general purpose timers */
+#define MMAP_SLTMR (CFG_MBAR + 0x00000900) /* slice timers */
+#define MMAP_GPIO (CFG_MBAR + 0x00000A00) /* gpio module */
+#define MMAP_XCPCI (CFG_MBAR + 0x00000B00) /* pci controller */
+#define MMAP_PCIARB (CFG_MBAR + 0x00000C00) /* pci arbiter */
+#define MMAP_EXTDMA1 (CFG_MBAR + 0x00000D00) /* external dma1 */
+#define MMAP_EXTDMA2 (CFG_MBAR + 0x00000E00) /* external dma1 */
+#define MMAP_USBH (CFG_MBAR + 0x00001000) /* usb host */
+#define MMAP_CMTMR (CFG_MBAR + 0x00007f00) /* comm timers */
+#define MMAP_DMA (CFG_MBAR + 0x00008000) /* dma */
+#define MMAP_USBD (CFG_MBAR + 0x00008200) /* usb device */
+#define MMAP_COMMPCI (CFG_MBAR + 0x00008400) /* pci comm Bus regs */
+#define MMAP_1284 (CFG_MBAR + 0x00008500) /* 1284 */
+#define MMAP_PEV (CFG_MBAR + 0x00008600) /* print engine video */
+#define MMAP_PSC1 (CFG_MBAR + 0x00008800) /* psc1 block */
+#define MMAP_I2C (CFG_MBAR + 0x00008f00) /* i2c controller */
+#define MMAP_FEC1 (CFG_MBAR + 0x00009000) /* fast ethernet 1 */
+#define MMAP_FEC2 (CFG_MBAR + 0x00009800) /* fast ethernet 2 */
+#define MMAP_JBIGRAM (CFG_MBAR + 0x0000a000) /* jbig RAM */
+#define MMAP_JBIG (CFG_MBAR + 0x0000c000) /* jbig */
+#define MMAP_PDLA (CFG_MBAR + 0x00010000) /* */
+#define MMAP_SRAMCFG (CFG_MBAR + 0x0001ff00) /* SRAM config */
+#define MMAP_SRAM (CFG_MBAR + 0x00020000) /* SRAM */
+
+#define SRAM_SIZE 0x8000 /* 32 KB */
+
+/* ------------------------------------------------------------------------ */
+/*
+ * Macro for Programmable Serial Channel
+ */
+/* equates for mode reg. 1 for channel A or B */
+#define PSC_MR1_RX_RTS 0x80000000 /* receiver RTS enabled */
+#define PSC_MR1_RX_INT 0x40000000 /* receiver intrupt enabled */
+#define PSC_MR1_ERR_MODE 0x20000000 /* block error mode */
+#define PSC_MR1_PAR_MODE_MULTI 0x18000000 /* multi_drop mode */
+#define PSC_MR1_NO_PARITY 0x10000000 /* no parity mode */
+#define PSC_MR1_ALWAYS_0 0x08000000 /* force parity mode */
+#define PSC_MR1_ALWAYS_1 0x0c000000 /* force parity mode */
+#define PSC_MR1_EVEN_PARITY 0x00000000 /* parity mode */
+#define PSC_MR1_ODD_PARITY 0x04000000 /* 0 = even, 1 = odd */
+#define PSC_MR1_BITS_CHAR_8 0x03000000 /* 8 bits */
+#define PSC_MR1_BITS_CHAR_7 0x02000000 /* 7 bits */
+#define PSC_MR1_BITS_CHAR_6 0x01000000 /* 6 bits */
+#define PSC_MR1_BITS_CHAR_5 0x00000000 /* 5 bits */
+
+/* equates for mode reg. 2 for channel A or B */
+#define PSC_MR2_NORMAL_MODE 0x00000000 /* normal channel mode */
+#define PSC_MR2_AUTO_MODE 0x40000000 /* automatic channel mode */
+#define PSC_MR2_LOOPBACK_LOCL 0x80000000 /* local loopback channel mode */
+#define PSC_MR2_LOOPBACK_REMT 0xc0000000 /* remote loopback channel mode */
+#define PSC_MR2_TX_RTS 0x20000000 /* transmitter RTS enabled */
+#define PSC_MR2_TX_CTS 0x10000000 /* transmitter CTS enabled */
+#define PSC_MR2_STOP_BITS_2 0x0f000000 /* 2 stop bits */
+#define PSC_MR2_STOP_BITS_1 0x07000000 /* 1 stop bit */
+
+/* equates for status reg. A or B */
+#define PSC_SR_BREAK 0x80000000 /* received break */
+#define PSC_SR_NEOF PSC_SR_BREAK /* Next byte is EOF - MIR/FIR */
+#define PSC_SR_FRAMING 0x40000000 /* framing error */
+#define PSC_SR_PHYERR PSC_SR_FRAMING/* Physical Layer error - MIR/FIR */
+#define PSC_SR_PARITY 0x20000000 /* parity error */
+#define PSC_SR_CRCERR PSC_SR_PARITY /* CRC error */
+#define PSC_SR_OVERRUN 0x10000000 /* overrun error */
+#define PSC_SR_TXEMT 0x08000000 /* transmitter empty */
+#define PSC_SR_TXRDY 0x04000000 /* transmitter ready*/
+#define PSC_SR_FFULL 0x02000000 /* fifo full */
+#define PSC_SR_RXRDY 0x01000000 /* receiver ready */
+#define PSC_SR_DEOF 0x00800000 /* Detect EOF or RX-FIFO contain EOF */
+#define PSC_SR_ERR 0x00400000 /* Error Status including FIFO */
+
+/* equates for clock select reg. */
+#define PSC_CSRX16EXT_CLK 0x1110 /* x 16 ext_clock */
+#define PSC_CSRX1EXT_CLK 0x1111 /* x 1 ext_clock */
+
+/* equates for command reg. A or B */
+#define PSC_CR_NO_COMMAND 0x00000000 /* no command */
+#define PSC_CR_RST_MR_PTR_CMD 0x10000000 /* reset mr pointer command */
+#define PSC_CR_RST_RX_CMD 0x20000000 /* reset receiver command */
+#define PSC_CR_RST_TX_CMD 0x30000000 /* reset transmitter command */
+#define PSC_CR_RST_ERR_STS_CMD 0x40000000 /* reset error status cmnd */
+#define PSC_CR_RST_BRK_INT_CMD 0x50000000 /* reset break int. command */
+#define PSC_CR_STR_BREAK_CMD 0x60000000 /* start break command */
+#define PSC_CR_STP_BREAK_CMD 0x70000000 /* stop break command */
+#define PSC_CR_RX_ENABLE 0x01000000 /* receiver enabled */
+#define PSC_CR_RX_DISABLE 0x02000000 /* receiver disabled */
+#define PSC_CR_TX_ENABLE 0x04000000 /* transmitter enabled */
+#define PSC_CR_TX_DISABLE 0x08000000 /* transmitter disabled */
+
+/* equates for input port change reg. */
+#define PSC_IPCR_SYNC 0x80000000 /* Sync Detect */
+#define PSC_IPCR_D_CTS 0x10000000 /* Delta CTS */
+#define PSC_IPCR_CTS 0x01000000 /* CTS - current state of PSC_CTS */
+
+/* equates for auxiliary control reg. (timer and counter clock selects) */
+#define PSC_ACR_BRG 0x80000000 /* for 68681 compatibility
+ baud rate gen select
+ 0 = set 1; 1 = set 2
+ equates are set 2 ONLY */
+#define PSC_ACR_TMR_EXT_CLK_16 0x70000000 /* xtnl clock divided by 16 */
+#define PSC_ACR_TMR_EXT_CLK 0x60000000 /* external clock */
+#define PSC_ACR_TMR_IP2_16 0x50000000 /* ip2 divided by 16 */
+#define PSC_ACR_TMR_IP2 0x40000000 /* ip2 */
+#define PSC_ACR_CTR_EXT_CLK_16 0x30000000 /* xtnl clock divided by 16 */
+#define PSC_ACR_CTR_TXCB 0x20000000 /* channel B xmitr clock */
+#define PSC_ACR_CTR_TXCA 0x10000000 /* channel A xmitr clock */
+#define PSC_ACR_CTR_IP2 0x00000000 /* ip2 */
+#define PSC_ACR_IEC0 0x01000000 /* interrupt enable ctrl for D_CTS */
+
+/* equates for int. status reg. */
+#define PSC_ISR_IPC 0x80000000 /* input port change*/
+#define PSC_ISR_BREAK 0x04000000 /* delta break */
+#define PSC_ISR_RX_RDY 0x02000000 /* receiver rdy /fifo full */
+#define PSC_ISR_TX_RDY 0x01000000 /* transmitter ready */
+#define PSC_ISR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */
+#define PSC_ISR_ERR 0x00400000 /* Error Status including FIFO */
+
+/* equates for int. mask reg. */
+#define PSC_IMR_CLEAR 0xff000000 /* Clear the imr */
+#define PSC_IMR_IPC 0x80000000 /* input port change*/
+#define PSC_IMR_BREAK 0x04000000 /* delta break */
+#define PSC_IMR_RX_RDY 0x02000000 /* rcvr ready / fifo full */
+#define PSC_IMR_TX_RDY 0x01000000 /* transmitter ready */
+#define PSC_IMR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */
+#define PSC_IMR_ERR 0x00400000 /* Error Status including FIFO */
+
+/* equates for input port reg. */
+#define PSC_IP_LPWRB 0x80000000 /* Low power mode in Ac97 */
+#define PSC_IP_TGL 0x40000000 /* test usage */
+#define PSC_IP_CTS 0x01000000 /* CTS */
+
+/* equates for output port bit set reg. */
+#define PSC_OPSET_RTS 0x01000000 /* Assert PSC_RTS output */
+
+/* equates for output port bit reset reg. */
+#define PSC_OPRESET_RTS 0x01000000 /* Assert PSC_RTS output */
+
+/* equates for rx FIFO number of data reg. */
+#define PSC_RFNUM(x) ((x&0xff)<<24)/* receive count */
+
+/* equates for tx FIFO number of data reg. */
+#define PSC_TFNUM(x) ((x&0xff)<<24)/* receive count */
+
+/* equates for rx FIFO status reg */
+#define PSC_RFSTAT_TAG(x) ((x&3)<<28) /* tag */
+#define PSC_RFSTAT_FRAME0 0x08 /* Frame Indicator 0 */
+#define PSC_RFSTAT_FRAME1 0x04 /* Frame Indicator 1 */
+#define PSC_RFSTAT_FRAME2 0x02 /* Frame Indicator 2 */
+#define PSC_RFSTAT_FRAME3 0x01 /* Frame Indicator 3 */
+#define PSC_RFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */
+#define PSC_RFSTAT_ERR 0x00400000 /* Fifo err */
+#define PSC_RFSTAT_UF 0x00200000 /* Underflow */
+#define PSC_RFSTAT_OF 0x00100000 /* overflow */
+#define PSC_RFSTAT_FR 0x00080000 /* frame ready */
+#define PSC_RFSTAT_FULL 0x00040000 /* full */
+#define PSC_RFSTAT_ALARM 0x00020000 /* alarm */
+#define PSC_RFSTAT_EMPTY 0x00010000 /* empty */
+
+/* equates for tx FIFO status reg */
+#define PSC_TFSTAT_TAG(x) ((x&3)<<28) /* tag */
+#define PSC_TFSTAT_FRAME0 0x08 /* Frame Indicator 0 */
+#define PSC_TFSTAT_FRAME1 0x04 /* Frame Indicator 1 */
+#define PSC_TFSTAT_FRAME2 0x02 /* Frame Indicator 2 */
+#define PSC_TFSTAT_FRAME3 0x01 /* Frame Indicator 3 */
+#define PSC_TFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */
+#define PSC_TFSTAT_ERR 0x00400000 /* Fifo err */
+#define PSC_TFSTAT_UF 0x00200000 /* Underflow */
+#define PSC_TFSTAT_OF 0x00100000 /* overflow */
+#define PSC_TFSTAT_FR 0x00080000 /* frame ready */
+#define PSC_TFSTAT_FULL 0x00040000 /* full */
+#define PSC_TFSTAT_ALARM 0x00020000 /* alarm */
+#define PSC_TFSTAT_EMPTY 0x00010000 /* empty */
+
+/* equates for rx FIFO control reg. */
+#define PSC_RFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */
+#define PSC_RFCNTL_FRAME 0x08000000 /* Frame mode enable */
+#define PSC_RFCNTL_GR(x) ((x&7)<<24) /* Granularity */
+
+/* equates for tx FIFO control reg. */
+#define PSC_TFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */
+#define PSC_TFCNTL_FRAME 0x08000000 /* Frame mode enable */
+#define PSC_TFCNTL_GR(x) ((x&7)<<24) /* Granularity */
+
+/* equates for rx FIFO alarm reg */
+#define PSC_RFALARM(x) (x&0x1ff) /* Alarm */
+
+/* equates for tx FIFO alarm reg */
+#define PSC_TFALARM(x) (x&0x1ff) /* Alarm */
+
+/* equates for rx FIFO read pointer */
+#define PSC_RFRPTR(x) (x&0x1ff) /* read pointer */
+
+/* equates for tx FIFO read pointer */
+#define PSC_TFRPTR(x) (x&0x1ff) /* read pointer */
+
+/* equates for rx FIFO write pointer */
+#define PSC_RFWPTR(x) (x&0x1ff) /* write pointer */
+
+/* equates for rx FIFO write pointer */
+#define PSC_TFWPTR(x) (x&0x1ff) /* write pointer */
+
+/* equates for rx FIFO last read frame pointer reg */
+#define PSC_RFLRFPTR(x) (x&0x1ff) /* last read frame pointer */
+
+/* equates for tx FIFO last read frame pointer reg */
+#define PSC_TFLRFPTR(x) (x&0x1ff) /* last read frame pointer */
+
+/* equates for rx FIFO last write frame pointer reg */
+#define PSC_RFLWFPTR(x) (x&0x1ff) /* last write frame pointer */
+
+/* equates for tx FIFO last write frame pointer reg */
+#define PSC_TFLWFPTR(x) (x&0x1ff) /* last write frame pointer */
+
+
+/* ------------------------------------------------------------------------ */
+/*
+ * Macro for General Purpose Timer
+ */
+/* Enable and Mode Select */
+#define GPT_OCT(x) (x & 0x3)<<4/* Output Compare Type */
+#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
+#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
+#define GPT_CTRL_CE 0x10 /* Counter Enable */
+#define GPT_CTRL_STPCNT 0x04 /* Stop continous */
+#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
+#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
+#define GPT_MODE_GPIO(x) (x & 0x3)<<4/* Gpio Mode Type */
+#define GPT_TMS_ICT 0x01 /* Input Capture Enable */
+#define GPT_TMS_OCT 0x02 /* Output Capture Enable */
+#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
+#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
+
+#define GPT_PWM_WIDTH(x) (x & 0xffff)
+
+/* Status */
+#define GPT_STA_CAPTURE(x) (x & 0xffff)/* Read of internal counter */
+
+#define GPT_OVFPIN_OVF(x) (x & 0x70) /* Internal counter roll over */
+#define GPT_OVFPIN_PIN 0x01 /* Input pin - Timer 0 and 1 */
+
+#define GPT_INT_TEXP 0x08 /* Timer Expired in Internal Timer mode */
+#define GPT_INT_PWMP 0x04 /* PWM end of period occurred */
+#define GPT_INT_COMP 0x02 /* OC reference event occurred */
+#define GPT_INT_CAPT 0x01 /* IC reference event occurred */
+
+/* ------------------------------------------------------------------------ */
+/*
+ * Port configuration
+ */
+#define CFG_FEC1_PORT0_CONFIG 0x00000000
+#define CFG_FEC1_PORT1_CONFIG 0x00000000
+#define CFG_1284_PORT0_CONFIG 0x55555557
+#define CFG_1284_PORT1_CONFIG 0x80000000
+#define CFG_FEC2_PORT2_CONFIG 0x00000000
+#define CFG_PEV_PORT2_CONFIG 0x55555540
+#define CFG_GP0_PORT0_CONFIG 0xaaaaaaa0
+#define CFG_GP1_PORT2_CONFIG 0xaaaaa000
+#define CFG_PSC_PORT3_CONFIG 0x00000000
+#define CFG_CS2_PORT3_CONFIG 0x10000000
+#define CFG_CS3_PORT3_CONFIG 0x40000000
+#define CFG_CS4_PORT3_CONFIG 0x00000400
+#define CFG_CS5_PORT3_CONFIG 0x00000100
+#define CFG_I2C_PORT3_CONFIG 0x003c0000
+
+/* ------------------------------------------------------------------------ */
+/*
+ * DRAM configuration
+ */
+
+/* Field definitions for the control register */
+#define CTL_MODE_ENABLE_SHIFT 31
+#define CTL_CKE_SHIFT 30
+#define CTL_DDR_SHIFT 29
+#define CTL_REFRESH_SHIFT 28
+#define CTL_ADDRMUX_SHIFT 24
+#define CTL_PRECHARGE_SHIFT 23
+#define CTL_DRIVE_RULE_SHIFT 22
+#define CTL_REFRESH_INTERVAL_SHIFT 16
+#define CTL_DQSOEN_SHIFT 8
+#define CTL_BUFFERED_SHIFT 4
+#define CTL_REFRESH_CMD_SHIFT 2
+#define CTL_PRECHARGE_CMD_SHIFT 1
+
+#define CTL_MODE_ENABLE (1<<CTL_MODE_ENABLE_SHIFT)
+#define CTL_CKE_HIGH (1<<CTL_CKE_SHIFT)
+#define CTL_DDR_MODE (1<<CTL_DDR_SHIFT)
+#define CTL_REFRESH_ENABLE (1<<CTL_REFRESH_SHIFT)
+#define CTL_ADDRMUX(value) ((value)<<CTL_ADDRMUX_SHIFT)
+#define CTL_A8PRECHARGE (1<<CTL_PRECHARGE_SHIFT)
+#define CTL_REFRESH_INTERVAL(value) ((value)<<CTL_REFRESH_INTERVAL_SHIFT)
+#define CTL_DQSOEN(value) ((value)<<CTL_DQSOEN_SHIFT)
+#define CTL_BUFFERED (1<<CTL_BUFFERED_SHIFT)
+#define CTL_REFRESH_CMD (1<<CTL_REFRESH_CMD_SHIFT)
+#define CTL_PRECHARGE_CMD (1<<CTL_PRECHARGE_CMD_SHIFT)
+
+/* Field definitions for config register 1 */
+
+#define CFG1_SRD2RWP_SHIFT 28
+#define CFG1_SWT2RWP_SHIFT 24
+#define CFG1_RLATENCY_SHIFT 20
+#define CFG1_ACT2WR_SHIFT 16
+#define CFG1_PRE2ACT_SHIFT 12
+#define CFG1_REF2ACT_SHIFT 8
+#define CFG1_WLATENCY_SHIFT 4
+
+#define CFG1_SRD2RWP(value) ((value)<<CFG1_SRD2RWP_SHIFT)
+#define CFG1_SWT2RWP(value) ((value)<<CFG1_SWT2RWP_SHIFT)
+#define CFG1_RLATENCY(value) ((value)<<CFG1_RLATENCY_SHIFT)
+#define CFG1_ACT2WR(value) ((value)<<CFG1_ACT2WR_SHIFT)
+#define CFG1_PRE2ACT(value) ((value)<<CFG1_PRE2ACT_SHIFT)
+#define CFG1_REF2ACT(value) ((value)<<CFG1_REF2ACT_SHIFT)
+#define CFG1_WLATENCY(value) ((value)<<CFG1_WLATENCY_SHIFT)
+
+/* Field definitions for config register 2 */
+#define CFG2_BRD2RP_SHIFT 28
+#define CFG2_BWT2RWP_SHIFT 24
+#define CFG2_BRD2WT_SHIFT 20
+#define CFG2_BURSTLEN_SHIFT 16
+
+#define CFG2_BRD2RP(value) ((value)<<CFG2_BRD2RP_SHIFT)
+#define CFG2_BWT2RWP(value) ((value)<<CFG2_BWT2RWP_SHIFT)
+#define CFG2_BRD2WT(value) ((value)<<CFG2_BRD2WT_SHIFT)
+#define CFG2_BURSTLEN(value) ((value)<<CFG2_BURSTLEN_SHIFT)
+
+/* Field definitions for the mode/extended mode register - mode
+ * register access
+ */
+#define MODE_REG_SHIFT 30
+#define MODE_OPMODE_SHIFT 25
+#define MODE_CL_SHIFT 22
+#define MODE_BT_SHIFT 21
+#define MODE_BURSTLEN_SHIFT 18
+#define MODE_CMD_SHIFT 16
+
+#define MODE_MODE 0
+#define MODE_OPMODE(value) ((value)<<MODE_OPMODE_SHIFT)
+#define MODE_CL(value) ((value)<<MODE_CL_SHIFT)
+#define MODE_BT_INTERLEAVED (1<<MODE_BT_SHIFT)
+#define MODE_BT_SEQUENTIAL (0<<MODE_BT_SHIFT)
+#define MODE_BURSTLEN(value) ((value)<<MODE_BURSTLEN_SHIFT)
+#define MODE_CMD (1<<MODE_CMD_SHIFT)
+
+#define MODE_BURSTLEN_8 3
+#define MODE_BURSTLEN_4 2
+#define MODE_BURSTLEN_2 1
+
+#define MODE_CL_2 2
+#define MODE_CL_2p5 6
+#define MODE_OPMODE_NORMAL 0
+#define MODE_OPMODE_RESETDLL 2
+
+
+/* Field definitions for the mode/extended mode register - extended
+ * mode register access
+ */
+#define MODE_X_DLL_SHIFT 18 /* DLL enable/disable */
+#define MODE_X_DS_SHIFT 19 /* Drive strength normal/reduced */
+#define MODE_X_QFC_SHIFT 20 /* QFC function (whatever that is) */
+#define MODE_X_OPMODE_SHIFT 21
+
+#define MODE_EXTENDED (1<<MODE_REG_SHIFT)
+#define MODE_X_DLL_ENABLE 0
+#define MODE_X_DLL_DISABLE (1<<MODE_X_DLL_SHIFT)
+#define MODE_X_DS_NORMAL 0
+#define MODE_X_DS_REDUCED (1<<MODE_X_DS_SHIFT)
+#define MODE_X_QFC_DISABLED 0
+#define MODE_X_OPMODE(value) ((value)<<MODE_X_OPMODE_SHIFT)
+
+#ifndef __ASSEMBLY__
+/*
+ * DMA control/status registers.
+ */
+struct mpc8220_dma {
+ u32 taskBar; /* DMA + 0x00 */
+ u32 currentPointer; /* DMA + 0x04 */
+ u32 endPointer; /* DMA + 0x08 */
+ u32 variablePointer;/* DMA + 0x0c */
+
+ u8 IntVect1; /* DMA + 0x10 */
+ u8 IntVect2; /* DMA + 0x11 */
+ u16 PtdCntrl; /* DMA + 0x12 */
+
+ u32 IntPend; /* DMA + 0x14 */
+ u32 IntMask; /* DMA + 0x18 */
+
+ u16 tcr_0; /* DMA + 0x1c */
+ u16 tcr_1; /* DMA + 0x1e */
+ u16 tcr_2; /* DMA + 0x20 */
+ u16 tcr_3; /* DMA + 0x22 */
+ u16 tcr_4; /* DMA + 0x24 */
+ u16 tcr_5; /* DMA + 0x26 */
+ u16 tcr_6; /* DMA + 0x28 */
+ u16 tcr_7; /* DMA + 0x2a */
+ u16 tcr_8; /* DMA + 0x2c */
+ u16 tcr_9; /* DMA + 0x2e */
+ u16 tcr_a; /* DMA + 0x30 */
+ u16 tcr_b; /* DMA + 0x32 */
+ u16 tcr_c; /* DMA + 0x34 */
+ u16 tcr_d; /* DMA + 0x36 */
+ u16 tcr_e; /* DMA + 0x38 */
+ u16 tcr_f; /* DMA + 0x3a */
+
+ u8 IPR0; /* DMA + 0x3c */
+ u8 IPR1; /* DMA + 0x3d */
+ u8 IPR2; /* DMA + 0x3e */
+ u8 IPR3; /* DMA + 0x3f */
+ u8 IPR4; /* DMA + 0x40 */
+ u8 IPR5; /* DMA + 0x41 */
+ u8 IPR6; /* DMA + 0x42 */
+ u8 IPR7; /* DMA + 0x43 */
+ u8 IPR8; /* DMA + 0x44 */
+ u8 IPR9; /* DMA + 0x45 */
+ u8 IPR10; /* DMA + 0x46 */
+ u8 IPR11; /* DMA + 0x47 */
+ u8 IPR12; /* DMA + 0x48 */
+ u8 IPR13; /* DMA + 0x49 */
+ u8 IPR14; /* DMA + 0x4a */
+ u8 IPR15; /* DMA + 0x4b */
+ u8 IPR16; /* DMA + 0x4c */
+ u8 IPR17; /* DMA + 0x4d */
+ u8 IPR18; /* DMA + 0x4e */
+ u8 IPR19; /* DMA + 0x4f */
+ u8 IPR20; /* DMA + 0x50 */
+ u8 IPR21; /* DMA + 0x51 */
+ u8 IPR22; /* DMA + 0x52 */
+ u8 IPR23; /* DMA + 0x53 */
+ u8 IPR24; /* DMA + 0x54 */
+ u8 IPR25; /* DMA + 0x55 */
+ u8 IPR26; /* DMA + 0x56 */
+ u8 IPR27; /* DMA + 0x57 */
+ u8 IPR28; /* DMA + 0x58 */
+ u8 IPR29; /* DMA + 0x59 */
+ u8 IPR30; /* DMA + 0x5a */
+ u8 IPR31; /* DMA + 0x5b */
+
+ u32 res1; /* DMA + 0x5c */
+ u32 res2; /* DMA + 0x60 */
+ u32 res3; /* DMA + 0x64 */
+ u32 MDEDebug; /* DMA + 0x68 */
+ u32 ADSDebug; /* DMA + 0x6c */
+ u32 Value1; /* DMA + 0x70 */
+ u32 Value2; /* DMA + 0x74 */
+ u32 Control; /* DMA + 0x78 */
+ u32 Status; /* DMA + 0x7c */
+ u32 EU00; /* DMA + 0x80 */
+ u32 EU01; /* DMA + 0x84 */
+ u32 EU02; /* DMA + 0x88 */
+ u32 EU03; /* DMA + 0x8c */
+ u32 EU04; /* DMA + 0x90 */
+ u32 EU05; /* DMA + 0x94 */
+ u32 EU06; /* DMA + 0x98 */
+ u32 EU07; /* DMA + 0x9c */
+ u32 EU10; /* DMA + 0xa0 */
+ u32 EU11; /* DMA + 0xa4 */
+ u32 EU12; /* DMA + 0xa8 */
+ u32 EU13; /* DMA + 0xac */
+ u32 EU14; /* DMA + 0xb0 */
+ u32 EU15; /* DMA + 0xb4 */
+ u32 EU16; /* DMA + 0xb8 */
+ u32 EU17; /* DMA + 0xbc */
+ u32 EU20; /* DMA + 0xc0 */
+ u32 EU21; /* DMA + 0xc4 */
+ u32 EU22; /* DMA + 0xc8 */
+ u32 EU23; /* DMA + 0xcc */
+ u32 EU24; /* DMA + 0xd0 */
+ u32 EU25; /* DMA + 0xd4 */
+ u32 EU26; /* DMA + 0xd8 */
+ u32 EU27; /* DMA + 0xdc */
+ u32 EU30; /* DMA + 0xe0 */
+ u32 EU31; /* DMA + 0xe4 */
+ u32 EU32; /* DMA + 0xe8 */
+ u32 EU33; /* DMA + 0xec */
+ u32 EU34; /* DMA + 0xf0 */
+ u32 EU35; /* DMA + 0xf4 */
+ u32 EU36; /* DMA + 0xf8 */
+ u32 EU37; /* DMA + 0xfc */
+};
+
+
+/* function prototypes */
+void loadtask(int basetask, int tasks);
+u32 dramSetup(void);
+
+#if defined(CONFIG_PSC_CONSOLE)
+int psc_serial_init (void);
+void psc_serial_putc(const char c);
+void psc_serial_puts (const char *s);
+int psc_serial_getc(void);
+int psc_serial_tstc(void);
+void psc_serial_setbrg(void);
+#endif
+
+#if defined (CONFIG_EXTUART_CONSOLE)
+int ext_serial_init (void);
+void ext_serial_putc(const char c);
+void ext_serial_puts (const char *s);
+int ext_serial_getc(void);
+int ext_serial_tstc(void);
+void ext_serial_setbrg(void);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __MPC8220_H__ */
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index d4d3b74..72d690e 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -175,7 +175,7 @@
#define IM_IMMR (IM_REGBASE+0x01a8)
#define IM_SCCR (IM_REGBASE+0x0c80)
-#elif defined(CONFIG_MPC5xxx)
+#elif defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8220)
#define HID0_ICE_BITPOS 16
#define HID0_DCE_BITPOS 17