clk: imx: Pass struct udevice into imx_clk_mux*()
Pass struct udevice * into imx_clk_mux*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut <marex@denx.de>
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 378c07c..54eaff2 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -172,19 +172,19 @@
base = (void *)ANATOP_BASE_ADDR;
clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
- imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+ imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MM_ARM_PLL_REF_SEL,
- imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+ imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
- imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
+ imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
- imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
+ imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
- imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+ imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MM_DRAM_PLL,
@@ -205,27 +205,27 @@
/* PLL bypass out */
clk_dm(IMX8MM_DRAM_PLL_BYPASS,
- imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
+ imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1,
dram_pll_bypass_sels,
ARRAY_SIZE(dram_pll_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MM_ARM_PLL_BYPASS,
- imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
+ imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1,
arm_pll_bypass_sels,
ARRAY_SIZE(arm_pll_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MM_SYS_PLL1_BYPASS,
- imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
+ imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1,
sys_pll1_bypass_sels,
ARRAY_SIZE(sys_pll1_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MM_SYS_PLL2_BYPASS,
- imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
+ imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1,
sys_pll2_bypass_sels,
ARRAY_SIZE(sys_pll2_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MM_SYS_PLL3_BYPASS,
- imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
+ imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1,
sys_pll3_bypass_sels,
ARRAY_SIZE(sys_pll3_bypass_sels),
CLK_SET_RATE_PARENT));
@@ -291,7 +291,7 @@
return -EINVAL;
clk_dm(IMX8MM_CLK_A53_SRC,
- imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+ imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3,
imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
clk_dm(IMX8MM_CLK_A53_CG,
imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
@@ -454,7 +454,7 @@
#endif
clk_dm(IMX8MM_CLK_ARM,
- imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
+ imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1,
imx8mm_arm_core_sels,
ARRAY_SIZE(imx8mm_arm_core_sels),
CLK_IS_CRITICAL));