// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for KR260 revB Carrier Card (A03 revision)
 *
 * (C) Copyright 2021 - 2022, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>

/dts-v1/;
/plugin/;

&{/} {
	compatible = "xlnx,zynqmp-sk-kr260-revB",
		     "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";

	ina260-u14 {
		compatible = "iio-hwmon";
		io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
	};

	clk_125: clock0 { /* u87 - GEM0/1 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
	};

	clk_27: clock1 { /* u86 - DP */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};

	clk_26: clock2 { /* u89 - USB */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	clk_156: clock3 { /* u90 - SFP+ */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <156250000>;
	};

	clk_25_0: clock4 { /* u92/u91 - GEM2 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	clk_25_1: clock5 { /* u92/u91 - GEM3 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};
};

&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1_default>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;

	u14: ina260@40 { /* u14 */
		compatible = "ti,ina260";
		#io-channel-cells = <1>;
		label = "ina260-u14";
		reg = <0x40>;
	};

	slg7xl45106: gpio@11 { /* u19 - reset logic */
		compatible = "dlg,slg7xl45106";
		reg = <0x11>;
		label = "resetchip";
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
				  "SD_RESET_B", "USB0_HUB_RESET_B",
				  "USB1_HUB_RESET_B", "PS_GEM0_RESET_B",
				  "PS_GEM1_RESET_B", "";
	};

	i2c-mux@74 { /* u18 */
		compatible = "nxp,pca9546";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x74>;
		usbhub_i2c0: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};
		usbhub_i2c1: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
		/* Bus 2/3 are not connected */
	};

	/* si5332@6a - u17 - clock-generator */
};

/* GEM SGMII/DP and USB 3.0 */
&psgtr {
	status = "okay";
	/* gem0/1, dp, usb */
	clocks = <&clk_125>, <&clk_27>, <&clk_26>;
	clock-names = "ref0", "ref1", "ref2";
};

&zynqmp_dpsub {
	status = "okay";
	phy-names = "dp-phy0";
	phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};

&zynqmp_dpdma {
	status = "okay";
	assigned-clock-rates = <600000000>;
};

&usb0 { /* mio52 - mio63 */
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0_default>;
	phy-names = "usb3-phy";
	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
	reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
	assigned-clock-rates = <250000000>, <20000000>;

	usbhub0: usb-hub { /* u43 */
		i2c-bus = <&usbhub_i2c0>;
		compatible = "microchip,usb5744";
		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
	};

	usb2244: usb-sd { /* u38 */
		compatible = "microchip,usb2244";
		reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
	};
};

&dwc3_0 {
	status = "okay";
	dr_mode = "host";
	snps,usb3_lpm_capable;
	maximum-speed = "super-speed";
};

&usb1 { /* mio64 - mio75 */
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1_default>;
	phy-names = "usb3-phy";
	phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
	reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
	assigned-clock-rates = <250000000>, <20000000>;

	usbhub1: usb-hub { /* u84 */
		i2c-bus = <&usbhub_i2c1>;
		compatible = "microchip,usb5744";
		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
	};
};

&dwc3_1 {
	status = "okay";
	dr_mode = "host";
	snps,usb3_lpm_capable;
	maximum-speed = "super-speed";
};

&gem0 { /* mdio mio50/51 */
	status = "okay";
	phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
	phy-handle = <&phy0>;
	phy-mode = "sgmii";
	is-internal-pcspma;
};

&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gem1_default>;
	phy-handle = <&phy1>;
	phy-mode = "rgmii-id";

	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: ethernet-phy@4 { /* u81 */
			#phy-cells = <1>;
			compatible = "ethernet-phy-id2000.a231";
			reg = <4>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			ti,dp83867-rxctrl-strap-quirk;
			reset-assert-us = <100>;
			reset-deassert-us = <280>;
			reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
		};
		phy1: ethernet-phy@8 { /* u36 */
			#phy-cells = <1>;
			compatible = "ethernet-phy-id2000.a231";
			reg = <8>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			ti,dp83867-rxctrl-strap-quirk;
			reset-assert-us = <100>;
			reset-deassert-us = <280>;
			reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>;
		};
	};
};

/* gem2/gem3 via PL with phys u79@2 and u80@3 */

&pinctrl0 { /* required by spec */
	status = "okay";

	pinctrl_uart1_default: uart1-default {
		conf {
			groups = "uart1_9_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
			drive-strength = <12>;
		};

		conf-rx {
			pins = "MIO37";
			bias-high-impedance;
		};

		conf-tx {
			pins = "MIO36";
			bias-disable;
		};

		mux {
			groups = "uart1_9_grp";
			function = "uart1";
		};
	};

	pinctrl_i2c1_default: i2c1-default {
		conf {
			groups = "i2c1_6_grp";
			bias-pull-up;
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};

		mux {
			groups = "i2c1_6_grp";
			function = "i2c1";
		};
	};

	pinctrl_i2c1_gpio: i2c1-gpio {
		conf {
			groups = "gpio0_24_grp", "gpio0_25_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};

		mux {
			groups = "gpio0_24_grp", "gpio0_25_grp";
			function = "gpio0";
		};
	};

	pinctrl_gem1_default: gem1-default {
		conf {
			groups = "ethernet1_0_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};

		conf-rx {
			pins = "MIO44", "MIO46", "MIO48";
			bias-high-impedance;
			low-power-disable;
		};

		conf-bootstrap {
			pins = "MIO45", "MIO47", "MIO49";
			bias-disable;
			low-power-disable;
		};

		conf-tx {
			pins = "MIO38", "MIO39", "MIO40",
				"MIO41", "MIO42", "MIO43";
			bias-disable;
			low-power-enable;
		};

		conf-mdio {
			groups = "mdio1_0_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
			bias-disable;
		};

		mux-mdio {
			function = "mdio1";
			groups = "mdio1_0_grp";
		};

		mux {
			function = "ethernet1";
			groups = "ethernet1_0_grp";
		};
	};

	pinctrl_usb0_default: usb0-default {
		conf {
			groups = "usb0_0_grp";
			power-source = <IO_STANDARD_LVCMOS18>;
		};

		conf-rx {
			pins = "MIO52", "MIO53", "MIO55";
			bias-high-impedance;
			drive-strength = <12>;
			slew-rate = <SLEW_RATE_FAST>;
		};

		conf-tx {
			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
			"MIO60", "MIO61", "MIO62", "MIO63";
			bias-disable;
			drive-strength = <4>;
			slew-rate = <SLEW_RATE_SLOW>;
		};

		mux {
			groups = "usb0_0_grp";
			function = "usb0";
		};
	};

	pinctrl_usb1_default: usb1-default {
		conf {
			groups = "usb1_0_grp";
			power-source = <IO_STANDARD_LVCMOS18>;
		};

		conf-rx {
			pins = "MIO64", "MIO65", "MIO67";
			bias-high-impedance;
			drive-strength = <12>;
			slew-rate = <SLEW_RATE_FAST>;
		};

		conf-tx {
			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
			"MIO72", "MIO73", "MIO74", "MIO75";
			bias-disable;
			drive-strength = <4>;
			slew-rate = <SLEW_RATE_SLOW>;
		};

		mux {
			groups = "usb1_0_grp";
			function = "usb1";
		};
	};
};

&uart1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1_default>;
};