Merge git://git.denx.de/u-boot-video
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 64e0ee4..83b7aa5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -698,6 +698,7 @@
select SPL_SYS_MALLOC_SIMPLE if SPL
select SYS_NS16550
select SPL_SYS_THUMB_BUILD if !ARM64
+ select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
select USB_STORAGE if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 85b7c70..8bbc981 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -490,3 +490,10 @@
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+
+config HAS_FSL_XHCI_USB
+ bool
+ default y if ARCH_LS1043A || ARCH_LS1046A
+ help
+ For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
+ pins, select it when the pins are assigned to USB.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index bbf8bba..cddcee9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -35,6 +35,7 @@
unsigned int el = current_el();
void *ppa_fit_addr;
u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
+ u32 *loadable_l, *loadable_h;
int ret;
#ifdef CONFIG_CHAIN_OF_TRUST
@@ -240,9 +241,9 @@
PPA_KEY_HASH,
&ppa_img_addr);
if (ret != 0)
- printf("PPA validation failed\n");
+ printf("SEC firmware(s) validation failed\n");
else
- printf("PPA validation Successful\n");
+ printf("SEC firmware(s) validation Successful\n");
}
#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
@@ -254,15 +255,24 @@
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
boot_loc_ptr_l = &gur->bootlocptrl;
boot_loc_ptr_h = &gur->bootlocptrh;
+
+ /* Assign addresses to loadable ptrs */
+ loadable_l = &gur->scratchrw[4];
+ loadable_h = &gur->scratchrw[5];
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
boot_loc_ptr_l = &scfg->scratchrw[1];
boot_loc_ptr_h = &scfg->scratchrw[0];
+
+ /* Assign addresses to loadable ptrs */
+ loadable_l = &scfg->scratchrw[2];
+ loadable_h = &scfg->scratchrw[3];
#endif
debug("fsl-ppa: boot_loc_ptr_l = 0x%p, boot_loc_ptr_h =0x%p\n",
boot_loc_ptr_l, boot_loc_ptr_h);
- ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h);
+ ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h,
+ loadable_l, loadable_h);
#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index 0e74834..927eae4 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -105,6 +105,74 @@
return 0;
}
+/*
+ * SEC Firmware FIT image parser to check if any loadable is
+ * present. If present, verify integrity of the loadable and
+ * copy loadable to address provided in (loadable_h, loadable_l).
+ *
+ * Returns 0 on success and a negative errno on error task fail.
+ */
+static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
+ u32 *loadable_l, u32 *loadable_h)
+{
+ phys_addr_t sec_firmware_loadable_addr = 0;
+ int conf_node_off, ld_node_off;
+ char *conf_node_name = NULL;
+ const void *data;
+ size_t size;
+ ulong load;
+
+ conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME;
+
+ conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
+ if (conf_node_off < 0) {
+ printf("SEC Firmware: %s: no such config\n", conf_node_name);
+ return -ENOENT;
+ }
+
+ ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
+ FIT_LOADABLE_PROP);
+ if (ld_node_off >= 0) {
+ printf("SEC Firmware: '%s' present in config\n",
+ FIT_LOADABLE_PROP);
+
+ /* Verify secure firmware image */
+ if (!(fit_image_verify(sec_firmware_img, ld_node_off))) {
+ printf("SEC Loadable: Bad loadable image (bad CRC)\n");
+ return -EINVAL;
+ }
+
+ if (fit_image_get_data(sec_firmware_img, ld_node_off,
+ &data, &size)) {
+ printf("SEC Loadable: Can't get subimage data/size");
+ return -ENOENT;
+ }
+
+ /* Get load address, treated as load offset to secure memory */
+ if (fit_image_get_load(sec_firmware_img, ld_node_off, &load)) {
+ printf("SEC Loadable: Can't get subimage load");
+ return -ENOENT;
+ }
+
+ /* Compute load address for loadable in secure memory */
+ sec_firmware_loadable_addr = (sec_firmware_addr -
+ gd->arch.tlb_size) + load;
+
+ /* Copy loadable to secure memory and flush dcache */
+ debug("%s copied to address 0x%p\n",
+ FIT_LOADABLE_PROP, (void *)sec_firmware_loadable_addr);
+ memcpy((void *)sec_firmware_loadable_addr, data, size);
+ flush_dcache_range(sec_firmware_loadable_addr,
+ sec_firmware_loadable_addr + size);
+ }
+
+ /* Populate address ptrs for loadable image with loadbale addr */
+ out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK));
+ out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT));
+
+ return 0;
+}
+
static int sec_firmware_copy_image(const char *title,
u64 image_addr, u32 image_size, u64 sec_firmware)
{
@@ -117,9 +185,11 @@
/*
* This function will parse the SEC Firmware image, and then load it
- * to secure memory.
+ * to secure memory. Also load any loadable if present along with SEC
+ * Firmware image.
*/
-static int sec_firmware_load_image(const void *sec_firmware_img)
+static int sec_firmware_load_image(const void *sec_firmware_img,
+ u32 *loadable_l, u32 *loadable_h)
{
const void *raw_image_addr;
size_t raw_image_size = 0;
@@ -172,6 +242,15 @@
if (ret)
goto out;
+ /*
+ * Check if any loadable are present along with firmware image, if
+ * present load them.
+ */
+ ret = sec_firmware_check_copy_loadable(sec_firmware_img, loadable_l,
+ loadable_h);
+ if (ret)
+ goto out;
+
sec_firmware_addr |= SEC_FIRMWARE_LOADED;
debug("SEC Firmware: Entry point: 0x%llx\n",
sec_firmware_addr & SEC_FIRMWARE_ADDR_MASK);
@@ -289,17 +368,22 @@
* @sec_firmware_img: the SEC Firmware image address
* @eret_hold_l: the address to hold exception return address low
* @eret_hold_h: the address to hold exception return address high
+ * @loadable_l: the address to hold loadable address low
+ * @loadable_h: the address to hold loadable address high
*/
int sec_firmware_init(const void *sec_firmware_img,
u32 *eret_hold_l,
- u32 *eret_hold_h)
+ u32 *eret_hold_h,
+ u32 *loadable_l,
+ u32 *loadable_h)
{
int ret;
if (!sec_firmware_is_valid(sec_firmware_img))
return -EINVAL;
- ret = sec_firmware_load_image(sec_firmware_img);
+ ret = sec_firmware_load_image(sec_firmware_img, loadable_l,
+ loadable_h);
if (ret) {
printf("SEC Firmware: Failed to load image\n");
return ret;
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5b90280..6db64f91 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -309,6 +309,7 @@
sun8i-a33-olinuxino.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
+ sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic-edition.dtb \
sun8i-r16-parrot.dtb
dtb-$(CONFIG_MACH_SUN8I_A83T) += \
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index d943a9e..64b4fcf 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -76,6 +76,20 @@
num-cs = <4>;
};
+ usb0: usb3@3100000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 80 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
+ usb1: usb3@3110000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <0 81 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
diff --git a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts
new file mode 100644
index 0000000..eaf0966
--- /dev/null
+++ b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2017 Free Electrons <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BananaPi M2 Magic";
+ compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "bpi-m2m:blue:usr";
+ gpios = <&pio 2 7 GPIO_ACTIVE_LOW>;
+ };
+
+ green {
+ label = "bpi-m2m:green:usr";
+ gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>;
+ };
+
+ red {
+ label = "bpi-m2m:red:power";
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ };
+
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
+ };
+};
+
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc3>;
+};
+
+&cpu0_opp_table {
+ opp@1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+};
+
+&dai {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+/* This is the i2c bus exposed on the DSI connector for the touch panel */
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "disabled";
+};
+
+/* This is the i2c bus exposed on the GPIO header */
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "disabled";
+};
+
+/* This is the i2c bus exposed on the CSI connector to control the sensor */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "disabled";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ vmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <®_aldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp22x: pmic@3a3 {
+ compatible = "x-powers,axp223";
+ reg = <0x3a3>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <®_dcdc1>;
+ x-powers,drive-vbus-en;
+ };
+};
+
+#include "axp223.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-io";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vdd-dll";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-lcd";
+};
+
+®_dc5ldo {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+/*
+ * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same
+ * time, with the two being in sync. Since this is not really
+ * supported right now, just use the two as always on, and we will fix
+ * it later.
+ */
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi0";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi1";
+};
+
+®_drivevbus {
+ regulator-name = "usb0-vbus";
+ status = "okay";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&sound {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_b>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_drivevbus>;
+ usb1_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index 5adfd9b..72e95af 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -1,5 +1,14 @@
#include <config.h>
+/*
+ * This is the maximum size the U-Boot binary can be, which is basically
+ * the start of the environment, minus the start of the U-Boot binary in
+ * the MMC. This makes the assumption that the MMC is using 512-bytes
+ * blocks, but devices using something other than that remains to be
+ * seen.
+ */
+#define UBOOT_MMC_MAX_SIZE (CONFIG_ENV_OFFSET - (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512))
+
/ {
binman {
filename = "u-boot-sunxi-with-spl.bin";
@@ -8,6 +17,9 @@
filename = "spl/sunxi-spl.bin";
};
u-boot-img {
+#ifdef CONFIG_MMC
+ size = <UBOOT_MMC_MAX_SIZE>;
+#endif
pos = <CONFIG_SPL_PAD_TO>;
};
};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index a7098be..95e2791 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -16,7 +16,7 @@
* Reserve secure memory
* To be aligned with MMU block size
*/
-#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
+#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
index 5dfcbf3..b4ea2f8 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
@@ -158,7 +158,7 @@
#define CPU_CLK_SRC_OSC24M 0
#define CPU_CLK_SRC_PLL1 1
-#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0xff) << 8)
+#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8)
#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16)
#define CCM_PLL1_CTRL_EN (0x1 << 31)
#define CMM_PLL1_CLOCK_TIME_2 (0x2 << 24)
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h
index 6d42a71..2ba1847 100644
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -9,8 +9,10 @@
#define PSCI_INVALID_VER 0xffffffff
#define SEC_JR3_OFFSET 0x40000
+#define WORD_MASK 0xffffffff
+#define WORD_SHIFT 32
-int sec_firmware_init(const void *, u32 *, u32 *);
+int sec_firmware_init(const void *, u32 *, u32 *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *);
bool sec_firmware_support_hwrng(void);
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 0e0daf5..e1f1208 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -184,12 +184,18 @@
mtspr SPRN_PIR,r4 /* write to PIR register */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+ mfspr r8, L1CSR2
+ clrrwi r8, r8, 10 /* clear bit [54-63] DCSTASHID */
+ mtspr L1CSR2, r8
+#else
#ifdef CONFIG_SYS_CACHE_STASHING
/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
slwi r8,r4,1
addi r8,r8,32
mtspr L1CSR2,r8
#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index c869ae2..98c56ad 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -402,15 +402,6 @@
do not overwrite the important boot service data which is used by
FSP, otherwise the subsequent call to fsp_notify() will fail.
-config FSP_LOCKDOWN_SPI
- bool
- depends on HAVE_FSP
- help
- Some Intel FSP (like Braswell) does SPI lock-down during the call
- to fsp_notify(INIT_PHASE_BOOT). This option should be turned on
- for such FSP and U-Boot will configure the SPI opcode registers
- before the lock-down.
-
config ENABLE_MRC_CACHE
bool "Enable MRC cache"
depends on !EFI && !SYS_COREBOOT
@@ -664,6 +655,7 @@
config HAVE_ACPI_RESUME
bool "Enable ACPI S3 resume"
+ select ENABLE_MRC_CACHE
help
Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
state where all system context is lost except system memory. U-Boot
diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig
index 0e214a7..31ac279 100644
--- a/arch/x86/cpu/braswell/Kconfig
+++ b/arch/x86/cpu/braswell/Kconfig
@@ -12,7 +12,6 @@
imply HAVE_INTEL_ME
imply HAVE_VBT
imply ENABLE_MRC_CACHE
- imply ENV_IS_IN_SPI_FLASH
imply AHCI_PCI
imply ICH_SPI
imply MMC
@@ -32,8 +31,4 @@
hex
default 0xfff20000
-config FSP_LOCKDOWN_SPI
- bool
- default y
-
endif
diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile
index ddf6d28..4a639b8 100644
--- a/arch/x86/cpu/braswell/Makefile
+++ b/arch/x86/cpu/braswell/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += braswell.o cpu.o early_uart.o fsp_configs.o
+obj-y += braswell.o early_uart.o fsp_configs.o
diff --git a/arch/x86/cpu/braswell/cpu.c b/arch/x86/cpu/braswell/cpu.c
deleted file mode 100644
index 6ff9036..0000000
--- a/arch/x86/cpu/braswell/cpu.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Derived from arch/x86/cpu/baytrail/cpu.c
- */
-
-#include <common.h>
-#include <cpu.h>
-#include <dm.h>
-#include <asm/cpu.h>
-#include <asm/cpu_x86.h>
-#include <asm/io.h>
-#include <asm/lapic.h>
-#include <asm/msr.h>
-#include <asm/turbo.h>
-
-static const unsigned int braswell_bus_freq_table[] = {
- 83333333,
- 100000000,
- 133333333,
- 116666666,
- 80000000,
- 93333333,
- 90000000,
- 88900000,
- 87500000
-};
-
-static unsigned int braswell_bus_freq(void)
-{
- msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
-
- if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))
- return braswell_bus_freq_table[clk_info.lo & 0xf];
-
- return 0;
-}
-
-static unsigned long braswell_tsc_freq(void)
-{
- msr_t platform_info;
- ulong bclk = braswell_bus_freq();
-
- if (!bclk)
- return 0;
-
- platform_info = msr_read(MSR_PLATFORM_INFO);
-
- return bclk * ((platform_info.lo >> 8) & 0xff);
-}
-
-static int braswell_get_info(struct udevice *dev, struct cpu_info *info)
-{
- info->cpu_freq = braswell_tsc_freq();
- info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);
-
- return 0;
-}
-
-static int braswell_get_count(struct udevice *dev)
-{
- int ecx = 0;
-
- /*
- * Use the algorithm described in Intel 64 and IA-32 Architectures
- * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
- * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
- * of CPUID Extended Topology Leaf.
- */
- while (1) {
- struct cpuid_result leaf_b;
-
- leaf_b = cpuid_ext(0xb, ecx);
-
- /*
- * Braswell doesn't have hyperthreading so just determine the
- * number of cores by from level type (ecx[15:8] == * 2)
- */
- if ((leaf_b.ecx & 0xff00) == 0x0200)
- return leaf_b.ebx & 0xffff;
-
- ecx++;
- }
-
- return 0;
-}
-
-static void braswell_set_max_freq(void)
-{
- msr_t perf_ctl;
- msr_t msr;
-
- /* Enable speed step */
- msr = msr_read(MSR_IA32_MISC_ENABLES);
- msr.lo |= (1 << 16);
- msr_write(MSR_IA32_MISC_ENABLES, msr);
-
- /* Enable Burst Mode */
- msr = msr_read(MSR_IA32_MISC_ENABLES);
- msr.hi = 0;
- msr_write(MSR_IA32_MISC_ENABLES, msr);
-
- /*
- * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to
- * bits [15:8] of the PERF_CTL
- */
- msr = msr_read(MSR_IACORE_TURBO_RATIOS);
- perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
-
- /*
- * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to
- * bits [7:0] of the PERF_CTL
- */
- msr = msr_read(MSR_IACORE_TURBO_VIDS);
- perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
-
- perf_ctl.hi = 0;
- msr_write(MSR_IA32_PERF_CTL, perf_ctl);
-}
-
-static int braswell_probe(struct udevice *dev)
-{
- debug("Init Braswell core\n");
-
- /*
- * On Braswell the turbo disable bit is actually scoped at the
- * building-block level, not package. For non-BSP cores that are
- * within a building block, enable turbo. The cores within the BSP's
- * building block will just see it already enabled and move on.
- */
- if (lapicid())
- turbo_enable();
-
- /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
- msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),
- msr_clrsetbits_64(MSR_POWER_MISC,
- ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);
-
- /* Disable C1E */
- msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
- msr_setbits_64(MSR_POWER_MISC, 0x44);
-
- /* Set this core to max frequency ratio */
- braswell_set_max_freq();
-
- return 0;
-}
-
-static const struct udevice_id braswell_ids[] = {
- { .compatible = "intel,braswell-cpu" },
- { }
-};
-
-static const struct cpu_ops braswell_ops = {
- .get_desc = cpu_x86_get_desc,
- .get_info = braswell_get_info,
- .get_count = braswell_get_count,
- .get_vendor = cpu_x86_get_vendor,
-};
-
-U_BOOT_DRIVER(cpu_x86_braswell_drv) = {
- .name = "cpu_x86_braswell",
- .id = UCLASS_CPU,
- .of_match = braswell_ids,
- .bind = cpu_x86_bind,
- .probe = braswell_probe,
- .ops = &braswell_ops,
-};
diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts
index 1ccb605..41e72f3 100644
--- a/arch/x86/dts/cherryhill.dts
+++ b/arch/x86/dts/cherryhill.dts
@@ -37,28 +37,28 @@
cpu@0 {
device_type = "cpu";
- compatible = "intel,braswell-cpu";
+ compatible = "cpu-x86";
reg = <0>;
intel,apic-id = <0>;
};
cpu@1 {
device_type = "cpu";
- compatible = "intel,braswell-cpu";
+ compatible = "cpu-x86";
reg = <1>;
intel,apic-id = <2>;
};
cpu@2 {
device_type = "cpu";
- compatible = "intel,braswell-cpu";
+ compatible = "cpu-x86";
reg = <2>;
intel,apic-id = <4>;
};
cpu@3 {
device_type = "cpu";
- compatible = "intel,braswell-cpu";
+ compatible = "cpu-x86";
reg = <3>;
intel,apic-id = <6>;
};
@@ -143,6 +143,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
+ intel,spi-lock-down;
spi-flash@0 {
#address-cells = <1>;
@@ -194,7 +195,6 @@
fsp,pmic-i2c-bus = <0>;
fsp,enable-isp;
fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
- fsp,turbo-mode;
fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
fsp,sd-detect-chk;
};
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/acpi/sleepstates.asl
similarity index 100%
rename from arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
rename to arch/x86/include/asm/acpi/sleepstates.asl
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
index a80d2c0..cf3de7c 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -36,4 +36,4 @@
}
/* Chipset specific sleep states */
-#include "sleepstates.asl"
+#include <asm/acpi/sleepstates.asl>
diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl
index 1ecf153..db59c46 100644
--- a/arch/x86/include/asm/arch-quark/acpi/platform.asl
+++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl
@@ -33,4 +33,4 @@
}
/* Chipset specific sleep states */
-#include "sleepstates.asl"
+#include <asm/acpi/sleepstates.asl>
diff --git a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
deleted file mode 100644
index 63c82fa..0000000
--- a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
-Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
-Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
-Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index 1714d13..3397bb8 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -19,8 +19,6 @@
DECLARE_GLOBAL_DATA_PTR;
-extern void ich_spi_config_opcode(struct udevice *dev);
-
int checkcpu(void)
{
return 0;
@@ -51,28 +49,6 @@
{
u32 status;
-#ifdef CONFIG_FSP_LOCKDOWN_SPI
- struct udevice *dev;
-
- /*
- * Some Intel FSP (like Braswell) does SPI lock-down during the call
- * to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
- * it's bootloader's responsibility to configure the SPI controller's
- * opcode registers properly otherwise SPI controller driver doesn't
- * know how to communicate with the SPI flash device.
- *
- * Note we cannot do such configuration elsewhere (eg: during the SPI
- * controller driver's probe() routine), because:
- *
- * 1). U-Boot SPI controller driver does not set the lock-down bit
- * 2). Any SPI transfer will corrupt the contents of these registers
- *
- * Hence we have to do it right here before SPI lock-down bit is set.
- */
- if (!uclass_first_device_err(UCLASS_SPI, &dev))
- ich_spi_config_opcode(dev);
-#endif
-
/* call into FspNotify */
debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
status = fsp_notify(NULL, INIT_PHASE_BOOT);
diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
index a19b067..af71276 100644
--- a/arch/x86/lib/fsp/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -37,6 +37,10 @@
/*
* If there is no graphics info structure, bail out and keep
* running on the serial console.
+ *
+ * Note: on some platforms (eg: Braswell), the FSP will not produce
+ * the graphics info HOB unless you plug some cables to the display
+ * interface (eg: HDMI) on the board.
*/
if (!ginfo) {
debug("FSP graphics hand-off block not found\n");
diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c
index de70aee..7fe446e 100644
--- a/board/freescale/ls1088a/eth_ls1088aqds.c
+++ b/board/freescale/ls1088a/eth_ls1088aqds.c
@@ -634,6 +634,7 @@
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
ls1088a_handle_phy_interface_rgmii(i);
break;
case PHY_INTERFACE_MODE_QSGMII:
diff --git a/board/ti/sdp4430/cmd_bat.c b/board/ti/sdp4430/cmd_bat.c
index 7e8dbb1..4c7beeb 100644
--- a/board/ti/sdp4430/cmd_bat.c
+++ b/board/ti/sdp4430/cmd_bat.c
@@ -39,4 +39,4 @@
"bat startcharge - start charging via USB\n"
"bat stopcharge - stop charging\n"
);
-#endif /* CONFIG_BAT_CMD */
+#endif /* CONFIG_CMD_BAT */
diff --git a/cmd/fastboot/Kconfig b/cmd/fastboot/Kconfig
index 214bbc2..4ce7a77 100644
--- a/cmd/fastboot/Kconfig
+++ b/cmd/fastboot/Kconfig
@@ -81,6 +81,16 @@
regarding the non-volatile storage device. Define this to
the eMMC device that fastboot should use to store the image.
+config FASTBOOT_FLASH_NAND_DEV
+ int "Define FASTBOOT NAND FLASH default device"
+ depends on FASTBOOT_FLASH && NAND
+ depends on CMD_MTDPARTS
+ default 0 if ARCH_SUNXI && NAND_SUNXI
+ help
+ The fastboot "flash" command requires additional information
+ regarding the non-volatile storage device. Define this to
+ the NAND device that fastboot should use to store the image.
+
config FASTBOOT_GPT_NAME
string "Target name for updating GPT"
depends on FASTBOOT_FLASH
diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig
new file mode 100644
index 0000000..82cd2c4
--- /dev/null
+++ b/configs/Bananapi_m2m_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_CONS_INDEX=1
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=600
+CONFIG_DRAM_ZQ=15291
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_ID_DET="PH8"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-bananapi-m2m"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index c1849e3..f91890c 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -6,8 +6,6 @@
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_FIT=y
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -25,7 +23,6 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index 6a542ed..a75d403 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -30,3 +30,12 @@
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CMD_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index 52b10af..bd44fa9 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -30,3 +30,12 @@
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CMD_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index 5918e72..e5fea42 100644
--- a/configs/orangepi_pc2_defconfig
+++ b/configs/orangepi_pc2_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
index 1a16ed1..5792e7a 100644
--- a/configs/orangepi_zero_defconfig
+++ b/configs/orangepi_zero_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e7ade94..3a8c61b 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -10,7 +10,6 @@
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
-obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
@@ -21,7 +20,6 @@
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
-obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o
diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c
deleted file mode 100644
index d340639..0000000
--- a/drivers/i2c/adi_i2c.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * i2c.c - driver for ADI TWI/I2C
- *
- * Copyright (c) 2006-2014 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <common.h>
-#include <console.h>
-#include <i2c.h>
-
-#include <asm/clock.h>
-#include <asm/twi.h>
-#include <asm/io.h>
-
-static struct twi_regs *i2c_get_base(struct i2c_adapter *adap);
-
-/* Every register is 32bit aligned, but only 16bits in size */
-#define ureg(name) u16 name; u16 __pad_##name;
-struct twi_regs {
- ureg(clkdiv);
- ureg(control);
- ureg(slave_ctl);
- ureg(slave_stat);
- ureg(slave_addr);
- ureg(master_ctl);
- ureg(master_stat);
- ureg(master_addr);
- ureg(int_stat);
- ureg(int_mask);
- ureg(fifo_ctl);
- ureg(fifo_stat);
- char __pad[0x50];
- ureg(xmt_data8);
- ureg(xmt_data16);
- ureg(rcv_data8);
- ureg(rcv_data16);
-};
-#undef ureg
-
-#ifdef TWI_CLKDIV
-#define TWI0_CLKDIV TWI_CLKDIV
-# ifdef CONFIG_SYS_MAX_I2C_BUS
-# undef CONFIG_SYS_MAX_I2C_BUS
-# endif
-#define CONFIG_SYS_MAX_I2C_BUS 1
-#endif
-
-/*
- * The way speed is changed into duty often results in integer truncation
- * with 50% duty, so we'll force rounding up to the next duty by adding 1
- * to the max. In practice this will get us a speed of something like
- * 385 KHz. The other limit is easy to handle as it is only 8 bits.
- */
-#define I2C_SPEED_MAX 400000
-#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
-#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
-#define I2C_DUTY_MIN 0xff /* 8 bit limited */
-#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
-/* Note: duty is inverse of speed, so the comparisons below are correct */
-#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
-# error "The I2C hardware can only operate 20KHz - 400KHz"
-#endif
-
-/* All transfers are described by this data structure */
-struct adi_i2c_msg {
- u8 flags;
-#define I2C_M_COMBO 0x4
-#define I2C_M_STOP 0x2
-#define I2C_M_READ 0x1
- int len; /* msg length */
- u8 *buf; /* pointer to msg data */
- int alen; /* addr length */
- u8 *abuf; /* addr buffer */
-};
-
-/* Allow msec timeout per ~byte transfer */
-#define I2C_TIMEOUT 10
-
-/**
- * wait_for_completion - manage the actual i2c transfer
- * @msg: the i2c msg
- */
-static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg)
-{
- u16 int_stat, ctl;
- ulong timebase = get_timer(0);
-
- do {
- int_stat = readw(&twi->int_stat);
-
- if (int_stat & XMTSERV) {
- writew(XMTSERV, &twi->int_stat);
- if (msg->alen) {
- writew(*(msg->abuf++), &twi->xmt_data8);
- --msg->alen;
- } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
- writew(*(msg->buf++), &twi->xmt_data8);
- --msg->len;
- } else {
- ctl = readw(&twi->master_ctl);
- if (msg->flags & I2C_M_COMBO)
- writew(ctl | RSTART | MDIR,
- &twi->master_ctl);
- else
- writew(ctl | STOP, &twi->master_ctl);
- }
- }
- if (int_stat & RCVSERV) {
- writew(RCVSERV, &twi->int_stat);
- if (msg->len) {
- *(msg->buf++) = readw(&twi->rcv_data8);
- --msg->len;
- } else if (msg->flags & I2C_M_STOP) {
- ctl = readw(&twi->master_ctl);
- writew(ctl | STOP, &twi->master_ctl);
- }
- }
- if (int_stat & MERR) {
- writew(MERR, &twi->int_stat);
- return msg->len;
- }
- if (int_stat & MCOMP) {
- writew(MCOMP, &twi->int_stat);
- if (msg->flags & I2C_M_COMBO && msg->len) {
- ctl = readw(&twi->master_ctl);
- ctl = (ctl & ~RSTART) |
- (min(msg->len, 0xff) << 6) | MEN | MDIR;
- writew(ctl, &twi->master_ctl);
- } else
- break;
- }
-
- /* If we were able to do something, reset timeout */
- if (int_stat)
- timebase = get_timer(0);
-
- } while (get_timer(timebase) < I2C_TIMEOUT);
-
- return msg->len;
-}
-
-static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
- int alen, uint8_t *buffer, int len, uint8_t flags)
-{
- struct twi_regs *twi = i2c_get_base(adap);
- int ret;
- u16 ctl;
- uchar addr_buffer[] = {
- (addr >> 0),
- (addr >> 8),
- (addr >> 16),
- };
- struct adi_i2c_msg msg = {
- .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
- .buf = buffer,
- .len = len,
- .abuf = addr_buffer,
- .alen = alen,
- };
-
- /* wait for things to settle */
- while (readw(&twi->master_stat) & BUSBUSY)
- if (ctrlc())
- return 1;
-
- /* Set Transmit device address */
- writew(chip, &twi->master_addr);
-
- /* Clear the FIFO before starting things */
- writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
- writew(0, &twi->fifo_ctl);
-
- /* prime the pump */
- if (msg.alen) {
- len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
- writew(*(msg.abuf++), &twi->xmt_data8);
- --msg.alen;
- } else if (!(msg.flags & I2C_M_READ) && msg.len) {
- writew(*(msg.buf++), &twi->xmt_data8);
- --msg.len;
- }
-
- /* clear int stat */
- writew(-1, &twi->master_stat);
- writew(-1, &twi->int_stat);
- writew(0, &twi->int_mask);
-
- /* Master enable */
- ctl = readw(&twi->master_ctl);
- ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
- ((msg.flags & I2C_M_READ) ? MDIR : 0);
- writew(ctl, &twi->master_ctl);
-
- /* process the rest */
- ret = wait_for_completion(twi, &msg);
-
- if (ret) {
- ctl = readw(&twi->master_ctl) & ~MEN;
- writew(ctl, &twi->master_ctl);
- ctl = readw(&twi->control) & ~TWI_ENA;
- writew(ctl, &twi->control);
- ctl = readw(&twi->control) | TWI_ENA;
- writew(ctl, &twi->control);
- }
-
- return ret;
-}
-
-static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
-{
- struct twi_regs *twi = i2c_get_base(adap);
- u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
-
- /* Set TWI interface clock */
- if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
- return -1;
- clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
- writew(clkdiv, &twi->clkdiv);
-
- /* Don't turn it on */
- writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
-
- return 0;
-}
-
-static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
- struct twi_regs *twi = i2c_get_base(adap);
- u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
-
- /* Set TWI internal clock as 10MHz */
- writew(prescale, &twi->control);
-
- /* Set TWI interface clock as specified */
- i2c_set_bus_speed(speed);
-
- /* Enable it */
- writew(TWI_ENA | prescale, &twi->control);
-}
-
-static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
- uint addr, int alen, uint8_t *buffer, int len)
-{
- return i2c_transfer(adap, chip, addr, alen, buffer,
- len, alen ? I2C_M_COMBO : I2C_M_READ);
-}
-
-static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
- uint addr, int alen, uint8_t *buffer, int len)
-{
- return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
-}
-
-static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
-{
- u8 byte;
- return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
-}
-
-static struct twi_regs *i2c_get_base(struct i2c_adapter *adap)
-{
- switch (adap->hwadapnr) {
-#if CONFIG_SYS_MAX_I2C_BUS > 2
- case 2:
- return (struct twi_regs *)TWI2_CLKDIV;
-#endif
-#if CONFIG_SYS_MAX_I2C_BUS > 1
- case 1:
- return (struct twi_regs *)TWI1_CLKDIV;
-#endif
- case 0:
- return (struct twi_regs *)TWI0_CLKDIV;
-
- default:
- printf("wrong hwadapnr: %d\n", adap->hwadapnr);
- }
-
- return NULL;
-}
-
-U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
- adi_i2c_read, adi_i2c_write,
- adi_i2c_setspeed,
- CONFIG_SYS_I2C_SPEED,
- 0,
- 0)
-
-#if CONFIG_SYS_MAX_I2C_BUS > 1
-U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
- adi_i2c_read, adi_i2c_write,
- adi_i2c_setspeed,
- CONFIG_SYS_I2C_SPEED,
- 0,
- 1)
-#endif
-
-#if CONFIG_SYS_MAX_I2C_BUS > 2
-U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
- adi_i2c_read, adi_i2c_write,
- adi_i2c_setspeed,
- CONFIG_SYS_I2C_SPEED,
- 0,
- 2)
-#endif
diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c
deleted file mode 100644
index 4da959f..0000000
--- a/drivers/i2c/fti2c010.c
+++ /dev/null
@@ -1,340 +0,0 @@
-/*
- * Faraday I2C Controller
- *
- * (C) Copyright 2010 Faraday Technology
- * Dante Su <dantesu@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <i2c.h>
-
-#include "fti2c010.h"
-
-#ifndef CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SPEED 5000
-#endif
-
-#ifndef CONFIG_SYS_I2C_SLAVE
-#define CONFIG_SYS_I2C_SLAVE 0
-#endif
-
-#ifndef CONFIG_FTI2C010_CLOCK
-#define CONFIG_FTI2C010_CLOCK clk_get_rate("I2C")
-#endif
-
-#ifndef CONFIG_FTI2C010_TIMEOUT
-#define CONFIG_FTI2C010_TIMEOUT 10 /* ms */
-#endif
-
-/* 7-bit dev address + 1-bit read/write */
-#define I2C_RD(dev) ((((dev) << 1) & 0xfe) | 1)
-#define I2C_WR(dev) (((dev) << 1) & 0xfe)
-
-struct fti2c010_chip {
- struct fti2c010_regs *regs;
-};
-
-static struct fti2c010_chip chip_list[] = {
- {
- .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE,
- },
-#ifdef CONFIG_FTI2C010_BASE1
- {
- .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1,
- },
-#endif
-#ifdef CONFIG_FTI2C010_BASE2
- {
- .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2,
- },
-#endif
-#ifdef CONFIG_FTI2C010_BASE3
- {
- .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3,
- },
-#endif
-};
-
-static int fti2c010_reset(struct fti2c010_chip *chip)
-{
- ulong ts;
- int ret = -1;
- struct fti2c010_regs *regs = chip->regs;
-
- writel(CR_I2CRST, ®s->cr);
- for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
- if (!(readl(®s->cr) & CR_I2CRST)) {
- ret = 0;
- break;
- }
- }
-
- if (ret)
- printf("fti2c010: reset timeout\n");
-
- return ret;
-}
-
-static int fti2c010_wait(struct fti2c010_chip *chip, uint32_t mask)
-{
- int ret = -1;
- uint32_t stat, ts;
- struct fti2c010_regs *regs = chip->regs;
-
- for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
- stat = readl(®s->sr);
- if ((stat & mask) == mask) {
- ret = 0;
- break;
- }
- }
-
- return ret;
-}
-
-static unsigned int set_i2c_bus_speed(struct fti2c010_chip *chip,
- unsigned int speed)
-{
- struct fti2c010_regs *regs = chip->regs;
- unsigned int clk = CONFIG_FTI2C010_CLOCK;
- unsigned int gsr = 0;
- unsigned int tsr = 32;
- unsigned int div, rate;
-
- for (div = 0; div < 0x3ffff; ++div) {
- /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
- rate = clk / (2 * (div + 2) + gsr);
- if (rate <= speed)
- break;
- }
-
- writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr);
- writel(CDR_DIV(div), ®s->cdr);
-
- return rate;
-}
-
-/*
- * Initialization, must be called once on start up, may be called
- * repeatedly to change the speed and slave addresses.
- */
-static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
- struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
-
- if (adap->init_done)
- return;
-
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- /* Call board specific i2c bus reset routine before accessing the
- * environment, which might be in a chip on that bus. For details
- * about this problem see doc/I2C_Edge_Conditions.
- */
- i2c_init_board();
-#endif
-
- /* master init */
-
- fti2c010_reset(chip);
-
- set_i2c_bus_speed(chip, speed);
-
- /* slave init, don't care */
-}
-
-/*
- * Probe the given I2C chip address. Returns 0 if a chip responded,
- * not 0 on failure.
- */
-static int fti2c010_probe(struct i2c_adapter *adap, u8 dev)
-{
- struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
- struct fti2c010_regs *regs = chip->regs;
- int ret;
-
- /* 1. Select slave device (7bits Address + 1bit R/W) */
- writel(I2C_WR(dev), ®s->dr);
- writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
-
- /* 2. Select device register */
- writel(0, ®s->dr);
- writel(CR_ENABLE | CR_TBEN, ®s->cr);
- ret = fti2c010_wait(chip, SR_DT);
-
- return ret;
-}
-
-static void to_i2c_addr(u8 *buf, uint32_t addr, int alen)
-{
- int i, shift;
-
- if (!buf || alen <= 0)
- return;
-
- /* MSB first */
- i = 0;
- shift = (alen - 1) * 8;
- while (alen-- > 0) {
- buf[i] = (u8)(addr >> shift);
- shift -= 8;
- }
-}
-
-static int fti2c010_read(struct i2c_adapter *adap,
- u8 dev, uint addr, int alen, uchar *buf, int len)
-{
- struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
- struct fti2c010_regs *regs = chip->regs;
- int ret, pos;
- uchar paddr[4] = { 0 };
-
- to_i2c_addr(paddr, addr, alen);
-
- /*
- * Phase A. Set register address
- */
-
- /* A.1 Select slave device (7bits Address + 1bit R/W) */
- writel(I2C_WR(dev), ®s->dr);
- writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
-
- /* A.2 Select device register */
- for (pos = 0; pos < alen; ++pos) {
- uint32_t ctrl = CR_ENABLE | CR_TBEN;
-
- writel(paddr[pos], ®s->dr);
- writel(ctrl, ®s->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
- }
-
- /*
- * Phase B. Get register data
- */
-
- /* B.1 Select slave device (7bits Address + 1bit R/W) */
- writel(I2C_RD(dev), ®s->dr);
- writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
-
- /* B.2 Get register data */
- for (pos = 0; pos < len; ++pos) {
- uint32_t ctrl = CR_ENABLE | CR_TBEN;
- uint32_t stat = SR_DR;
-
- if (pos == len - 1) {
- ctrl |= CR_NAK | CR_STOP;
- stat |= SR_ACK;
- }
- writel(ctrl, ®s->cr);
- ret = fti2c010_wait(chip, stat);
- if (ret)
- break;
- buf[pos] = (uchar)(readl(®s->dr) & 0xFF);
- }
-
- return ret;
-}
-
-static int fti2c010_write(struct i2c_adapter *adap,
- u8 dev, uint addr, int alen, u8 *buf, int len)
-{
- struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
- struct fti2c010_regs *regs = chip->regs;
- int ret, pos;
- uchar paddr[4] = { 0 };
-
- to_i2c_addr(paddr, addr, alen);
-
- /*
- * Phase A. Set register address
- *
- * A.1 Select slave device (7bits Address + 1bit R/W)
- */
- writel(I2C_WR(dev), ®s->dr);
- writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
-
- /* A.2 Select device register */
- for (pos = 0; pos < alen; ++pos) {
- uint32_t ctrl = CR_ENABLE | CR_TBEN;
-
- writel(paddr[pos], ®s->dr);
- writel(ctrl, ®s->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
- }
-
- /*
- * Phase B. Set register data
- */
- for (pos = 0; pos < len; ++pos) {
- uint32_t ctrl = CR_ENABLE | CR_TBEN;
-
- if (pos == len - 1)
- ctrl |= CR_STOP;
- writel(buf[pos], ®s->dr);
- writel(ctrl, ®s->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- break;
- }
-
- return ret;
-}
-
-static unsigned int fti2c010_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
-{
- struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
- int ret;
-
- fti2c010_reset(chip);
- ret = set_i2c_bus_speed(chip, speed);
-
- return ret;
-}
-
-/*
- * Register i2c adapters
- */
-U_BOOT_I2C_ADAP_COMPLETE(i2c_0, fti2c010_init, fti2c010_probe, fti2c010_read,
- fti2c010_write, fti2c010_set_bus_speed,
- CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- 0)
-#ifdef CONFIG_FTI2C010_BASE1
-U_BOOT_I2C_ADAP_COMPLETE(i2c_1, fti2c010_init, fti2c010_probe, fti2c010_read,
- fti2c010_write, fti2c010_set_bus_speed,
- CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- 1)
-#endif
-#ifdef CONFIG_FTI2C010_BASE2
-U_BOOT_I2C_ADAP_COMPLETE(i2c_2, fti2c010_init, fti2c010_probe, fti2c010_read,
- fti2c010_write, fti2c010_set_bus_speed,
- CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- 2)
-#endif
-#ifdef CONFIG_FTI2C010_BASE3
-U_BOOT_I2C_ADAP_COMPLETE(i2c_3, fti2c010_init, fti2c010_probe, fti2c010_read,
- fti2c010_write, fti2c010_set_bus_speed,
- CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- 3)
-#endif
diff --git a/drivers/i2c/fti2c010.h b/drivers/i2c/fti2c010.h
deleted file mode 100644
index b9d0eb7..0000000
--- a/drivers/i2c/fti2c010.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Faraday I2C Controller
- *
- * (C) Copyright 2010 Faraday Technology
- * Dante Su <dantesu@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __FTI2C010_H
-#define __FTI2C010_H
-
-/*
- * FTI2C010 registers
- */
-struct fti2c010_regs {
- uint32_t cr; /* 0x00: control register */
- uint32_t sr; /* 0x04: status register */
- uint32_t cdr; /* 0x08: clock division register */
- uint32_t dr; /* 0x0c: data register */
- uint32_t sar; /* 0x10: slave address register */
- uint32_t tgsr;/* 0x14: time & glitch suppression register */
- uint32_t bmr; /* 0x18: bus monitor register */
- uint32_t rsvd[5];
- uint32_t revr;/* 0x30: revision register */
-};
-
-/*
- * control register
- */
-#define CR_ALIRQ 0x2000 /* arbitration lost interrupt (master) */
-#define CR_SAMIRQ 0x1000 /* slave address match interrupt (slave) */
-#define CR_STOPIRQ 0x800 /* stop condition interrupt (slave) */
-#define CR_NAKRIRQ 0x400 /* NACK response interrupt (master) */
-#define CR_DRIRQ 0x200 /* rx interrupt (both) */
-#define CR_DTIRQ 0x100 /* tx interrupt (both) */
-#define CR_TBEN 0x80 /* tx enable (both) */
-#define CR_NAK 0x40 /* NACK (both) */
-#define CR_STOP 0x20 /* stop (master) */
-#define CR_START 0x10 /* start (master) */
-#define CR_GCEN 0x8 /* general call support (slave) */
-#define CR_SCLEN 0x4 /* enable clock out (master) */
-#define CR_I2CEN 0x2 /* enable I2C (both) */
-#define CR_I2CRST 0x1 /* reset I2C (both) */
-#define CR_ENABLE \
- (CR_ALIRQ | CR_NAKRIRQ | CR_DRIRQ | CR_DTIRQ | CR_SCLEN | CR_I2CEN)
-
-/*
- * status register
- */
-#define SR_CLRAL 0x400 /* clear arbitration lost */
-#define SR_CLRGC 0x200 /* clear general call */
-#define SR_CLRSAM 0x100 /* clear slave address match */
-#define SR_CLRSTOP 0x80 /* clear stop */
-#define SR_CLRNAKR 0x40 /* clear NACK respond */
-#define SR_DR 0x20 /* rx ready */
-#define SR_DT 0x10 /* tx done */
-#define SR_BB 0x8 /* bus busy */
-#define SR_BUSY 0x4 /* chip busy */
-#define SR_ACK 0x2 /* ACK/NACK received */
-#define SR_RW 0x1 /* set when master-rx or slave-tx mode */
-
-/*
- * clock division register
- */
-#define CDR_DIV(n) ((n) & 0x3ffff)
-
-/*
- * time & glitch suppression register
- */
-#define TGSR_GSR(n) (((n) & 0x7) << 10)
-#define TGSR_TSR(n) ((n) & 0x3ff)
-
-/*
- * bus monitor register
- */
-#define BMR_SCL 0x2 /* SCL is pull-up */
-#define BMR_SDA 0x1 /* SDA is pull-up */
-
-#endif /* __FTI2C010_H */
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 5700859..6ba255d 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -140,6 +140,7 @@
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
+ select SPL_SPI_FLASH_SUPPORT
---help---
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 12dbcd8..be2b611 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -725,9 +725,9 @@
* Initialize the global default MC portal
* And check that the MC firmware is responding portal commands:
*/
- root_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
+ root_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
if (!root_mc_io) {
- printf(" No memory: malloc() failed\n");
+ printf(" No memory: calloc() failed\n");
return -ENOMEM;
}
@@ -879,11 +879,12 @@
struct dpio_cfg dpio_cfg;
int err = 0;
- dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj));
+ dflt_dpio = (struct fsl_dpio_obj *)calloc(
+ sizeof(struct fsl_dpio_obj), 1);
if (!dflt_dpio) {
- printf("No memory: malloc() failed\n");
+ printf("No memory: calloc() failed\n");
err = -ENOMEM;
- goto err_malloc;
+ goto err_calloc;
}
dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL;
@@ -948,7 +949,7 @@
dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
err_create:
free(dflt_dpio);
-err_malloc:
+err_calloc:
return err;
}
@@ -1030,11 +1031,11 @@
goto err_create;
}
- dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
+ dflt_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
if (!dflt_mc_io) {
err = -ENOMEM;
- printf(" No memory: malloc() failed\n");
- goto err_malloc;
+ printf(" No memory: calloc() failed\n");
+ goto err_calloc;
}
child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset);
@@ -1059,7 +1060,7 @@
return 0;
err_child_open:
free(dflt_mc_io);
-err_malloc:
+err_calloc:
dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
root_dprc_handle, child_dprc_id);
err_create:
@@ -1110,11 +1111,12 @@
struct dpbp_attr dpbp_attr;
struct dpbp_cfg dpbp_cfg;
- dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
+ dflt_dpbp = (struct fsl_dpbp_obj *)calloc(
+ sizeof(struct fsl_dpbp_obj), 1);
if (!dflt_dpbp) {
- printf("No memory: malloc() failed\n");
+ printf("No memory: calloc() failed\n");
err = -ENOMEM;
- goto err_malloc;
+ goto err_calloc;
}
dpbp_cfg.options = 512;
@@ -1164,7 +1166,7 @@
dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
err_create:
-err_malloc:
+err_calloc:
return err;
}
@@ -1206,11 +1208,12 @@
struct dpni_extended_cfg dpni_extended_cfg;
struct dpni_cfg dpni_cfg;
- dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj));
+ dflt_dpni = (struct fsl_dpni_obj *)calloc(
+ sizeof(struct fsl_dpni_obj), 1);
if (!dflt_dpni) {
- printf("No memory: malloc() failed\n");
+ printf("No memory: calloc() failed\n");
err = -ENOMEM;
- goto err_malloc;
+ goto err_calloc;
}
memset(&dpni_extended_cfg, 0, sizeof(dpni_extended_cfg));
@@ -1272,7 +1275,7 @@
err_create:
err_prepare_extended_cfg:
free(dflt_dpni);
-err_malloc:
+err_calloc:
return err;
}
diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c
index 061935e..780a239 100644
--- a/drivers/net/ldpaa_eth/ls1088a.c
+++ b/drivers/net/ldpaa_eth/ls1088a.c
@@ -99,7 +99,7 @@
ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
if (!ec)
- wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII);
+ wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII_ID);
#endif
#ifdef CONFIG_SYS_FSL_EC2
@@ -108,7 +108,7 @@
ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
if (!ec)
- wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII);
+ wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII_ID);
#endif
}
#endif
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 22fc83d..927bbd7 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -184,6 +184,19 @@
trans->bytesin -= bytes;
}
+static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
+{
+ if (plat->ich_version == ICHV_7) {
+ struct ich7_spi_regs *ich7_spi = sbase;
+
+ setbits_le16(&ich7_spi->spis, SPIS_LOCK);
+ } else if (plat->ich_version == ICHV_9) {
+ struct ich9_spi_regs *ich9_spi = sbase;
+
+ setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
+ }
+}
+
static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
{
int lock = 0;
@@ -592,6 +605,12 @@
return ret;
}
+ /* Lock down SPI controller settings if required */
+ if (plat->lockdown) {
+ ich_spi_config_opcode(dev);
+ spi_lock_down(plat, priv->base);
+ }
+
priv->cur_speed = priv->max_speed;
return 0;
@@ -662,6 +681,9 @@
plat->ich_version = ICHV_9;
}
+ plat->lockdown = fdtdec_get_bool(gd->fdt_blob, node,
+ "intel,spi-lock-down");
+
return ret;
}
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index c867c57..06b7fb9 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -174,6 +174,7 @@
struct ich_spi_platdata {
enum ich_version ich_version; /* Controller version, 7 or 9 */
+ bool lockdown; /* lock down controller settings? */
};
struct ich_spi_priv {
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index f5f19ed..5264475 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -71,6 +71,12 @@
Select the DRA7XX xHCI USB index.
Current supported values: 0, 1.
+config USB_XHCI_FSL
+ bool "Support for NXP Layerscape on-chip xHCI USB controller"
+ default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2
+ depends on !SPL_NO_USB
+ help
+ Enables support for the on-chip xHCI controller on NXP Layerscape SoCs.
endif # USB_XHCI_HCD
config USB_EHCI_HCD
diff --git a/env/Kconfig b/env/Kconfig
index 02cb7cb..8c9d800 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -16,6 +16,7 @@
default ENV_IS_IN_FLASH if SH && !CPU_SH4
default ENV_IS_IN_SPI_FLASH if ARMADA_XP
default ENV_IS_IN_SPI_FLASH if INTEL_BAYTRAIL
+ default ENV_IS_IN_SPI_FLASH if INTEL_BRASWELL
default ENV_IS_IN_SPI_FLASH if INTEL_BROADWELL
default ENV_IS_IN_SPI_FLASH if NORTHBRIDGE_INTEL_IVYBRIDGE
default ENV_IS_IN_SPI_FLASH if INTEL_QUARK
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index d6982d3..7e805ec 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -109,7 +109,6 @@
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_ENABLE_36BIT_PHYS
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 13edd0a..adb4a18 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -205,7 +205,6 @@
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_ENABLE_36BIT_PHYS
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
index 2eeb3d1..32439f5 100644
--- a/include/configs/am335x_shc.h
+++ b/include/configs/am335x_shc.h
@@ -266,7 +266,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_NET_MULTI
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h
index ab3d40c..717ec80 100644
--- a/include/configs/ap_sh4a_4a.h
+++ b/include/configs/ap_sh4a_4a.h
@@ -12,7 +12,6 @@
#define CONFIG_CPU_SH7734 1
#define CONFIG_AP_SH4A_4A 1
#define CONFIG_400MHZ_MODE 1
-/* #define CONFIG_533MHZ_MODE 1 */
#define CONFIG_SYS_TEXT_BASE 0x8BFC0000
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 111a7dc..67115f9 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -72,7 +72,6 @@
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP 2
#define CONFIG_PMECC_SECTOR_SIZE 512
-#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h
index 3b65416..03700b0 100644
--- a/include/configs/bg0900.h
+++ b/include/configs/bg0900.h
@@ -27,7 +27,6 @@
/* SPI */
#ifdef CONFIG_CMD_SPI
#define CONFIG_DEFAULT_SPI_BUS 2
-#define CONFIG_DEFAULT_SPI_CS 0
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
/* SPI FLASH */
diff --git a/include/configs/blanche.h b/include/configs/blanche.h
index 2b18033..ce7c716 100755
--- a/include/configs/blanche.h
+++ b/include/configs/blanche.h
@@ -65,7 +65,6 @@
#undef CONFIG_CMD_SPI
#endif
-#define CONFIG_NET_MULTI
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 7012a95..a222491 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -50,7 +50,6 @@
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_NET_MULTI
#define CONFIG_PHY_ATHEROS
#define CONFIG_SYS_RX_ETH_BUFFER 64
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 13e7c71..1b20d85 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -370,7 +370,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_NET_MULTI
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
index c9584ad..7bd2c4a 100644
--- a/include/configs/etamin.h
+++ b/include/configs/etamin.h
@@ -120,7 +120,6 @@
-#define CONFIG_DFU_MTD
#undef COMMON_ENV_DFU_ARGS
#define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \
"setenv bootargs ${bootargs};" \
diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h
index 79e6d13..ae9ead5 100644
--- a/include/configs/exynos5420-common.h
+++ b/include/configs/exynos5420-common.h
@@ -43,11 +43,6 @@
#define CONFIG_LOWPOWER_FLAG 0x02020028
#define CONFIG_LOWPOWER_ADDR 0x0202002C
-/*
- * Number of CPUs available
- */
-#define CONFIG_CORE_COUNT 0x8
-
#define CONFIG_USB_XHCI_EXYNOS
#endif /* __CONFIG_EXYNOS5420_H */
diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
index 0aeec39..4e10471 100644
--- a/include/configs/exynos7420-common.h
+++ b/include/configs/exynos7420-common.h
@@ -43,9 +43,6 @@
#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
#define CPU_RELEASE_ADDR secondary_boot_addr
-/* Number of CPUs available */
-#define CONFIG_CORE_COUNT 0x8
-
/* select serial console configuration */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 77bd930..d2fa50a 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -32,7 +32,7 @@
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* CSU */
#define CONFIG_LAYERSCAPE_NS_ACCESS
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index 6b1ba57..efb4c00 100644
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h
@@ -31,16 +31,6 @@
"kernel_load=0x96000000\0" \
"kernel_size=0x2800000\0"
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index b3121d2..d150547 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -118,14 +118,6 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
-/*XHCI Support - enabled by default*/
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
@@ -146,7 +138,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_NET_MULTI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_MEMINFO
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index e9edcd2..7941170 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -19,15 +19,6 @@
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
/*
* I2C IO expander
@@ -62,7 +53,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_NET_MULTI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_MEMINFO
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 6366781..46bf55f 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -19,14 +19,6 @@
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-/* XHCI Support - enabled by default */
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index f3d3aa2..6669f2f 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -404,14 +404,6 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
-/*XHCI Support - enabled by default*/
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
/*
* Video
*/
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 852ff57..0f20e5e 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -44,14 +44,6 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
-/* XHCI Support - enabled by default */
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index a297134..a24d006 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -165,7 +165,6 @@
#define CONFIG_PCIE3 /* PCIE controller 3 */
#ifdef CONFIG_PCI
-#define CONFIG_NET_MULTI
#define CONFIG_PCI_SCAN_SHOW
#endif
#endif
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 5aadd92..8cc2abb 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -370,13 +370,6 @@
#endif
#endif
-/* USB */
-#define CONFIG_HAS_FSL_XHCI_USB
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#endif
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index f9843f5..b4b4d5e 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -284,15 +284,6 @@
#endif
#endif
-/* USB */
-#ifndef SPL_NO_USB
-#define CONFIG_HAS_FSL_XHCI_USB
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#endif
-#endif
-
/* SATA */
#ifndef SPL_NO_SATA
#define CONFIG_LIBATA
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 39bd1c3..586e9e9 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -136,13 +136,6 @@
#define CFG_LPUART_EN 0x2
#endif
-/* USB */
-#define CONFIG_HAS_FSL_XHCI_USB
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#endif
-
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 7bbd4ad..bb27dd0 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -209,15 +209,6 @@
#endif
#endif
-/* USB */
-#ifndef SPL_NO_USB
-#define CONFIG_HAS_FSL_XHCI_USB
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#endif
-#endif
-
/* SATA */
#ifndef SPL_NO_SATA
#define CONFIG_LIBATA
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 71d0e4e..c2e6fd2 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -20,7 +20,6 @@
#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 39f1345..478ddd0 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -12,7 +12,6 @@
#define CONFIG_DISPLAY_BOARDINFO_LATE
#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 54d6b51..f1968cc 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -435,13 +435,6 @@
#endif
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
#include <asm/fsl_secure_boot.h>
#endif /* __LS2_QDS_H */
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 9e9979e..48c3a53 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -333,13 +333,6 @@
#define CONFIG_MISC_INIT_R
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
#undef CONFIG_CMDLINE_EDITING
#include <config_distro_defaults.h>
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 4fcf480..b5ba6b4 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -72,7 +72,6 @@
/* SPI */
#ifdef CONFIG_CMD_SPI
#define CONFIG_DEFAULT_SPI_BUS 2
-#define CONFIG_DEFAULT_SPI_CS 0
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
/* SPI FLASH */
diff --git a/include/configs/novena.h b/include/configs/novena.h
index ac00975..3acc8c6 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -80,7 +80,6 @@
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_SPD_BUS_NUM 0
diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h
index 896c329..9c84acc 100644
--- a/include/configs/nsa310s.h
+++ b/include/configs/nsa310s.h
@@ -67,7 +67,6 @@
/* Ethernet driver configuration */
#ifdef CONFIG_CMD_NET
#define CONFIG_NETCONSOLE
-#define CONFIG_NET_MULTI
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 1
#define CONFIG_RESET_PHY_R
diff --git a/include/configs/nsim.h b/include/configs/nsim.h
index c086de6..c4775e5 100644
--- a/include/configs/nsim.h
+++ b/include/configs/nsim.h
@@ -30,7 +30,6 @@
*
*/
#define CONFIG_ARC_SERIAL
-#define CONFIG_ARC_UART_BASE 0xC0FC1000
/*
* Command line configuration
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index c89bd13..c7f7131 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -16,7 +16,6 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_4430SDP 1 /* working with SDP */
#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP
#include <configs/ti_omap4_common.h>
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 570c375..2fa280e 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -182,9 +182,6 @@
/* Disable CPSW SPL support so we fit within the 101KiB limit. */
#endif
-/* CPSW ethernet */
-#define CONFIG_NET_MULTI
-
/* Network */
#define CONFIG_PHY_RESET 1
#define CONFIG_PHY_NATSEMI
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index a31c6e2..1fef8b5 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -12,7 +12,6 @@
#define CONFIG_CPU_SH7734 1
#define CONFIG_R0P7734 1
#define CONFIG_400MHZ_MODE 1
-/* #define CONFIG_533MHZ_MODE 1 */
#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 9859f30..7ecaefb 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -170,7 +170,6 @@
/* Download menu - Samsung common */
#define CONFIG_LCD_MENU
-#define CONFIG_LCD_MENU_BOARD
/* Download menu - definitions for check keys */
#ifndef __ASSEMBLY__
diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h
index 5bf5731..77a12de 100644
--- a/include/configs/salvator-x.h
+++ b/include/configs/salvator-x.h
@@ -25,7 +25,6 @@
/* use to RPC(SPI Multi I/O Bus Controller) */
/* Ethernet RAVB */
-#define CONFIG_NET_MULTI
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 7b5417a..7281bda 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -94,7 +94,6 @@
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_MII
-#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
#endif
/*
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 5b33a3b..a34c349 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -180,7 +180,6 @@
/* Download menu - Samsung common */
#define CONFIG_LCD_MENU
-#define CONFIG_LCD_MENU_BOARD
/* Download menu - definitions for check keys */
#ifndef __ASSEMBLY__
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 95c011f..6b371f4 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -162,7 +162,6 @@
/* Download menu - Samsung common */
#define CONFIG_LCD_MENU
-#define CONFIG_LCD_MENU_BOARD
/* Download menu - definitions for check keys */
#ifndef __ASSEMBLY__
diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h
index cce2456..b54e63c 100644
--- a/include/configs/ulcb.h
+++ b/include/configs/ulcb.h
@@ -33,7 +33,6 @@
/* use to RPC(SPI Multi I/O Bus Controller) */
/* Ethernet RAVB */
-#define CONFIG_NET_MULTI
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 1399dfd..8526ba0 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -131,7 +131,6 @@
/* Ethernet driver */
#if defined(CONFIG_ZYNQ_GEM)
-# define CONFIG_NET_MULTI
# define CONFIG_MII
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHY_MARVELL
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index b433224..6c0981b 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -204,7 +204,6 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_FDT_FIXUP_PCI_IRQ 1
/*
* I2C
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index bd54089..a916afb 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -58,7 +58,7 @@
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_ARCH_LS2080A)
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index f627340..743b848 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1439,10 +1439,7 @@
/* Make sure that notification functions are not called anymore */
efi_tpl = TPL_HIGH_LEVEL;
-#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
- /* save any EFI variables that have been written: */
- env_save();
-#endif
+ /* XXX Should persist EFI variables here */
board_quiesce_devices();
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index a39d3d5..72c9030 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -873,7 +873,6 @@
CONFIG_HAS_FEC
CONFIG_HAS_FSL_DR_USB
CONFIG_HAS_FSL_MPH_USB
-CONFIG_HAS_FSL_XHCI_USB
CONFIG_HAS_POST
CONFIG_HCLK_FREQ
CONFIG_HDBOOT
@@ -5027,7 +5026,6 @@
CONFIG_USB_TUSB_OMAP_DMA
CONFIG_USB_ULPI_TIMEOUT
CONFIG_USB_XHCI_EXYNOS
-CONFIG_USB_XHCI_FSL
CONFIG_USB_XHCI_KEYSTONE
CONFIG_USB_XHCI_OMAP
CONFIG_USER_LOWLEVEL_INIT