Merge branch 'master' of git://www.denx.de/git/u-boot-coldfire
diff --git a/Makefile b/Makefile
index a2fd7f6..1f499c5 100644
--- a/Makefile
+++ b/Makefile
@@ -490,7 +490,7 @@
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
- $(MAKE) -C $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb
+ $(MAKE) $(build) $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
# Both images are created using mkimage (crc etc), so that the ROM
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
index 8e20073..a2a1f92 100644
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -18,7 +18,7 @@
else
ifdef CONFIG_SPL_BUILD
-COBJS-y += spl.o
+obj-y += spl.o
endif
obj-y += p1_p2_rdb_pc.o
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index c4b3c8f..010cd24 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -160,9 +160,25 @@
image_header_t *hdr =
(image_header_t *)fpga_data;
ulong data;
+ uint8_t comp;
+
+ comp = image_get_comp(hdr);
+ if (comp == IH_COMP_GZIP) {
+ ulong image_buf = image_get_data(hdr);
+ data = image_get_load(hdr);
+ ulong image_size = ~0UL;
- data = (ulong)image_get_data(hdr);
- data_size = image_get_data_size(hdr);
+ if (gunzip((void *)data, ~0UL,
+ (void *)image_buf,
+ &image_size) != 0) {
+ puts("GUNZIP: error\n");
+ return 1;
+ }
+ data_size = image_size;
+ } else {
+ data = (ulong)image_get_data(hdr);
+ data_size = image_get_data_size(hdr);
+ }
rc = fpga_load(dev, (void *)data, data_size);
}
break;
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 717c039..1effbad 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <asm/io.h>
#include <zynqpl.h>
+#include <asm/sizes.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
@@ -177,8 +178,14 @@
return FPGA_FAIL;
}
- if ((u32)buf_start & 0x3) {
- u32 *new_buf = (u32 *)((u32)buf & ~0x3);
+ if ((u32)buf < SZ_1M) {
+ printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
+ __func__, (u32)buf);
+ return FPGA_FAIL;
+ }
+
+ if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
+ u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
(u32)buf_start, (u32)new_buf, swap);
@@ -284,6 +291,10 @@
debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
debug("%s: Size = %zu\n", __func__, bsize);
+ /* flush(clean & invalidate) d-cache range buf */
+ flush_dcache_range((u32)buf, (u32)buf +
+ roundup(bsize, ARCH_DMA_MINALIGN));
+
/* Set up the transfer */
writel((u32)buf | 1, &devcfg_base->dma_src_addr);
writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);