Merge git://git.denx.de/u-boot-fsl-qoriq
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f2c35e3..de323bf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -122,6 +122,9 @@
config ARM_ERRATA_852423
bool
+config ARM_ERRATA_855873
+ bool
+
config CPU_ARM720T
bool
select SYS_CACHE_SHIFT_5
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 6c03dfb..cefbdfe 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,6 +1,7 @@
config ARCH_LS1012A
bool
select ARMV8_SET_SMPEN
+ select ARM_ERRATA_855873
select FSL_LSCH2
select SYS_FSL_DDR_BE
select SYS_FSL_MMDC
@@ -16,6 +17,7 @@
config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
+ select ARM_ERRATA_855873
select FSL_LSCH2
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
@@ -68,6 +70,7 @@
config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
+ select ARM_ERRATA_855873
select FSL_LSCH3
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
@@ -493,8 +496,7 @@
config SYS_MC_RSV_MEM_ALIGN
hex "Management Complex reserved memory alignment"
depends on RESV_RAM
- default 0x20000000 if ARCH_LS2080A
- default 0x70000000 if ARCH_LS1088A
+ default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A
help
Reserved memory needs to be aligned for MC to use. Default value
is 512MB.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 115c3fc..0cb6d4e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,8 +7,10 @@
obj-y += cpu.o
obj-y += lowlevel.o
obj-y += soc.o
+ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
+endif
obj-$(CONFIG_SPL) += spl.o
obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 00d2564..1e0030c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -30,6 +30,7 @@
#endif
#include <asm/arch/clock.h>
#include <hwconfig.h>
+#include <fsl_qbman.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -565,6 +566,9 @@
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_qbman_portals();
+#endif
return 0;
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 39ffe1a..80af318 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -26,6 +26,8 @@
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
#endif
+#include <asm/arch/speed.h>
+#include <fsl_qbman.h>
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
@@ -442,6 +444,13 @@
fdt_fixup_esdhc(blob, bd);
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ fdt_fixup_bportals(blob);
+ fdt_fixup_qportals(blob);
+ do_fixup_by_compat_u32(blob, "fsl,qman",
+ "clock-frequency", get_qman_freq(), 1);
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 2d7775e..5f23aad 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -155,7 +155,21 @@
sys_info->freq_localbus = sys_info->freq_systembus /
CONFIG_SYS_FSL_IFC_CLK_DIV;
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ sys_info->freq_qman = sys_info->freq_systembus;
+#endif
+}
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void)
+{
+ struct sys_info sys_info;
+
+ get_sys_info(&sys_info);
+
+ return sys_info.freq_qman;
}
+#endif
int get_clocks(void)
{
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index ae57c0e..dc4a437 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -341,6 +341,8 @@
#ifdef CONFIG_SYS_SATA2
ccsr_ahci = (void *)CONFIG_SYS_SATA2;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
#endif
@@ -348,6 +350,8 @@
#ifdef CONFIG_SYS_SATA1
ccsr_ahci = (void *)CONFIG_SYS_SATA1;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
@@ -368,6 +372,8 @@
/* Disable SATA ECC */
out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 03e744e..f385ed4 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -196,7 +196,10 @@
WEAK(apply_core_errata)
mov x29, lr /* Save LR */
- /* For now, we support Cortex-A57 specific errata only */
+ /* For now, we support Cortex-A53, Cortex-A57 specific errata */
+
+ /* Check if we are running on a Cortex-A53 core */
+ branch_if_a53_core x0, apply_a53_core_errata
/* Check if we are running on a Cortex-A57 core */
branch_if_a57_core x0, apply_a57_core_errata
@@ -204,6 +207,25 @@
mov lr, x29 /* Restore LR */
ret
+apply_a53_core_errata:
+
+#ifdef CONFIG_ARM_ERRATA_855873
+ mrs x0, midr_el1
+ tst x0, #(0xf << 20)
+ b.ne 0b
+
+ mrs x0, midr_el1
+ and x0, x0, #0xf
+ cmp x0, #3
+ b.lt 0b
+
+ mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
+ /* Enable data cache clean as data cache clean/invalidate */
+ orr x0, x0, #1 << 44
+ msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+#endif
+ b 0b
+
apply_a57_core_errata:
#ifdef CONFIG_ARM_ERRATA_828024
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2561ead..1ff5cac 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -23,6 +23,8 @@
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
+#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
@@ -41,6 +43,33 @@
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
+#define CONFIG_SYS_BMAN_NUM_PORTALS 10
+#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000
+#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
+ CONFIG_SYS_BMAN_MEM_BASE)
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000
+#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
+ CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
+#define CONFIG_SYS_QMAN_NUM_PORTALS 10
+#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
+#define CONFIG_SYS_QMAN_MEM_PHYS (0xf00000000ull + \
+ CONFIG_SYS_QMAN_MEM_BASE)
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
+#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
+ CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
+
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 09f64e7..1e65e4e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -88,6 +88,8 @@
/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
+#define AHCI_PORT_PHY2_CFG 0x28184d1f
+#define AHCI_PORT_PHY3_CFG 0x0e081509
#define AHCI_PORT_TRANS_CFG 0x08000029
#define AHCI_PORT_AXICC_CFG 0x3fffffff
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
index de795f6..e94fe8e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/speed.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
@@ -7,4 +7,7 @@
#ifndef _FSL_LAYERSCAPE_SPEED_H
#define _FSL_LAYERSCAPE_SPEED_H
void get_sys_info(struct sys_info *sys_info);
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void);
+#endif
#endif /* _FSL_LAYERSCAPE_SPEED_H */
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index ec6463d..3f30470 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -26,6 +26,14 @@
#define CONFIG_KEY_REVOCATION
+#if defined(CONFIG_FSL_LAYERSCAPE)
+/*
+ * For fsl layerscape based platforms, ESBC image Address in Header
+ * is 64 bit.
+ */
+#define CONFIG_ESBC_ADDR_64BIT
+#endif
+
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
@@ -42,14 +50,6 @@
#endif
-#if defined(CONFIG_FSL_LAYERSCAPE)
-/*
- * For fsl layerscape based platforms, ESBC image Address in Header
- * is 64 bit.
- */
-#define CONFIG_ESBC_ADDR_64BIT
-#endif
-
#ifdef CONFIG_ARCH_LS2080A
#define CONFIG_EXTRA_ENV \
"setenv fdt_high 0xa0000000;" \
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index ea46e49..b350bfe 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -26,6 +26,7 @@
#ifdef CONFIG_FSL_CORENET
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
+#include <fsl_qbman.h>
#endif
#include <fsl_usb.h>
#include <hwconfig.h>
@@ -804,7 +805,7 @@
#ifdef CONFIG_FSL_CORENET
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
+ setup_qbman_portals();
#endif
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 297dc4a..1159f06 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -15,6 +15,7 @@
#include <asm/io.h>
#include <asm/fsl_fdt.h>
#include <asm/fsl_portals.h>
+#include <fsl_qbman.h>
#include <hwconfig.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index 3777c6f..b298d11 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -14,75 +14,6 @@
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
-#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
-#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
-static void inhibit_portals(void __iomem *addr, int max_portals,
- int arch_max_portals, int portal_cinh_size)
-{
- uint32_t val;
- int i;
-
- /* arch_max_portals is the maximum based on memory size. This includes
- * the reserved memory in the SoC. max_portals the number of physical
- * portals in the SoC */
- if (max_portals > arch_max_portals) {
- printf("ERROR: portal config error\n");
- max_portals = arch_max_portals;
- }
-
- for (i = 0; i < max_portals; i++) {
- out_be32(addr, -1);
- val = in_be32(addr);
- if (!val) {
- printf("ERROR: Stopped after %d portals\n", i);
- goto done;
- }
- addr += portal_cinh_size;
- }
-#ifdef DEBUG
- printf("Cleared %d portals\n", i);
-#endif
-done:
-
- return;
-}
-
-void setup_portals(void)
-{
- ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
- void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
- CONFIG_SYS_BMAN_SWP_ISDR_REG;
- void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
- CONFIG_SYS_QMAN_SWP_ISDR_REG;
-#ifdef CONFIG_FSL_CORENET
- int i;
-
- for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
- u8 sdest = qp_info[i].sdest;
- u16 fliodn = qp_info[i].fliodn;
- u16 dliodn = qp_info[i].dliodn;
- u16 liodn_off = qp_info[i].liodn_offset;
-
- out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
- dliodn);
- /* set frame liodn */
- out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
- }
-#endif
-
- /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
-#ifdef CONFIG_PHYS_64BIT
- out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
-#endif
- out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-
- /* Change default state of BMan ISDR portals to all 1s */
- inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
- CONFIG_SYS_BMAN_SP_CINH_SIZE);
- inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
- CONFIG_SYS_QMAN_SP_CINH_SIZE);
-}
-
/* Update portal containter to match LAW setup of portal in phy map */
void fdt_portal(void *blob, const char *compat, const char *container,
u64 addr, u32 size)
@@ -142,215 +73,3 @@
printf("ERROR: %s isn't in a container. Not supported\n", compat);
}
-
-static int fdt_qportal(void *blob, int off, int id, char *name,
- enum fsl_dpaa_dev dev, int create)
-{
- int childoff, dev_off, ret = 0;
- uint32_t dev_handle;
-#ifdef CONFIG_FSL_CORENET
- int num;
- u32 liodns[2];
-#endif
-
- childoff = fdt_subnode_offset(blob, off, name);
- if (create) {
- char handle[64], *p;
-
- strncpy(handle, name, sizeof(handle));
- p = strchr(handle, '@');
- if (!strncmp(name, "fman", 4)) {
- *p = *(p + 1);
- p++;
- }
- *p = '\0';
-
- dev_off = fdt_path_offset(blob, handle);
- /* skip this node if alias is not found */
- if (dev_off == -FDT_ERR_BADPATH)
- return 0;
- if (dev_off < 0)
- return dev_off;
-
- if (childoff <= 0)
- childoff = fdt_add_subnode(blob, off, name);
-
- /* need to update the dev_off after adding a subnode */
- dev_off = fdt_path_offset(blob, handle);
- if (dev_off < 0)
- return dev_off;
-
- if (childoff > 0) {
- dev_handle = fdt_get_phandle(blob, dev_off);
- if (dev_handle <= 0) {
- dev_handle = fdt_alloc_phandle(blob);
- ret = fdt_set_phandle(blob, dev_off,
- dev_handle);
- if (ret < 0)
- return ret;
- }
-
- ret = fdt_setprop(blob, childoff, "dev-handle",
- &dev_handle, sizeof(dev_handle));
- if (ret < 0)
- return ret;
-
-#ifdef CONFIG_FSL_CORENET
- num = get_dpaa_liodn(dev, &liodns[0], id);
- ret = fdt_setprop(blob, childoff, "fsl,liodn",
- &liodns[0], sizeof(u32) * num);
- if (!strncmp(name, "pme", 3)) {
- u32 pme_rev1, pme_rev2;
- ccsr_pme_t *pme_regs =
- (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
-
- pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
- pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
- ret = fdt_setprop(blob, childoff,
- "fsl,pme-rev1", &pme_rev1, sizeof(u32));
- if (ret < 0)
- return ret;
- ret = fdt_setprop(blob, childoff,
- "fsl,pme-rev2", &pme_rev2, sizeof(u32));
- }
-#endif
- } else {
- return childoff;
- }
- } else {
- if (childoff > 0)
- ret = fdt_del_node(blob, childoff);
- }
-
- return ret;
-}
-
-void fdt_fixup_qportals(void *blob)
-{
- int off, err;
- unsigned int maj, min;
- unsigned int ip_cfg;
- ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
- u32 rev_1 = in_be32(&qman->ip_rev_1);
- u32 rev_2 = in_be32(&qman->ip_rev_2);
- char compat[64];
- int compat_len;
-
- maj = (rev_1 >> 8) & 0xff;
- min = rev_1 & 0xff;
- ip_cfg = rev_2 & 0xff;
-
- compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
- maj, min, ip_cfg) + 1;
- compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
-
- off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
- while (off != -FDT_ERR_NOTFOUND) {
-#ifdef CONFIG_FSL_CORENET
- u32 liodns[2];
-#endif
- const int *ci = fdt_getprop(blob, off, "cell-index", &err);
- int i;
-
- if (!ci)
- goto err;
-
- i = *ci;
-#ifdef CONFIG_SYS_DPAA_FMAN
- int j;
-#endif
-
- err = fdt_setprop(blob, off, "compatible", compat, compat_len);
- if (err < 0)
- goto err;
-
-#ifdef CONFIG_FSL_CORENET
- liodns[0] = qp_info[i].dliodn;
- liodns[1] = qp_info[i].fliodn;
-
- err = fdt_setprop(blob, off, "fsl,liodn",
- &liodns, sizeof(u32) * 2);
- if (err < 0)
- goto err;
-#endif
-
- i++;
-
- err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
- IS_E_PROCESSOR(get_svr()));
- if (err < 0)
- goto err;
-
-#ifdef CONFIG_FSL_CORENET
-#ifdef CONFIG_SYS_DPAA_PME
- err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
- if (err < 0)
- goto err;
-#else
- fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
-#endif
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
- char name[] = "fman@0";
-
- name[sizeof(name) - 2] = '0' + j;
- err = fdt_qportal(blob, off, i, name,
- FSL_HW_PORTAL_FMAN1 + j, 1);
- if (err < 0)
- goto err;
- }
-#endif
-#ifdef CONFIG_SYS_DPAA_RMAN
- err = fdt_qportal(blob, off, i, "rman@0",
- FSL_HW_PORTAL_RMAN, 1);
- if (err < 0)
- goto err;
-#endif
-
-err:
- if (err < 0) {
- printf("ERROR: unable to create props for %s: %s\n",
- fdt_get_name(blob, off, NULL), fdt_strerror(err));
- return;
- }
-
- off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal");
- }
-}
-
-void fdt_fixup_bportals(void *blob)
-{
- int off, err;
- unsigned int maj, min;
- unsigned int ip_cfg;
- ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
- u32 rev_1 = in_be32(&bman->ip_rev_1);
- u32 rev_2 = in_be32(&bman->ip_rev_2);
- char compat[64];
- int compat_len;
-
- maj = (rev_1 >> 8) & 0xff;
- min = rev_1 & 0xff;
-
- ip_cfg = rev_2 & 0xff;
-
- compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
- maj, min, ip_cfg) + 1;
- compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
-
- off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
- while (off != -FDT_ERR_NOTFOUND) {
- err = fdt_setprop(blob, off, "compatible", compat, compat_len);
- if (err < 0) {
- printf("ERROR: unable to create props for %s: %s\n",
- fdt_get_name(blob, off, NULL),
- fdt_strerror(err));
- return;
- }
-
- off = fdt_node_offset_by_compatible(blob, off, "fsl,bman-portal");
- }
-
-}
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 8c91e72..0ccb79c 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -8,6 +8,7 @@
#define _FSL_LIODN_H_
#include <asm/types.h>
+#include <fsl_qbman.h>
struct srio_liodn_id_table {
u32 id[2];
@@ -128,12 +129,14 @@
CONFIG_SYS_MPC85xx_TDM_OFFSET)
#define SET_QMAN_LIODN(liodn) \
- SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
+ SET_LIODN_ENTRY_1("fsl,qman", liodn, \
+ offsetof(struct ccsr_qman, liodnr) + \
CONFIG_SYS_FSL_QMAN_OFFSET, \
CONFIG_SYS_FSL_QMAN_OFFSET)
#define SET_BMAN_LIODN(liodn) \
- SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \
+ SET_LIODN_ENTRY_1("fsl,bman", liodn, \
+ offsetof(struct ccsr_bman, liodnr) + \
CONFIG_SYS_FSL_BMAN_OFFSET, \
CONFIG_SYS_FSL_BMAN_OFFSET)
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
index f13ba14..10d459e 100644
--- a/arch/powerpc/include/asm/fsl_portals.h
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -41,10 +41,6 @@
extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
u32 *liodns, int liodn_offset);
-extern void setup_portals(void);
-extern void fdt_fixup_qportals(void *blob);
-extern void fdt_fixup_bportals(void *blob);
-
extern struct qportal_info qp_info[];
extern void fdt_portal(void *blob, const char *compat, const char *container,
u64 addr, u32 size);
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index ee537f4..841f3d9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2702,66 +2702,6 @@
FSL_SRDS_B3_LANE_D = 23,
};
-typedef struct ccsr_qman {
-#ifdef CONFIG_SYS_FSL_QMAN_V3
- u8 res0[0x200];
-#else
- struct {
- u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
- u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
- u32 res;
- u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
- } qcsp[32];
-#endif
- /* Not actually reserved, but irrelevant to u-boot */
- u8 res[0xbf8 - 0x200];
- u32 ip_rev_1;
- u32 ip_rev_2;
- u32 fqd_bare; /* FQD Extended Base Addr Register */
- u32 fqd_bar; /* FQD Base Addr Register */
- u8 res1[0x8];
- u32 fqd_ar; /* FQD Attributes Register */
- u8 res2[0xc];
- u32 pfdr_bare; /* PFDR Extended Base Addr Register */
- u32 pfdr_bar; /* PFDR Base Addr Register */
- u8 res3[0x8];
- u32 pfdr_ar; /* PFDR Attributes Register */
- u8 res4[0x4c];
- u32 qcsp_bare; /* QCSP Extended Base Addr Register */
- u32 qcsp_bar; /* QCSP Base Addr Register */
- u8 res5[0x78];
- u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
- u32 srcidr; /* Source ID Register */
- u32 liodnr; /* LIODN Register */
- u8 res6[4];
- u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
- u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
- u8 res7[0x2e8];
-#ifdef CONFIG_SYS_FSL_QMAN_V3
- struct {
- u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
- u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
- u32 res;
- u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
- } qcsp[50];
-#endif
-} ccsr_qman_t;
-
-typedef struct ccsr_bman {
- /* Not actually reserved, but irrelevant to u-boot */
- u8 res[0xbf8];
- u32 ip_rev_1;
- u32 ip_rev_2;
- u32 fbpr_bare; /* FBPR Extended Base Addr Register */
- u32 fbpr_bar; /* FBPR Base Addr Register */
- u8 res1[0x8];
- u32 fbpr_ar; /* FBPR Attributes Register */
- u8 res2[0xf0];
- u32 srcidr; /* Source ID Register */
- u32 liodnr; /* LIODN Register */
- u8 res7[0x2f4];
-} ccsr_bman_t;
-
typedef struct ccsr_pme {
u8 res0[0x804];
u32 liodnbr; /* LIODN Base Register */
diff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS
index de3961d..371e5db 100644
--- a/board/freescale/ls1088a/MAINTAINERS
+++ b/board/freescale/ls1088a/MAINTAINERS
@@ -27,3 +27,8 @@
M: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
S: Maintained
F: configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+
+LS1088ARDB_SD_SECURE_BOOT BOARD
+M: Sumit Garg <sumit.garg@nxp.com>
+S: Maintained
+F: configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile
index bdcce9e..0e15031 100644
--- a/board/freescale/ls1088a/Makefile
+++ b/board/freescale/ls1088a/Makefile
@@ -5,6 +5,8 @@
#
obj-y += ls1088a.o
+obj-y += ddr.o
+ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o
-obj-y += ddr.o
+endif
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 96f183e..d12bcae 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -25,6 +25,13 @@
DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void)
+{
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+#ifdef CONFIG_FSL_QIXIS
unsigned long long get_qixis_addr(void)
{
unsigned long long addr;
@@ -42,7 +49,9 @@
return addr;
}
+#endif
+#if !defined(CONFIG_SPL_BUILD)
int checkboard(void)
{
char buf[64];
@@ -342,12 +351,6 @@
return 0;
}
-int board_early_init_f(void)
-{
- fsl_lsch3_early_init_f();
- return 0;
-}
-
void detail_board_ddr_info(void)
{
puts("\nDDR ");
@@ -451,3 +454,4 @@
return 0;
}
#endif
+#endif /* defined(CONFIG_SPL_BUILD) */
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index ccda824..a23a5d5 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -18,6 +18,7 @@
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
+#include <fsl_qbman.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <netdev.h>
@@ -81,7 +82,7 @@
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- setup_portals();
+ setup_qbman_portals();
return 0;
}
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index 8c9d6b1..d70b1d1 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -126,7 +126,7 @@
invalidate_icache();
set_liodns();
- setup_portals();
+ setup_qbman_portals();
ret = trigger_fpga_config();
if (ret)
diff --git a/board/varisys/cyrus/cyrus.c b/board/varisys/cyrus/cyrus.c
index 30f518a..f458627 100644
--- a/board/varisys/cyrus/cyrus.c
+++ b/board/varisys/cyrus/cyrus.c
@@ -69,7 +69,7 @@
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
+ setup_qbman_portals();
#endif
print_lbc_regs();
return 0;
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index b8e083c..4a09a5c 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -34,6 +34,7 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..a7466f1
--- /dev/null
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088ARDB=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SECURE_BOOT=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
+CONFIG_SD_BOOT=y
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
+CONFIG_SPL_CRYPTO_SUPPORT=y
+CONFIG_SPL_HASH_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ada7624..e8d598c 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -53,3 +53,4 @@
obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
+obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
new file mode 100644
index 0000000..3b3dd02
--- /dev/null
+++ b/drivers/misc/fsl_portals.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#ifdef CONFIG_PPC
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#endif
+#include <fsl_qbman.h>
+
+#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
+#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
+void setup_qbman_portals(void)
+{
+ void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
+ CONFIG_SYS_BMAN_SWP_ISDR_REG;
+ void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
+ CONFIG_SYS_QMAN_SWP_ISDR_REG;
+#ifdef CONFIG_PPC
+ struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+
+ /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
+#ifdef CONFIG_PHYS_64BIT
+ out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+#endif
+ out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
+#endif
+#ifdef CONFIG_FSL_CORENET
+ int i;
+
+ for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+ u8 sdest = qp_info[i].sdest;
+ u16 fliodn = qp_info[i].fliodn;
+ u16 dliodn = qp_info[i].dliodn;
+ u16 liodn_off = qp_info[i].liodn_offset;
+
+ out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
+ dliodn);
+ /* set frame liodn */
+ out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
+ }
+#endif
+
+ /* Change default state of BMan ISDR portals to all 1s */
+ inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
+ CONFIG_SYS_BMAN_SP_CINH_SIZE);
+ inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
+ CONFIG_SYS_QMAN_SP_CINH_SIZE);
+}
+
+void inhibit_portals(void __iomem *addr, int max_portals,
+ int arch_max_portals, int portal_cinh_size)
+{
+ u32 val;
+ int i;
+
+ /* arch_max_portals is the maximum based on memory size. This includes
+ * the reserved memory in the SoC. max_portals the number of physical
+ * portals in the SoC
+ */
+ if (max_portals > arch_max_portals) {
+ printf("ERROR: portal config error\n");
+ max_portals = arch_max_portals;
+ }
+
+ for (i = 0; i < max_portals; i++) {
+ out_be32(addr, -1);
+ val = in_be32(addr);
+ if (!val) {
+ printf("ERROR: Stopped after %d portals\n", i);
+ return;
+ }
+ addr += portal_cinh_size;
+ }
+ debug("Cleared %d portals\n", i);
+}
+
+#ifdef CONFIG_PPC
+static int fdt_qportal(void *blob, int off, int id, char *name,
+ enum fsl_dpaa_dev dev, int create)
+{
+ int childoff, dev_off, ret = 0;
+ u32 dev_handle;
+#ifdef CONFIG_FSL_CORENET
+ int num;
+ u32 liodns[2];
+#endif
+
+ childoff = fdt_subnode_offset(blob, off, name);
+ if (create) {
+ char handle[64], *p;
+
+ strncpy(handle, name, sizeof(handle));
+ p = strchr(handle, '@');
+ if (!strncmp(name, "fman", 4)) {
+ *p = *(p + 1);
+ p++;
+ }
+ *p = '\0';
+
+ dev_off = fdt_path_offset(blob, handle);
+ /* skip this node if alias is not found */
+ if (dev_off == -FDT_ERR_BADPATH)
+ return 0;
+ if (dev_off < 0)
+ return dev_off;
+
+ if (childoff <= 0)
+ childoff = fdt_add_subnode(blob, off, name);
+
+ /* need to update the dev_off after adding a subnode */
+ dev_off = fdt_path_offset(blob, handle);
+ if (dev_off < 0)
+ return dev_off;
+
+ if (childoff > 0) {
+ dev_handle = fdt_get_phandle(blob, dev_off);
+ if (dev_handle <= 0) {
+ dev_handle = fdt_alloc_phandle(blob);
+ ret = fdt_set_phandle(blob, dev_off,
+ dev_handle);
+ if (ret < 0)
+ return ret;
+ }
+
+ ret = fdt_setprop(blob, childoff, "dev-handle",
+ &dev_handle, sizeof(dev_handle));
+ if (ret < 0)
+ return ret;
+
+#ifdef CONFIG_FSL_CORENET
+ num = get_dpaa_liodn(dev, &liodns[0], id);
+ ret = fdt_setprop(blob, childoff, "fsl,liodn",
+ &liodns[0], sizeof(u32) * num);
+ if (!strncmp(name, "pme", 3)) {
+ u32 pme_rev1, pme_rev2;
+ ccsr_pme_t *pme_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+
+ pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
+ pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
+ ret = fdt_setprop(blob, childoff,
+ "fsl,pme-rev1", &pme_rev1,
+ sizeof(u32));
+ if (ret < 0)
+ return ret;
+ ret = fdt_setprop(blob, childoff,
+ "fsl,pme-rev2", &pme_rev2,
+ sizeof(u32));
+ }
+#endif
+ } else {
+ return childoff;
+ }
+ } else {
+ if (childoff > 0)
+ ret = fdt_del_node(blob, childoff);
+ }
+
+ return ret;
+}
+#endif /* CONFIG_PPC */
+
+void fdt_fixup_qportals(void *blob)
+{
+ int off, err;
+ unsigned int maj, min;
+ unsigned int ip_cfg;
+ struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+ u32 rev_1 = in_be32(&qman->ip_rev_1);
+ u32 rev_2 = in_be32(&qman->ip_rev_2);
+ char compat[64];
+ int compat_len;
+
+ maj = (rev_1 >> 8) & 0xff;
+ min = rev_1 & 0xff;
+ ip_cfg = rev_2 & 0xff;
+
+ compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
+ maj, min, ip_cfg) + 1;
+ compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
+ while (off != -FDT_ERR_NOTFOUND) {
+#ifdef CONFIG_PPC
+#ifdef CONFIG_FSL_CORENET
+ u32 liodns[2];
+#endif
+ const int *ci = fdt_getprop(blob, off, "cell-index", &err);
+ int i;
+
+ if (!ci)
+ goto err;
+
+ i = *ci;
+#ifdef CONFIG_SYS_DPAA_FMAN
+ int j;
+#endif
+
+#endif /* CONFIG_PPC */
+ err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+ if (err < 0)
+ goto err;
+#ifdef CONFIG_PPC
+#ifdef CONFIG_FSL_CORENET
+ liodns[0] = qp_info[i].dliodn;
+ liodns[1] = qp_info[i].fliodn;
+ err = fdt_setprop(blob, off, "fsl,liodn",
+ &liodns, sizeof(u32) * 2);
+ if (err < 0)
+ goto err;
+#endif
+
+ i++;
+
+ err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
+ IS_E_PROCESSOR(get_svr()));
+ if (err < 0)
+ goto err;
+
+#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_DPAA_PME
+ err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
+ if (err < 0)
+ goto err;
+#else
+ fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
+#endif
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
+ char name[] = "fman@0";
+
+ name[sizeof(name) - 2] = '0' + j;
+ err = fdt_qportal(blob, off, i, name,
+ FSL_HW_PORTAL_FMAN1 + j, 1);
+ if (err < 0)
+ goto err;
+ }
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+ err = fdt_qportal(blob, off, i, "rman@0",
+ FSL_HW_PORTAL_RMAN, 1);
+ if (err < 0)
+ goto err;
+#endif
+#endif /* CONFIG_PPC */
+
+err:
+ if (err < 0) {
+ printf("ERROR: unable to create props for %s: %s\n",
+ fdt_get_name(blob, off, NULL),
+ fdt_strerror(err));
+ return;
+ }
+
+ off = fdt_node_offset_by_compatible(blob, off,
+ "fsl,qman-portal");
+ }
+}
+
+void fdt_fixup_bportals(void *blob)
+{
+ int off, err;
+ unsigned int maj, min;
+ unsigned int ip_cfg;
+ struct ccsr_bman *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
+ u32 rev_1 = in_be32(&bman->ip_rev_1);
+ u32 rev_2 = in_be32(&bman->ip_rev_2);
+ char compat[64];
+ int compat_len;
+
+ maj = (rev_1 >> 8) & 0xff;
+ min = rev_1 & 0xff;
+
+ ip_cfg = rev_2 & 0xff;
+
+ compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
+ maj, min, ip_cfg) + 1;
+ compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
+ while (off != -FDT_ERR_NOTFOUND) {
+ err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+ if (err < 0) {
+ printf("ERROR: unable to create props for %s: %s\n",
+ fdt_get_name(blob, off, NULL),
+ fdt_strerror(err));
+ return;
+ }
+
+ off = fdt_node_offset_by_compatible(blob, off,
+ "fsl,bman-portal");
+ }
+}
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ee1cc3a..46b17b1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -373,4 +373,28 @@
The PHY does not have a RXERR line (RMII only).
(so program the FEC to ignore it).
+config SYS_DPAA_QBMAN
+ bool "Device tree fixup for QBMan on freescale SOCs"
+ depends on (ARM || PPC) && !SPL_BUILD
+ default y if ARCH_B4860 || \
+ ARCH_B4420 || \
+ ARCH_P1023 || \
+ ARCH_P2041 || \
+ ARCH_T1023 || \
+ ARCH_T1024 || \
+ ARCH_T1040 || \
+ ARCH_T1042 || \
+ ARCH_T2080 || \
+ ARCH_T2081 || \
+ ARCH_T4240 || \
+ ARCH_T4160 || \
+ ARCH_P4080 || \
+ ARCH_P3041 || \
+ ARCH_P5040 || \
+ ARCH_P5020 || \
+ ARCH_LS1043A || \
+ ARCH_LS1046A
+ help
+ QBman fixups to allow deep sleep in DPAA 1 SOCs
+
endif # NETDEVICES
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index b1b6725..25e6c1f 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -571,7 +571,6 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 25
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 17ae6cf..1863bec 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -270,7 +270,6 @@
#define CONFIG_LOADADDR 1000000
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 8e71fdf..6b9f366 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -437,7 +437,6 @@
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index dd3cd6e..2354dc8 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -641,7 +641,6 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 791c6ef..733e44f 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -648,7 +648,6 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index fb79b6a..e96d3a0 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -531,7 +531,6 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index ceb9daa..1231c1a 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -641,7 +641,6 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 43fcc6f..6fbac5f 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -534,7 +534,7 @@
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_FSL_PCIE_RESET
+#define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
@@ -578,13 +578,11 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 18
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index e1c57de..85bda94 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -522,7 +522,6 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 18
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 099e9e1..73e91bc 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -381,7 +381,6 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 50
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index ecf7f64..b63c38c 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -542,7 +542,6 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 50
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index de9bc53..0e9dae6 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -453,7 +453,6 @@
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 942fbe2..e413b51 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -316,7 +316,6 @@
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 6aa2b9d..a0c932a 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -296,7 +296,6 @@
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index e208f7d..5c2ad69 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -155,10 +155,6 @@
#endif
#endif
-#ifndef SPL_NO_QBMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
-#endif
-
/* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 6587296..e684884 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -7,6 +7,19 @@
#ifndef __LS1088_COMMON_H
#define __LS1088_COMMON_H
+/* SPL build */
+#ifdef CONFIG_SPL_BUILD
+#define SPL_NO_BOARDINFO
+#define SPL_NO_QIXIS
+#define SPL_NO_PCI
+#define SPL_NO_ENV
+#define SPL_NO_RTC
+#define SPL_NO_USB
+#define SPL_NO_SATA
+#define SPL_NO_QSPI
+#define SPL_NO_IFC
+#undef CONFIG_DISPLAY_CPUINFO
+#endif
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
@@ -74,8 +87,10 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
/* IFC */
#define CONFIG_FSL_IFC
+#endif
/*
* During booting, IFC is mapped at the region of 0x30000000.
@@ -172,6 +187,7 @@
/* #define CONFIG_DISPLAY_CPUINFO */
+#ifndef SPL_NO_ENV
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@@ -211,6 +227,7 @@
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
#endif
+#endif
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
@@ -219,7 +236,9 @@
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
+#ifndef SPL_NO_ENV
#define CONFIG_CMDLINE_EDITING 1
+#endif
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 64 /* max command args */
@@ -235,7 +254,20 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw u-boot image instead of fit image.
+ */
+#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN 0x100000
+#endif /* ifdef CONFIG_SECURE_BOOT */
+
#endif
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 1438bec..3c6c666 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -9,7 +9,9 @@
#include "ls1088a_common.h"
+#ifndef SPL_NO_BOARDINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
+#endif
#define CONFIG_MISC_INIT_R
@@ -29,7 +31,9 @@
#endif
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_QIXIS_I2C_ACCESS
+#endif
#define SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#endif
@@ -97,7 +101,11 @@
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#endif
#endif
+
+#ifndef SPL_NO_IFC
#define CONFIG_NAND_FSL_IFC
+#endif
+
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
@@ -139,7 +147,10 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#ifndef SPL_NO_QIXIS
#define CONFIG_FSL_QIXIS
+#endif
+
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 2
#define QIXIS_QMAP_MASK 0xe0
@@ -223,6 +234,8 @@
#define I2C_RETIMER_ADDR 0x18
#define I2C_MUX_CH_DEFAULT 0x8
#define I2C_MUX_CH5 0xD
+
+#ifndef SPL_NO_RTC
/*
* RTC configuration
*/
@@ -230,6 +243,7 @@
#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#define CONFIG_CMD_DATE
+#endif
/* EEPROM */
#define CONFIG_ID_EEPROM
@@ -240,12 +254,14 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#ifndef SPL_NO_QSPI
/* QSPI device */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_QSPI
#define FSL_QSPI_FLASH_SIZE (1 << 26)
#define FSL_QSPI_FLASH_NUM 2
#endif
+#endif
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
@@ -260,6 +276,7 @@
#define CONFIG_FSL_MEMAC
+#ifndef SPL_NO_ENV
/* Initial environment variables */
#if defined(CONFIG_QSPI_BOOT)
#define MC_INIT_CMD \
@@ -408,6 +425,7 @@
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#define CONFIG_PHY_GIGE
#endif
+#endif
/* MMC */
#ifdef CONFIG_MMC
@@ -415,6 +433,7 @@
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
+#ifndef SPL_NO_ENV
#undef CONFIG_CMDLINE_EDITING
#include <config_distro_defaults.h>
@@ -423,6 +442,7 @@
func(SCSI, scsi, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
+#endif
#include <asm/fsl_secure_boot.h>
diff --git a/include/fsl_qbman.h b/include/fsl_qbman.h
new file mode 100644
index 0000000..06262ec
--- /dev/null
+++ b/include/fsl_qbman.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_QBMAN_H__
+#define __FSL_QBMAN_H__
+void fdt_fixup_qportals(void *blob);
+void fdt_fixup_bportals(void *blob);
+void inhibit_portals(void __iomem *addr, int max_portals,
+ int arch_max_portals, int portal_cinh_size);
+void setup_qbman_portals(void);
+
+struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+ u8 res0[0x200];
+#else
+ struct {
+ u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
+ u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
+ u32 res;
+ u32 qcsp_dd_cfg; /* 0xc - SW Portal Dynamic Debug cfg */
+ } qcsp[32];
+#endif
+ /* Not actually reserved, but irrelevant to u-boot */
+ u8 res[0xbf8 - 0x200];
+ u32 ip_rev_1;
+ u32 ip_rev_2;
+ u32 fqd_bare; /* FQD Extended Base Addr Register */
+ u32 fqd_bar; /* FQD Base Addr Register */
+ u8 res1[0x8];
+ u32 fqd_ar; /* FQD Attributes Register */
+ u8 res2[0xc];
+ u32 pfdr_bare; /* PFDR Extended Base Addr Register */
+ u32 pfdr_bar; /* PFDR Base Addr Register */
+ u8 res3[0x8];
+ u32 pfdr_ar; /* PFDR Attributes Register */
+ u8 res4[0x4c];
+ u32 qcsp_bare; /* QCSP Extended Base Addr Register */
+ u32 qcsp_bar; /* QCSP Base Addr Register */
+ u8 res5[0x78];
+ u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
+ u32 srcidr; /* Source ID Register */
+ u32 liodnr; /* LIODN Register */
+ u8 res6[4];
+ u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
+ u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
+ u8 res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+ struct {
+ u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
+ u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
+ u32 res;
+ u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
+ } qcsp[50];
+#endif
+};
+
+struct ccsr_bman {
+ /* Not actually reserved, but irrelevant to u-boot */
+ u8 res[0xbf8];
+ u32 ip_rev_1;
+ u32 ip_rev_2;
+ u32 fbpr_bare; /* FBPR Extended Base Addr Register */
+ u32 fbpr_bar; /* FBPR Base Addr Register */
+ u8 res1[0x8];
+ u32 fbpr_ar; /* FBPR Attributes Register */
+ u8 res2[0xf0];
+ u32 srcidr; /* Source ID Register */
+ u32 liodnr; /* LIODN Register */
+ u8 res7[0x2f4];
+};
+
+#endif /* __FSL_QBMAN_H__ */