Merge tag 'u-boot-dfu-20241126' of https://source.denx.de/u-boot/custodians/u-boot-dfu
CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/23572
- Fastboot:
- handle unknown partition type as "raw"
- USB gadget:
- Fix ci_udc gadget driver for Tegra 2 devices by not using USBADRA
diff --git a/Kconfig b/Kconfig
index eb55f25..1f5b0f1 100644
--- a/Kconfig
+++ b/Kconfig
@@ -765,10 +765,15 @@
config NO_NET
bool "No networking support"
+ help
+ Do not include networking support
config NET
bool "Legacy U-Boot networking stack"
imply NETDEVICES
+ help
+ Include networking support with U-Boot's internal implementation of
+ the TCP/IP protocol stack.
config NET_LWIP
bool "Use lwIP for networking stack"
diff --git a/MAINTAINERS b/MAINTAINERS
index bd2c494..8c6c0c2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -860,6 +860,7 @@
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-zynqmp/
+F: drivers/bootcount/bootcount_zynqmp.c
F: drivers/clk/clk_zynqmp.c
F: driver/firmware/firmware-zynqmp.c
F: drivers/fpga/zynqpl.c
diff --git a/Makefile b/Makefile
index 2eaae42..22953bd 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2025
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 042282f..6ad59ae 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -190,7 +190,8 @@
cn9130-crb-A.dtb \
cn9130-crb-B.dtb \
ac5-98dx35xx-rd.dtb \
- ac5-98dx35xx-atl-x240.dtb
+ ac5-98dx35xx-atl-x240.dtb \
+ cn9130-atl-x250.dtb
endif
dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
diff --git a/arch/arm/dts/cn9130-atl-x250.dts b/arch/arm/dts/cn9130-atl-x250.dts
new file mode 100644
index 0000000..f2c82da
--- /dev/null
+++ b/arch/arm/dts/cn9130-atl-x250.dts
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Allied Telesis Labs
+ */
+
+#include "cn9130.dtsi"
+
+/ {
+ model = "Allied Telesis x250";
+ compatible = "alliedtelesis,x250",
+ "marvell,cn9130",
+ "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+
+ aliases {
+ serial0 = &uart0;
+ i2c0 = &cp0_i2c0;
+ i2c1 = &cp0_i2c1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ fault {
+ label = "fault:red";
+ gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ };
+};
+
+/*
+ * AP related configuration
+ */
+&ap_pinctl {
+ /* AP_MPP Pins:
+ * GPIO & NC [0-6,9-10,12]
+ * UART0 [11,19]
+ * UART1 [7,8]
+ * Note: The x250-28XTm PT1 units has the console port wired
+ * to the second uart pins (UART1). This was fixed in all
+ * subsequent models.
+ * Here we choose to configure the pin control for both
+ * uarts to cater for either unit.
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0 0 0 0 0 0 0 3 3 0
+ 0 3 0 0 0 0 0 0 0 3 >;
+};
+
+&ap_gpio0 {
+ pp-reset {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "pp-reset";
+ };
+};
+
+/*
+ * CP related configuration
+ */
+&cp0_pinctl {
+ /* MPP Bus:
+ * [0-1] DEV
+ * [2-8] GPIO
+ * [9] DEV
+ * [10-12] GPIO
+ * [13] ND_RB
+ * [14] GPIO
+ * [15-28] DEV
+ * [29-30] GPIO
+ * [31] DEV
+ * [32-34] GPIO
+ * [35-36] I2C1
+ * [37-38] I2C0
+ * [39-55] GPIO
+ * [56-60] SPI
+ * [61-62] GPIO
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 0 0 0 0 0 0 0 1
+ 0 0 0 2 0 1 1 1 1 1
+ 1 1 1 1 1 1 1 1 1 0
+ 0 1 0 0 0 2 2 2 2 0
+ 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 6 6 6 6
+ 6 0 0>;
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = <37 38>;
+ marvell,function = <2>;
+ };
+
+ cp0_i2c0_gpio_pins: cp0-i2c-gpio-pins-0 {
+ marvell,pins = <37 38>;
+ marvell,function = <0>;
+ };
+
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = <35 36>;
+ marvell,function = <2>;
+ };
+
+ cp0_nand_pins: cp0-nand-pins {
+ marvell,pins = <0 1 9 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31>;
+ marvell,function = <1>;
+ };
+
+ cp0_nand_rb: cp0-nand-rb {
+ marvell,pins = <13>;
+ marvell,function = <2>;
+ };
+
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = <56 57 58 59 60>;
+ marvell,function = <6>;
+ };
+};
+
+&cp0_comphy {
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <COMPHY_TYPE_IGNORE>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_IGNORE>;
+ };
+
+ phy3 {
+ phy-type = <COMPHY_TYPE_IGNORE>;
+ };
+
+ phy4 {
+ phy-type = <COMPHY_TYPE_IGNORE>;
+ };
+
+ phy5 {
+ phy-type = <COMPHY_TYPE_IGNORE>;
+ };
+};
+
+&cp0_pcie0 {
+ num-lanes = <1>;
+ /* non-prefetchable memory */
+ ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
+ status = "disabled";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ clock-frequency = <200000000>;
+};
+
+&cp0_utmi0 {
+ status = "okay";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+};
+
+&cp0_spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi0_pins>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ };
+};
+
+&cp0_nand {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-timing-mode = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@user {
+ reg = <0x00000000 0x10000000>;
+ label = "user";
+ };
+ };
+};
+
+&cp0_gpio0
+{
+ nand-protect {
+ gpio-hog;
+ gpios = <29 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "nand-protect";
+ };
+};
+
+&cp0_gpio1
+{
+ usb-en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-en";
+ };
+
+ phy-reset {
+ gpio-hog;
+ gpios = <21 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "phy-reset";
+ };
+};
+
+&cp0_i2c0 {
+ status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ pinctrl-1 = <&cp0_i2c0_gpio_pins>;
+ scl-gpios = <&cp0_gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&cp0_gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ mux@71 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,pca9546";
+ reg = <0x71>;
+ i2c-mux-idle-disconnect;
+ reset-gpios = <&cp0_gpio1 19 GPIO_ACTIVE_LOW>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hwmon@2e {
+ compatible = "adi,adt7476";
+ reg = <0x2e>;
+ };
+
+ rtc@68 {
+ compatible = "adi,max31331";
+ reg = <0x68>;
+ };
+ };
+ };
+};
+
+&cp0_i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c1_pins>;
+};
diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi
index 6875c6d..6d80d85 100644
--- a/arch/arm/dts/imx8mn-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-u-boot.dtsi
@@ -68,6 +68,11 @@
bootph-all;
};
+&osc_32k {
+ bootph-pre-ram;
+ bootph-all;
+};
+
#ifdef CONFIG_FSL_CAAM
&sec_jr0 {
bootph-pre-ram;
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
index 1af3f64..c4f7058 100644
--- a/arch/arm/dts/zynqmp-sc-revB.dts
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP Generic System Controller
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2024, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -80,7 +80,7 @@
pwm-fan {
compatible = "pwm-fan";
status = "okay";
- pwms = <&ttc0 2 40000 1>;
+ pwms = <&ttc0 2 40000 0>;
};
};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 8056f6b..8c43ade 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -387,6 +387,7 @@
&rtc {
status = "okay";
+ calibration = <0x7fff>;
};
&lpd_dma_chan1 {
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 192c120..974cbfe 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -73,11 +73,10 @@
* Call remove function of all devices with a removal flag set.
* This may be useful for last-stage operations, like cancelling
* of DMA operation or releasing device internal buffers.
+ * dm_remove_devices_active() ensures that vital devices are removed in
+ * a second round.
*/
- dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL);
-
- /* Remove all active vital devices next */
- dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+ dm_remove_devices_active();
cleanup_before_linux();
}
diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c
index 05390c1..0c5a82e 100644
--- a/arch/arm/mach-aspeed/ast2600/spl.c
+++ b/arch/arm/mach-aspeed/ast2600/spl.c
@@ -45,10 +45,10 @@
}
/* boot from UART has higher priority */
- if (scu->hwstrap2 & SCU_HWSTRAP2_BOOT_UART)
+ if (readl(&scu->hwstrap2) & SCU_HWSTRAP2_BOOT_UART)
return BOOT_DEVICE_UART;
- if (scu->hwstrap1 & SCU_HWSTRAP1_BOOT_EMMC)
+ if (readl(&scu->hwstrap1) & SCU_HWSTRAP1_BOOT_EMMC)
return BOOT_DEVICE_MMC1;
out:
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index c1a1a33..adb8169 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -215,9 +215,16 @@
bool "Support Allied Telesis x530"
select 88F6820
+config TARGET_X250
+ bool "Support Allied Telesis x250"
+ select ARMADA_8K
+ imply SCSI
+ imply BOOTSTD_DEFAULTS
+
config TARGET_X240
bool "Support Allied Telesis x240"
select ALLEYCAT_5
+ imply BOOTSTD_DEFAULTS
config TARGET_DB_XC3_24G4XG
bool "Support DB-XC3-24G4XG"
@@ -301,6 +308,7 @@
default "theadorable" if TARGET_THEADORABLE
default "a38x" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
+ default "x250" if TARGET_X250
default "x240" if TARGET_X240
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
@@ -325,6 +333,7 @@
default "turris_mox" if TARGET_TURRIS_MOX
default "controlcenterdc" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
+ default "x250" if TARGET_X250
default "x240" if TARGET_X240
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
@@ -349,6 +358,7 @@
default "CZ.NIC" if TARGET_TURRIS_MOX
default "gdsys" if TARGET_CONTROLCENTERDC
default "alliedtelesis" if TARGET_X530
+ default "alliedtelesis" if TARGET_X250
default "alliedtelesis" if TARGET_X240
default "mikrotik" if TARGET_CRS3XX_98DX3236
default "Marvell" if TARGET_MVEBU_ALLEYCAT5
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index 536960b..976c0e3 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -11,6 +11,9 @@
Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
will be used as the custom board directory.
+config SYS_MALLOC_LEN
+ default 0x10000000
+
config SYS_MALLOC_F_LEN
default 0x2000
@@ -20,6 +23,9 @@
config SPL_SYS_MALLOC_F_LEN
default 0x2000
+config SYS_MALLOC_LEN
+ default 0x800000
+
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default 0x80000000
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 7a4495c..343e825 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -3,4 +3,5 @@
# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
obj-y += board.o
+obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += capsule_update.o
obj-$(CONFIG_OF_LIVE) += of_fixup.o
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 2ab2ceb..75a880f 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -6,7 +6,9 @@
* Author: Caleb Connolly <caleb.connolly@linaro.org>
*/
-#include "time.h"
+#define LOG_CATEGORY LOGC_BOARD
+#define pr_fmt(fmt) "QCOM: " fmt
+
#include <asm/armv8/mmu.h>
#include <asm/gpio.h>
#include <asm/io.h>
@@ -29,6 +31,7 @@
#include <fdt_support.h>
#include <usb.h>
#include <sort.h>
+#include <time.h>
#include "qcom-priv.h"
@@ -448,6 +451,9 @@
configure_env();
qcom_late_init();
+ /* Configure the dfu_string for capsule updates */
+ qcom_configure_capsule_updates();
+
return 0;
}
diff --git a/arch/arm/mach-snapdragon/capsule_update.c b/arch/arm/mach-snapdragon/capsule_update.c
new file mode 100644
index 0000000..bf75a9a
--- /dev/null
+++ b/arch/arm/mach-snapdragon/capsule_update.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Capsule update support for Qualcomm boards.
+ *
+ * Copyright (c) 2024 Linaro Ltd.
+ * Author: Caleb Connolly <caleb.connolly@linaro.org>
+ */
+
+#define pr_fmt(fmt) "QCOM-FMP: " fmt
+
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <efi.h>
+#include <efi_loader.h>
+#include <malloc.h>
+#include <scsi.h>
+#include <part.h>
+#include <linux/err.h>
+
+#include "qcom-priv.h"
+
+/*
+ * NOTE: for now this implementation only supports the rb3gen2. Supporting other
+ * boards that boot in different ways (e.g. chainloaded from ABL) will require
+ * additional complexity to properly create the dfu string and fw_images array.
+ */
+
+/*
+ * To handle different variants like chainloaded U-Boot here we'll need to
+ * build the fw_images array dynamically at runtime. It looks like
+ * mach-rockchip is a good example for how to do this.
+ * Detecting which image types a board uses is TBD, hence for now we only
+ * support the one new board that runs U-Boot as its primary bootloader.
+ */
+struct efi_fw_image fw_images[] = {
+ {
+ /* U-Boot flashed to the uefi_X partition (e.g. rb3gen2) */
+ .fw_name = u"UBOOT_UEFI_PARTITION",
+ .image_index = 1,
+ },
+};
+
+struct efi_capsule_update_info update_info = {
+ /* Filled in by configure_dfu_string() */
+ .dfu_string = NULL,
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+/* LSB first */
+struct part_slot_status {
+ u16: 2;
+ u16 active : 1;
+ u16: 3;
+ u16 successful : 1;
+ u16 unbootable : 1;
+ u16 tries_remaining : 4;
+};
+
+static int find_boot_partition(const char *partname, struct blk_desc *blk_dev, char *name)
+{
+ int ret;
+ int partnum;
+ struct disk_partition info;
+ struct part_slot_status *slot_status;
+
+ for (partnum = 1;; partnum++) {
+ ret = part_get_info(blk_dev, partnum, &info);
+ if (ret)
+ return ret;
+
+ slot_status = (struct part_slot_status *)&info.type_flags;
+ log_io("%16s: Active: %1d, Successful: %1d, Unbootable: %1d, Tries left: %1d\n",
+ info.name, slot_status->active,
+ slot_status->successful, slot_status->unbootable,
+ slot_status->tries_remaining);
+ /*
+ * FIXME: eventually we'll want to find the active/inactive variant of the partition
+ * but on the rb3gen2 these values might all be 0
+ */
+ if (!strncmp(info.name, partname, strlen(partname))) {
+ log_debug("Found active %s partition: '%s'!\n", partname, info.name);
+ strlcpy(name, info.name, sizeof(info.name));
+ return partnum;
+ }
+ }
+
+ return -1;
+}
+
+/**
+ * qcom_configure_capsule_updates() - Configure the DFU string for capsule updates
+ *
+ * U-Boot is flashed to the boot partition on Qualcomm boards. In most cases there
+ * are two boot partitions, boot_a and boot_b. As we don't currently support doing
+ * full A/B updates, we only support updating the currently active boot partition.
+ *
+ * So we need to find the current slot suffix and the associated boot partition.
+ * We do this by looking for the boot partition that has the 'active' flag set
+ * in the GPT partition vendor attribute bits.
+ */
+void qcom_configure_capsule_updates(void)
+{
+ struct blk_desc *desc;
+ int ret = 0, partnum = -1, devnum;
+ static char dfu_string[32] = { 0 };
+ char name[32]; /* GPT partition name */
+ char *partname = "uefi_a";
+ struct udevice *dev = NULL;
+
+ if (IS_ENABLED(CONFIG_SCSI)) {
+ /* Scan for SCSI devices */
+ ret = scsi_scan(false);
+ if (ret) {
+ debug("Failed to scan SCSI devices: %d\n", ret);
+ return;
+ }
+ }
+
+ uclass_foreach_dev_probe(UCLASS_BLK, dev) {
+ if (device_get_uclass_id(dev) != UCLASS_BLK)
+ continue;
+
+ desc = dev_get_uclass_plat(dev);
+ if (!desc || desc->part_type == PART_TYPE_UNKNOWN)
+ continue;
+ devnum = desc->devnum;
+ partnum = find_boot_partition(partname, desc,
+ name);
+ if (partnum >= 0)
+ break;
+ }
+
+ if (partnum < 0) {
+ log_err("Failed to find boot partition\n");
+ return;
+ }
+
+ switch (desc->uclass_id) {
+ case UCLASS_SCSI:
+ snprintf(dfu_string, 32, "scsi %d=u-boot.bin part %d", devnum, partnum);
+ break;
+ case UCLASS_MMC:
+ snprintf(dfu_string, 32, "mmc 0=u-boot.bin part %d %d", devnum, partnum);
+ break;
+ default:
+ debug("Unsupported storage uclass: %d\n", desc->uclass_id);
+ return;
+ }
+ log_debug("boot partition is %s, DFU string: '%s'\n", name, dfu_string);
+
+ update_info.dfu_string = dfu_string;
+}
diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h
index 0a7ed5e..74d3919 100644
--- a/arch/arm/mach-snapdragon/qcom-priv.h
+++ b/arch/arm/mach-snapdragon/qcom-priv.h
@@ -3,6 +3,12 @@
#ifndef __QCOM_PRIV_H__
#define __QCOM_PRIV_H__
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+void qcom_configure_capsule_updates(void);
+#else
+void qcom_configure_capsule_updates(void) {}
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
#if CONFIG_IS_ENABLED(OF_LIVE)
/**
* qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index 49e449e..3c372bd 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -188,6 +188,8 @@
u32 gen_storage4; /* 0x40 */
u32 reserved1[1];
u32 gen_storage6; /* 0x48 */
+ u32 reserved2[3];
+ u32 pers_gen_storage2; /* 0x58 */
};
#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
index 6e6da80..448bc53 100644
--- a/arch/arm/mach-zynqmp/mp.c
+++ b/arch/arm/mach-zynqmp/mp.c
@@ -352,7 +352,7 @@
*/
flush_dcache_all();
- if (!strncmp(argv[1], "lockstep", 8)) {
+ if (!strcmp(argv[1], "lockstep") || !strcmp(argv[1], "0")) {
if (nr != ZYNQMP_CORE_RPU0) {
printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n");
return 1;
@@ -369,7 +369,7 @@
dcache_enable();
set_r5_halt_mode(nr, RELEASE, LOCK);
mark_r5_used(nr, LOCK);
- } else if (!strncmp(argv[1], "split", 5)) {
+ } else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) {
printf("R5 split mode\n");
set_r5_reset(nr, SPLIT);
set_r5_tcm_mode(SPLIT);
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 8250297..76c610b 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -57,7 +57,7 @@
* This may be useful for last-stage operations, like cancelling
* of DMA operation or releasing device internal buffers.
*/
- dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+ dm_remove_devices_active();
cleanup_before_linux();
}
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 55f5818..0f79a5d 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -49,7 +49,7 @@
* This may be useful for last-stage operations, like cancelling
* of DMA operation or releasing device internal buffers.
*/
- dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+ dm_remove_devices_active();
}
#if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
diff --git a/board/Marvell/sheevaplug/sheevaplug.env b/board/Marvell/sheevaplug/sheevaplug.env
new file mode 100644
index 0000000..bcd62db
--- /dev/null
+++ b/board/Marvell/sheevaplug/sheevaplug.env
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2024 Tony Dinh <mibodhi@gmail.com>
+ *
+ * Environment variables configurations
+ */
+
+kernel_addr_r=0x800000
+fdt_addr_r=0x2c00000
+ramdisk_addr_r=0x01100000
+scriptaddr=0x200000
+fdtfile=CONFIG_DEFAULT_DEVICE_TREE.dtb
+mtdparts=CONFIG_MTDPARTS_DEFAULT
+console=ttyS0,115200
+
+/* Standard Boot */
+bootcmd=
+ bootflow scan -lb
+failed=
+ echo CONFIG_SYS_BOARD boot failed - please check your image
diff --git a/board/alliedtelesis/x250/MAINTAINERS b/board/alliedtelesis/x250/MAINTAINERS
new file mode 100644
index 0000000..8a74dbc
--- /dev/null
+++ b/board/alliedtelesis/x250/MAINTAINERS
@@ -0,0 +1,7 @@
+X250 BOARD
+M: Chris Packham <chris.packham@alliedtelesis.co.nz>
+S: Maintained
+F: board/alliedtelesis/x250/
+F: arch/arm/dts/cn9130-atl-x250.dts
+F: include/configs/x250.h
+F: configs/x250_defconfig
diff --git a/board/alliedtelesis/x250/Makefile b/board/alliedtelesis/x250/Makefile
new file mode 100644
index 0000000..98e0cce
--- /dev/null
+++ b/board/alliedtelesis/x250/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Allied Telesis
+#
+
+obj-y += x250.o
diff --git a/board/alliedtelesis/x250/x250.c b/board/alliedtelesis/x250/x250.c
new file mode 100644
index 0000000..66c7826
--- /dev/null
+++ b/board/alliedtelesis/x250/x250.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <config.h>
+#include <asm/global_data.h>
+#include <linux/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DEVICE_BUS_SYNC_CTRL 0xF27004C8
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
+
+ /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
+ writel(0x00004001, DEVICE_BUS_SYNC_CTRL);
+
+ return 0;
+}
diff --git a/board/armltd/total_compute/MAINTAINERS b/board/armltd/total_compute/MAINTAINERS
index 3dc1cd1..92486f4 100644
--- a/board/armltd/total_compute/MAINTAINERS
+++ b/board/armltd/total_compute/MAINTAINERS
@@ -1,5 +1,5 @@
TOTAL_COMPUTE BOARD
-M: Usama Arif <usama.arif@arm.com>
+M: Ben Horgan <ben.horgan@arm.com>
S: Maintained
F: board/armltd/total_compute/
F: include/configs/total_compute.h
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 0ff8440..f7152d6 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -40,6 +40,15 @@
endif
+config XILINX_MINI
+ bool "Mini configuration"
+ depends on ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
+ help
+ This option disables features which are not needed for Mini U-Boot
+ configurations. Mini U-Boot is running in EL3 mostly on size contrained
+ systems. It's purpose is to program non volatile memories or running
+ initial memory tests.
+
config XILINX_OF_BOARD_DTB_ADDR
hex "Default DTB pickup address"
default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 38dd805..a12dccd 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -19,6 +19,7 @@
#include <i2c.h>
#include <linux/sizes.h>
#include <malloc.h>
+#include <memtop.h>
#include <mtd_node.h>
#include "board.h"
#include <dm.h>
@@ -676,3 +677,31 @@
return 0;
}
#endif
+
+#ifndef CONFIG_XILINX_MINI
+
+#ifndef MMU_SECTION_SIZE
+#define MMU_SECTION_SIZE (1 * 1024 * 1024)
+#endif
+
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+{
+ phys_size_t size;
+ phys_addr_t reg;
+
+ if (!total_size)
+ return gd->ram_top;
+
+ if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
+ panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
+
+ size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
+ reg = get_mem_top(gd->ram_base, gd->ram_size, size,
+ (void *)gd->fdt_blob);
+ if (!reg)
+ reg = gd->ram_top - size;
+
+ return reg + size;
+}
+
+#endif
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 3947467..fd5c6ce 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -12,12 +12,15 @@
#include <env_internal.h>
#include <log.h>
#include <malloc.h>
+#include <memalign.h>
+#include <mmc.h>
#include <time.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
+#include <linux/sizes.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <versalpl.h>
@@ -301,9 +304,11 @@
return 0;
}
+#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
}
+#endif
#if defined(CONFIG_ENV_IS_NOWHERE)
enum env_location env_get_location(enum env_operation op, int prio)
@@ -336,3 +341,41 @@
}
}
#endif
+
+#if defined(CONFIG_SET_DFU_ALT_INFO)
+
+#define DFU_ALT_BUF_LEN SZ_1K
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ int bootseq = 0, len = 0;
+ u32 bootmode = versal_get_bootmode();
+
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+
+ if (env_get("dfu_alt_info"))
+ return;
+
+ memset(buf, 0, sizeof(buf));
+
+ switch (bootmode) {
+ case EMMC_MODE:
+ case SD_MODE:
+ case SD1_LSHFT_MODE:
+ case SD_MODE1:
+ bootseq = mmc_get_env_dev();
+
+ len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot",
+ bootseq);
+
+ len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1",
+ bootseq);
+ break;
+ default:
+ return;
+ }
+
+ env_set("dfu_alt_info", buf);
+ puts("DFU alt info setting: done\n");
+}
+#endif
diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env
index 927f398..ff3a092 100644
--- a/board/xilinx/zynqmp/zynqmp_kria.env
+++ b/board/xilinx/zynqmp/zynqmp_kria.env
@@ -77,6 +77,7 @@
tpm_kd240=if test ${card1_rev} = A; then run tpm_reset; fi
board_setup=\
+rtc dev 0; \
zynqmp mmio_write 0xFFCA0010 0xfff 0; \
if test ${card1_name} = SCK-KV-G; then run kv260_setup; run tpm_kv260; fi;\
if test ${card1_name} = SCK-KR-G; then run kr260_setup; run tpm_reset; fi;\
diff --git a/boot/image-board.c b/boot/image-board.c
index 1757e58..b726bd6 100644
--- a/boot/image-board.c
+++ b/boot/image-board.c
@@ -624,9 +624,10 @@
void *buf;
int conf_noffset;
int fit_img_result;
- const char *uname, *name;
+ const char *uname, *name, *compatible;
int err;
int devnum = 0; /* TODO support multi fpga platforms */
+ int flags = 0;
if (!IS_ENABLED(CONFIG_FPGA))
return -ENOSYS;
@@ -674,20 +675,29 @@
return fit_img_result;
}
+ conf_noffset = fit_image_get_node(buf, uname);
+ compatible = fdt_getprop(buf, conf_noffset, "compatible", NULL);
+ if (!compatible) {
+ printf("'fpga' image without 'compatible' property\n");
+ } else {
+ if (CONFIG_IS_ENABLED(FPGA_LOAD_SECURE))
+ flags = fpga_compatible2flag(devnum, compatible);
+ }
+
if (!fpga_is_partial_data(devnum, img_len)) {
name = "full";
err = fpga_loadbitstream(devnum, (char *)img_data,
img_len, BIT_FULL);
if (err)
err = fpga_load(devnum, (const void *)img_data,
- img_len, BIT_FULL, 0);
+ img_len, BIT_FULL, flags);
} else {
name = "partial";
err = fpga_loadbitstream(devnum, (char *)img_data,
img_len, BIT_PARTIAL);
if (err)
err = fpga_load(devnum, (const void *)img_data,
- img_len, BIT_PARTIAL, 0);
+ img_len, BIT_PARTIAL, flags);
}
if (err)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index b2d0348..1d7ddb4 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -2016,7 +2016,9 @@
config CMD_CDP
bool "cdp"
help
- Perform CDP network configuration
+ The cdp command is used to announce the U-Boot device in the network
+ and to retrieve configuration data including the VLAN id using the
+ proprietary Cisco Discovery Protocol (CDP).
config CMD_SNTP
bool "sntp"
diff --git a/cmd/net-lwip.c b/cmd/net-lwip.c
index 6f5fc74..0fd446e 100644
--- a/cmd/net-lwip.c
+++ b/cmd/net-lwip.c
@@ -27,6 +27,9 @@
#endif
#if defined(CONFIG_CMD_WGET)
-U_BOOT_CMD(wget, 3, 1, do_wget, "boot image via network using HTTP protocol",
- "[loadAddress] URL");
+U_BOOT_CMD(wget, 3, 1, do_wget,
+ "boot image via network using HTTP/HTTPS protocol",
+ "[loadAddress] url\n"
+ "wget [loadAddress] [host:]path"
+);
#endif
diff --git a/common/Makefile b/common/Makefile
index 2ee5ef9..3599156 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -7,6 +7,7 @@
ifndef CONFIG_XPL_BUILD
obj-y += init/
obj-y += main.o
+obj-y += memtop.o
obj-y += exports.o
obj-y += cli_getch.o cli_simple.o cli_readline.o
obj-$(CONFIG_HUSH_OLD_PARSER) += cli_hush.o
diff --git a/common/memtop.c b/common/memtop.c
new file mode 100644
index 0000000..841d89e
--- /dev/null
+++ b/common/memtop.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#include <fdt_support.h>
+#include <fdtdec.h>
+#include <memtop.h>
+
+#include <asm/types.h>
+
+#define MEM_RGN_COUNT 16
+
+struct region {
+ phys_addr_t base;
+ phys_size_t size;
+};
+
+struct mem_region {
+ struct region rgn[MEM_RGN_COUNT];
+ uint count;
+};
+
+static void add_mem_region(struct mem_region *mem_rgn, phys_addr_t base,
+ phys_size_t size)
+{
+ long i;
+
+ for (i = mem_rgn->count; i >= 0; i--) {
+ if (i && base < mem_rgn->rgn[i - 1].base) {
+ mem_rgn->rgn[i] = mem_rgn->rgn[i - 1];
+ } else {
+ mem_rgn->rgn[i].base = base;
+ mem_rgn->rgn[i].size = size;
+ break;
+ }
+ }
+
+ mem_rgn->count++;
+}
+
+static void mem_regions_init(struct mem_region *mem)
+{
+ uint i;
+
+ mem->count = 0;
+ for (i = 0; i < MEM_RGN_COUNT; i++) {
+ mem->rgn[i].base = 0;
+ mem->rgn[i].size = 0;
+ }
+}
+
+static int fdt_add_reserved_regions(struct mem_region *free_mem,
+ struct mem_region *reserved_mem,
+ void *fdt_blob)
+{
+ u64 addr, size;
+ int i, total, ret;
+ int nodeoffset, subnode;
+ struct fdt_resource res;
+
+ if (fdt_check_header(fdt_blob) != 0)
+ return -1;
+
+ /* process memreserve sections */
+ total = fdt_num_mem_rsv(fdt_blob);
+ assert_noisy(total < MEM_RGN_COUNT);
+ for (i = 0; i < total; i++) {
+ if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
+ continue;
+ add_mem_region(reserved_mem, addr, size);
+ }
+
+ i = 0;
+ /* process reserved-memory */
+ nodeoffset = fdt_subnode_offset(fdt_blob, 0, "reserved-memory");
+ if (nodeoffset >= 0) {
+ subnode = fdt_first_subnode(fdt_blob, nodeoffset);
+ while (subnode >= 0) {
+ /* check if this subnode has a reg property */
+ ret = fdt_get_resource(fdt_blob, subnode, "reg", 0,
+ &res);
+ if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) {
+ addr = res.start;
+ size = res.end - res.start + 1;
+ assert_noisy(i < MEM_RGN_COUNT);
+ add_mem_region(reserved_mem, addr, size);
+ }
+
+ subnode = fdt_next_subnode(fdt_blob, subnode);
+ ++i;
+ }
+ }
+
+ return 0;
+}
+
+static long addrs_overlap(phys_addr_t base1, phys_size_t size1,
+ phys_addr_t base2, phys_size_t size2)
+{
+ const phys_addr_t base1_end = base1 + size1 - 1;
+ const phys_addr_t base2_end = base2 + size2 - 1;
+
+ return ((base1 <= base2_end) && (base2 <= base1_end));
+}
+
+static long region_overlap_check(struct mem_region *mem_rgn, phys_addr_t base,
+ phys_size_t size)
+{
+ unsigned long i;
+ struct region *rgn = mem_rgn->rgn;
+
+ for (i = 0; i < mem_rgn->count; i++) {
+ phys_addr_t rgnbase = rgn[i].base;
+ phys_size_t rgnsize = rgn[i].size;
+
+ if (addrs_overlap(base, size, rgnbase, rgnsize))
+ break;
+ }
+
+ return (i < mem_rgn->count) ? i : -1;
+}
+
+static int find_ram_top(struct mem_region *free_mem,
+ struct mem_region *reserved_mem, phys_size_t size)
+{
+ long i, rgn;
+ phys_addr_t base = 0;
+ phys_addr_t res_base;
+
+ for (i = free_mem->count - 1; i >= 0; i--) {
+ phys_addr_t rgnbase = free_mem->rgn[i].base;
+ phys_size_t rgnsize = free_mem->rgn[i].size;
+
+ if (rgnsize < size)
+ continue;
+
+ base = rgnbase + rgnsize - size;
+ while (base && rgnbase <= base) {
+ rgn = region_overlap_check(reserved_mem, base, size);
+ if (rgn < 0)
+ return base;
+
+ res_base = reserved_mem->rgn[rgn].base;
+ if (res_base < size)
+ break;
+ base = res_base - size;
+ }
+ }
+
+ return 0;
+}
+
+phys_addr_t get_mem_top(phys_addr_t ram_start, phys_size_t ram_size,
+ phys_size_t size, void *fdt)
+{
+ int i;
+ struct mem_region free_mem;
+ struct mem_region reserved_mem;
+
+ mem_regions_init(&free_mem);
+ mem_regions_init(&reserved_mem);
+
+ add_mem_region(&free_mem, ram_start, ram_size);
+
+ i = fdt_add_reserved_regions(&free_mem, &reserved_mem, fdt);
+ if (i < 0)
+ return 0;
+
+ return find_ram_top(&free_mem, &reserved_mem, size);
+}
diff --git a/common/usb_onboard_hub.c b/common/usb_onboard_hub.c
index 68a04ac..6f28036 100644
--- a/common/usb_onboard_hub.c
+++ b/common/usb_onboard_hub.c
@@ -7,37 +7,203 @@
* Mostly inspired by Linux kernel v6.1 onboard_usb_hub driver
*/
+#include <asm/gpio.h>
#include <dm.h>
#include <dm/device_compat.h>
+#include <i2c.h>
+#include <linux/delay.h>
#include <power/regulator.h>
+#define USB5744_COMMAND_ATTACH 0x0056
+#define USB5744_COMMAND_ATTACH_LSB 0xAA
+#define USB5744_CONFIG_REG_ACCESS 0x0037
+#define USB5744_CONFIG_REG_ACCESS_LSB 0x99
+
struct onboard_hub {
struct udevice *vdd;
+ struct gpio_desc *reset_gpio;
+};
+
+struct onboard_hub_data {
+ unsigned long reset_us;
+ unsigned long power_on_delay_us;
+ int (*init)(struct udevice *dev);
};
+static int usb5744_i2c_init(struct udevice *dev)
+{
+ /*
+ * Prevent the MCU from the putting the HUB in suspend mode through register write.
+ * The BYPASS_UDC_SUSPEND bit (Bit 3) of the RuntimeFlags2 register at address
+ * 0x411D controls this aspect of the hub.
+ * Format to write to hub registers via SMBus- 2D 00 00 05 00 01 41 1D 08
+ * Byte 0: Address of slave 2D
+ * Byte 1: Memory address 00
+ * Byte 2: Memory address 00
+ * Byte 3: Number of bytes to write to memory
+ * Byte 4: Write configuration register (00)
+ * Byte 5: Write the number of data bytes (01- 1 data byte)
+ * Byte 6: LSB of register address 0x41
+ * Byte 7: MSB of register address 0x1D
+ * Byte 8: value to be written to the register
+ */
+ u8 data_buf[8] = {0x0, 0x5, 0x0, 0x1, 0x41, 0x1D, 0x08};
+ u8 config_reg_access_buf = USB5744_CONFIG_REG_ACCESS;
+ struct udevice *i2c_bus = NULL, *i2c_dev;
+ struct ofnode_phandle_args phandle;
+ u8 buf = USB5744_COMMAND_ATTACH;
+ struct dm_i2c_chip *i2c_chip;
+ int ret, slave_addr;
+
+ ret = dev_read_phandle_with_args(dev, "i2c-bus", NULL, 0, 0, &phandle);
+ if (ret) {
+ dev_err(dev, "i2c-bus not specified\n");
+ return ret;
+ }
+
+ ret = device_get_global_by_ofnode(ofnode_get_parent(phandle.node), &i2c_bus);
+ if (ret) {
+ dev_err(dev, "Failed to get i2c node, err: %d\n", ret);
+ return ret;
+ }
+
+ ret = ofnode_read_u32(phandle.node, "reg", &slave_addr);
+ if (ret)
+ return ret;
+
+ ret = i2c_get_chip(i2c_bus, slave_addr, 1, &i2c_dev);
+ if (ret) {
+ dev_err(dev, "%s: can't find i2c chip device for addr 0x%x\n", __func__,
+ slave_addr);
+ return ret;
+ }
+
+ i2c_chip = dev_get_parent_plat(i2c_dev);
+ if (!i2c_chip) {
+ dev_err(dev, "parent platform data not found\n");
+ return -EINVAL;
+ }
+
+ i2c_chip->flags &= ~DM_I2C_CHIP_WR_ADDRESS;
+ /* SMBus write command */
+ ret = dm_i2c_write(i2c_dev, 0, (uint8_t *)&data_buf, 8);
+ if (ret) {
+ dev_err(dev, "data_buf i2c_write failed, err:%d\n", ret);
+ return ret;
+ }
+
+ /* Configuration register access command */
+ ret = dm_i2c_write(i2c_dev, USB5744_CONFIG_REG_ACCESS_LSB,
+ &config_reg_access_buf, 2);
+ if (ret) {
+ dev_err(dev, "config_reg_access i2c_write failed, err: %d\n", ret);
+ return ret;
+ }
+
+ /* USB Attach with SMBus */
+ ret = dm_i2c_write(i2c_dev, USB5744_COMMAND_ATTACH_LSB, &buf, 2);
+ if (ret) {
+ dev_err(dev, "usb_attach i2c_write failed, err: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int usb_onboard_hub_reset(struct udevice *dev)
+{
+ struct onboard_hub_data *data =
+ (struct onboard_hub_data *)dev_get_driver_data(dev);
+ struct onboard_hub *hub = dev_get_priv(dev);
+ int ret;
+
+ hub->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_IS_OUT);
+
+ /* property is optional, don't return error! */
+ if (!hub->reset_gpio)
+ return 0;
+
+ ret = dm_gpio_set_value(hub->reset_gpio, 1);
+ if (ret)
+ return ret;
+
+ udelay(data->reset_us);
+
+ ret = dm_gpio_set_value(hub->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ udelay(data->power_on_delay_us);
+
+ return 0;
+}
+
static int usb_onboard_hub_probe(struct udevice *dev)
{
+ struct onboard_hub_data *data =
+ (struct onboard_hub_data *)dev_get_driver_data(dev);
struct onboard_hub *hub = dev_get_priv(dev);
int ret;
ret = device_get_supply_regulator(dev, "vdd-supply", &hub->vdd);
- if (ret) {
+ if (ret && ret != -ENOENT) {
dev_err(dev, "can't get vdd-supply: %d\n", ret);
return ret;
}
- ret = regulator_set_enable_if_allowed(hub->vdd, true);
+ if (hub->vdd) {
+ ret = regulator_set_enable_if_allowed(hub->vdd, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "can't enable vdd-supply: %d\n", ret);
+ return ret;
+ }
+ }
+
+ ret = usb_onboard_hub_reset(dev);
if (ret)
- dev_err(dev, "can't enable vdd-supply: %d\n", ret);
+ return ret;
+ if (data->init) {
+ ret = data->init(dev);
+ if (ret) {
+ dev_err(dev, "onboard i2c init failed: %d\n", ret);
+ goto err;
+ }
+ }
+ return 0;
+err:
+ dm_gpio_set_value(hub->reset_gpio, 0);
return ret;
}
+static int usb_onboard_hub_bind(struct udevice *dev)
+{
+ struct ofnode_phandle_args phandle;
+ const void *fdt = gd->fdt_blob;
+ int ret, off;
+
+ ret = dev_read_phandle_with_args(dev, "peer-hub", NULL, 0, 0, &phandle);
+ if (ret) {
+ dev_err(dev, "peer-hub not specified\n");
+ return ret;
+ }
+
+ off = ofnode_to_offset(phandle.node);
+ ret = fdt_node_check_compatible(fdt, off, "usb424,5744");
+ if (!ret)
+ return 0;
+
+ return -ENODEV;
+}
+
static int usb_onboard_hub_remove(struct udevice *dev)
{
struct onboard_hub *hub = dev_get_priv(dev);
int ret;
+ if (hub->reset_gpio)
+ dm_gpio_free(hub->reset_gpio->dev, hub->reset_gpio);
+
ret = regulator_set_enable_if_allowed(hub->vdd, false);
if (ret)
dev_err(dev, "can't disable vdd-supply: %d\n", ret);
@@ -45,15 +211,34 @@
return ret;
}
+static const struct onboard_hub_data usb2514_data = {
+ .power_on_delay_us = 500,
+ .reset_us = 1,
+};
+
+static const struct onboard_hub_data usb5744_data = {
+ .init = usb5744_i2c_init,
+ .power_on_delay_us = 1000,
+ .reset_us = 5,
+};
+
static const struct udevice_id usb_onboard_hub_ids[] = {
/* Use generic usbVID,PID dt-bindings (usb-device.yaml) */
- { .compatible = "usb424,2514" }, /* USB2514B USB 2.0 */
- { }
+ { .compatible = "usb424,2514", /* USB2514B USB 2.0 */
+ .data = (ulong)&usb2514_data,
+ }, {
+ .compatible = "usb424,2744", /* USB2744 USB 2.0 */
+ .data = (ulong)&usb5744_data,
+ }, {
+ .compatible = "usb424,5744", /* USB5744 USB 3.0 */
+ .data = (ulong)&usb5744_data,
+ }
};
U_BOOT_DRIVER(usb_onboard_hub) = {
.name = "usb_onboard_hub",
.id = UCLASS_USB_HUB,
+ .bind = usb_onboard_hub_bind,
.probe = usb_onboard_hub_probe,
.remove = usb_onboard_hub_remove,
.of_match = usb_onboard_hub_ids,
diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig
index ea22541..4c902e4 100644
--- a/configs/amd_versal2_mini_defconfig
+++ b/configs/amd_versal2_mini_defconfig
@@ -15,6 +15,7 @@
CONFIG_SYS_LOAD_ADDR=0xBBF80000
CONFIG_DEBUG_UART_BASE=0xf1920000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
CONFIG_DEBUG_UART=y
diff --git a/configs/amd_versal2_mini_emmc_defconfig b/configs/amd_versal2_mini_emmc_defconfig
index 6d4b261..da3eebe 100644
--- a/configs/amd_versal2_mini_emmc_defconfig
+++ b/configs/amd_versal2_mini_emmc_defconfig
@@ -12,6 +12,7 @@
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_DEBUG_UART_BASE=0xf1920000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_XILINX_MINI=y
# CONFIG_PSCI_RESET is not set
CONFIG_DEBUG_UART=y
# CONFIG_EXPERT is not set
diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig
index 71bd667..d881cd4 100644
--- a/configs/amd_versal2_mini_ospi_defconfig
+++ b/configs/amd_versal2_mini_ospi_defconfig
@@ -15,6 +15,7 @@
CONFIG_SYS_LOAD_ADDR=0xBBF80000
CONFIG_DEBUG_UART_BASE=0xf1920000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
CONFIG_DEBUG_UART=y
diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig
index 3947604..eb63f06 100644
--- a/configs/amd_versal2_mini_qspi_defconfig
+++ b/configs/amd_versal2_mini_qspi_defconfig
@@ -15,6 +15,7 @@
CONFIG_SYS_LOAD_ADDR=0xBBF80000
CONFIG_DEBUG_UART_BASE=0xf1920000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
CONFIG_DEBUG_UART=y
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index 323e2f5..1ba02e0 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -33,7 +33,6 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)"
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index e35ca16..9411567 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -33,7 +33,6 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),-(root)"
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index 25e5be3..44e9b17 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -49,7 +49,6 @@
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_OVERWRITE=y
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index af758fc..add4a24 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -35,7 +35,6 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)"
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index 0fab4c3..540b918 100644
--- a/configs/guruplug_defconfig
+++ b/configs/guruplug_defconfig
@@ -35,7 +35,6 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896K(uboot),128K(uboot_env),-@1M(root)"
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index 9d195e1..6ee40e3 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -35,7 +35,6 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)"
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index a9d595c..2e618d8 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -47,7 +47,6 @@
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_JFFS2=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index 783879d..ca70ee9 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -34,7 +34,6 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xa0000@0x0(uboot),0x010000@0xa0000(env),0x500000@0xc0000(uimage),0x1a40000@0x5c0000(rootfs)"
@@ -66,5 +65,3 @@
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_NAND=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index f671835..9a42c39 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -30,7 +30,6 @@
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(root)"
diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig
index c4235ee..ab93163 100644
--- a/configs/nsa325_defconfig
+++ b/configs/nsa325_defconfig
@@ -42,7 +42,6 @@
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
# CONFIG_CMD_BLOCK_CACHE is not set
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x100000(uboot),0x80000(stock_uboot_env),0x80000(key_store),0x80000(info),0xA00000(etc),0xA00000(kernel_1),0x2FC0000(rootfs1),0xA00000(kernel_2),0x2FC0000(rootfs2)"
@@ -73,6 +72,4 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_NAND=y
CONFIG_UBIFS_SILENCE_MSG=y
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index 50103f3..50c9292 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -32,7 +32,6 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)"
diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig
index fb8036a..03b4fd9 100644
--- a/configs/pogo_v4_defconfig
+++ b/configs/pogo_v4_defconfig
@@ -41,7 +41,6 @@
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
# CONFIG_CMD_BLOCK_CACHE is not set
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:2M(u-boot),3M(uImage),3M(uImage2),8M(failsafe),112M(root)"
@@ -73,6 +72,4 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_NAND=y
CONFIG_UBIFS_SILENCE_MSG=y
diff --git a/configs/qcm6490_defconfig b/configs/qcm6490_defconfig
index 5ddc5ab..ba26924 100644
--- a/configs/qcm6490_defconfig
+++ b/configs/qcm6490_defconfig
@@ -19,3 +19,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs6490-rb3gen2"
+
+# Enable capsule updates
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index ea0dd3e..30f7b1c 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -21,12 +21,14 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
# CONFIG_CMD_BIND is not set
CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -34,6 +36,7 @@
CONFIG_CMD_USB=y
CONFIG_CMD_CAT=y
CONFIG_CMD_BMP=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_LOG=y
CONFIG_OF_LIVE=y
@@ -52,6 +55,9 @@
CONFIG_CLK_QCOM_SM8550=y
CONFIG_CLK_QCOM_SM8650=y
CONFIG_CLK_QCOM_SC7280=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SCSI=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x200000
CONFIG_MSM_GPIO=y
CONFIG_QCOM_PMIC_GPIO=y
CONFIG_DM_I2C=y
@@ -77,10 +83,12 @@
CONFIG_DWC_ETH_QOS_QCOM=y
CONFIG_RGMII=y
CONFIG_PHY=y
+CONFIG_PHY_QCOM_QMP_UFS=y
CONFIG_PHY_QCOM_QUSB2=y
CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y
CONFIG_PHY_QCOM_SNPS_EUSB2=y
CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
CONFIG_PINCTRL_QCOM_APQ8016=y
CONFIG_PINCTRL_QCOM_APQ8096=y
CONFIG_PINCTRL_QCOM_QCM2290=y
@@ -114,6 +122,7 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_UFS=y
+CONFIG_QCOM_UFS=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_FONT_8X16 is not set
CONFIG_VIDEO_FONT_16X32=y
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index 9ac40b9..a7f6c73 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -16,16 +16,14 @@
CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-sheevaplug"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
+CONFIG_LTO=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=524288
+CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
@@ -35,19 +33,10 @@
CONFIG_CMD_NAND=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
-CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
@@ -68,6 +57,5 @@
CONFIG_RTC_MV=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
CONFIG_BZIP2=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 1c70d1d..20f89ae 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -32,6 +32,7 @@
CONFIG_RISCV_SMODE=y
# CONFIG_OF_BOARD_FIXUP is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_FIT=y
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_BOOTSTAGE=y
diff --git a/configs/x240_defconfig b/configs/x240_defconfig
index f930d28..ff64916 100644
--- a/configs/x240_defconfig
+++ b/configs/x240_defconfig
@@ -27,16 +27,12 @@
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_IPV6=y
CONFIG_CLK=y
CONFIG_CLK_MVEBU=y
CONFIG_GPIO_HOG=y
@@ -74,7 +70,6 @@
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
@@ -83,3 +78,4 @@
CONFIG_USB_ETHER_SMSC95XX=y
# CONFIG_FAT_WRITE is not set
# CONFIG_SMBIOS is not set
+# CONFIG_TOOLS_MKEFICAPSULE is not set
diff --git a/configs/x250_defconfig b/configs/x250_defconfig
new file mode 100644
index 0000000..dffe85b
--- /dev/null
+++ b/configs/x250_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_TEXT_BASE=0x00000000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
+CONFIG_TARGET_X250=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xf80000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="cn9130-atl-x250"
+CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
+CONFIG_USE_PREBOOT=y
+CONFIG_SPL_SILENT_CONSOLE=y
+CONFIG_TPL_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_UBI=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ARP_TIMEOUT=200
+CONFIG_NET_RETRY_COUNT=50
+CONFIG_IPV6=y
+CONFIG_SYS_64BIT_LBA=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+# CONFIG_INPUT is not set
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_MVPP2=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_PHY=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_DS1307=y
+CONFIG_RTC_MAX313XX=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+# CONFIG_TOOLS_MKEFICAPSULE is not set
diff --git a/configs/x530_defconfig b/configs/x530_defconfig
index 89612be..815370c 100644
--- a/configs/x530_defconfig
+++ b/configs/x530_defconfig
@@ -65,6 +65,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
+CONFIG_IPV6=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
@@ -95,3 +96,4 @@
CONFIG_WDT=y
CONFIG_WDT_ORION=y
CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_TOOLS_MKEFICAPSULE is not set
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index 7388a78..ac3815b 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -12,6 +12,7 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="versal-mini"
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
CONFIG_SYS_MEMTEST_START=0x00000000
diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig
index a36e40d..21f241e 100644
--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@@ -12,6 +12,7 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0"
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig
index 3ae2115..6cb654c 100644
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@@ -12,6 +12,7 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1"
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index d0ea2b6..c2a5624 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -13,6 +13,7 @@
# CONFIG_DM_GPIO is not set
CONFIG_DEFAULT_DEVICE_TREE="versal-mini-ospi-single"
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_VERSAL_NO_DDR=y
# CONFIG_PSCI_RESET is not set
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index ef6eec0..4d23b35 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -11,6 +11,7 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="versal-mini-qspi-single"
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_VERSAL_NO_DDR=y
# CONFIG_PSCI_RESET is not set
diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig
index 1640dfa..e489f70 100644
--- a/configs/xilinx_versal_net_mini_defconfig
+++ b/configs/xilinx_versal_net_mini_defconfig
@@ -14,6 +14,7 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini"
CONFIG_SYS_LOAD_ADDR=0xBBF00000
+CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
CONFIG_SYS_MEMTEST_START=0x00000000
diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig
index 4c6159a..ab20156 100644
--- a/configs/xilinx_versal_net_mini_emmc_defconfig
+++ b/configs/xilinx_versal_net_mini_emmc_defconfig
@@ -10,6 +10,7 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-emmc"
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig
index 071eeb8..f5864b5 100644
--- a/configs/xilinx_versal_net_mini_ospi_defconfig
+++ b/configs/xilinx_versal_net_mini_ospi_defconfig
@@ -13,6 +13,7 @@
# CONFIG_DM_GPIO is not set
CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single"
CONFIG_SYS_LOAD_ADDR=0xBBF80000
+CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
CONFIG_LTO=y
diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig
index 227c45d..8453be5 100644
--- a/configs/xilinx_versal_net_mini_qspi_defconfig
+++ b/configs/xilinx_versal_net_mini_qspi_defconfig
@@ -11,6 +11,7 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single"
CONFIG_SYS_LOAD_ADDR=0xBBF80000
+CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
CONFIG_LTO=y
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index a9320de..30d79ab 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -133,6 +133,7 @@
CONFIG_CADENCE_OSPI_VERSAL=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
CONFIG_TPM2_TIS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index f220cc0..c8f166c 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -4,6 +4,7 @@
CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
CONFIG_ARCH_VERSAL=y
CONFIG_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x100000
CONFIG_NR_DRAM_BANKS=36
CONFIG_SF_DEFAULT_SPEED=30000000
@@ -18,6 +19,10 @@
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_REMAKE_ELF=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_EFI_HTTP_BOOT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -76,6 +81,7 @@
CONFIG_SIMPLE_PM_BUS=y
CONFIG_CLK_VERSAL=y
CONFIG_DFU_TIMEOUT=y
+CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000
CONFIG_ARM_FFA_TRANSPORT=y
@@ -99,11 +105,14 @@
CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
@@ -136,6 +145,9 @@
CONFIG_CADENCE_OSPI_VERSAL=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
CONFIG_TPM2_TIS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index e00b386..ed3d101 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -146,6 +146,7 @@
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQ_QSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index 5757a0c..e5ffc70 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -187,7 +187,6 @@
CONFIG_PWM_CADENCE_TTC=y
CONFIG_RESET_ZYNQMP=y
CONFIG_DM_RTC=y
-CONFIG_RTC_EMULATION=y
CONFIG_RTC_ZYNQMP=y
CONFIG_SCSI=y
CONFIG_ARM_DCC=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index 7aab69c..b58cf8a 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini"
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index c56b1e83..f47880b 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -15,6 +15,7 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SPL=y
+CONFIG_XILINX_MINI=y
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index a8dbf00..fc0070a 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -15,6 +15,7 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SPL=y
+CONFIG_XILINX_MINI=y
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index ba8f02c..6a7541f 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -10,6 +10,7 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index a8a0055..3643cae 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -10,6 +10,7 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index c08b10c..a60403d 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -15,6 +15,7 @@
CONFIG_SPL=y
# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_ZYNQMP_NO_DDR=y
# CONFIG_PSCI_RESET is not set
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index f3d83a2..310efdf 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -210,6 +210,7 @@
CONFIG_SPI=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_POWEROFF=y
CONFIG_SYSRESET_PSCI=y
diff --git a/disk/part_efi.c b/disk/part_efi.c
index bdcfcba..932d058 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -292,6 +292,7 @@
print_efiname(&gpt_pte[part - 1]));
strcpy((char *)info->type, "U-Boot");
info->bootable = get_bootable(&gpt_pte[part - 1]);
+ info->type_flags = gpt_pte[part - 1].attributes.fields.type_guid_specific;
if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) {
uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b,
(char *)disk_partition_uuid(info),
diff --git a/doc/README.TPL b/doc/README.TPL
deleted file mode 100644
index 95b466e..0000000
--- a/doc/README.TPL
+++ /dev/null
@@ -1,49 +0,0 @@
-Generic TPL framework
-=====================
-
-Overview
---------
-
-TPL---Third Program Loader.
-
-Due to the SPL on some boards(powerpc mpc85xx) has a size limit and cannot
-be compatible with all the external device(e.g. DDR). So add a tertiary
-program loader (TPL) to enable a loader stub loaded by the code from the
-SPL. It loads the final uboot image into DDR, then jump to it to begin
-execution. Now, only the powerpc mpc85xx has this requirement and will
-implemente it.
-
-Keep consistent with SPL, with this framework almost all source files for a
-board can be reused. No code duplication or symlinking is necessary anymore.
-
-How it works
-------------
-
-There has been a directory $(srctree)/spl which contains only a Makefile. The
-Makefile is shared by SPL and TPL.
-
-The object files are built separately for SPL/TPL and placed in the
-directory spl/tpl. The final binaries which are generated are
-u-boot-{spl|tpl}, u-boot-{spl|tpl}.bin and u-boot-{spl|tpl}.map.
-
-During the TPL build a variable named CONFIG_TPL_BUILD is exported in the
-make environment and also appended to CPPFLAGS with -DCONFIG_TPL_BUILD.
-
-The SPL options are shared by SPL and TPL, the board config file should
-determine which SPL options to choose based on whether CONFIG_TPL_BUILD
-is set. Source files can be compiled for TPL with options chosen in the
-board config file.
-
-TPL use a small device tree (u-boot-tpl.dtb), containing only the nodes with
-the pre-relocation properties: 'bootph-all' and 'bootph-pre-sram'
-(see doc/develop/spl.rst for details).
-
-For example:
-
-spl/Makefile:
-LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o
-
-CONFIG_SPL_LIBCOMMON_SUPPORT is defined in board config file:
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#endif
diff --git a/doc/README.kconfig b/doc/README.kconfig
deleted file mode 100644
index 808cf56..0000000
--- a/doc/README.kconfig
+++ /dev/null
@@ -1,151 +0,0 @@
-Kconfig in U-Boot
-=================
-
-This document describes the configuration infrastructure of U-Boot.
-
-The conventional configuration was replaced by Kconfig at v2014.10-rc1 release.
-
-
-Language Specification
-----------------------
-
-Kconfig originates in Linux Kernel.
-See the file "Documentation/kbuild/kconfig*.txt" in your Linux Kernel
-source directory for a basic specification of Kconfig.
-
-
-Difference from Linux's Kconfig
--------------------------------
-
-Here are some worth-mentioning configuration targets.
-
-- silentoldconfig
-
- This target updates .config, include/generated/autoconf.h and
- include/configs/* as in Linux. In U-Boot, it also does the following
- for the compatibility with the old configuration system:
-
- * create a symbolic link "arch/${ARCH}/include/asm/arch" pointing to
- the SoC/CPU specific header directory
- * create include/config.h
- * create include/autoconf.mk
- * create spl/include/autoconf.mk (SPL and TPL only)
- * create tpl/include/autoconf.mk (TPL only)
-
- If we could completely switch to Kconfig in a long run
- (i.e. remove all the include/configs/*.h), those additional processings
- above would be removed.
-
-- defconfig
-
- In U-Boot, "make defconfig" is a shorthand of "make sandbox_defconfig"
-
-- <board>_defconfig
-
- Now it works as in Linux.
- The prefixes such as "+S:" in *_defconfig are deprecated.
- You can simply remove the prefixes. Do not add them for new boards.
-
-- <board>_config
-
- This does not exist in Linux's Kconfig.
- "make <board>_config" works the same as "make <board>_defconfig".
- Prior to Kconfig, in U-Boot, "make <board>_config" was used for the
- configuration. It is still supported for backward compatibility, so
- we do not need to update the distro recipes.
-
-
-The other configuration targets work as in Linux Kernel.
-
-
-Migration steps to Kconfig
---------------------------
-
-Prior to Kconfig, the C preprocessor based board configuration had been used
-in U-Boot.
-
-Although Kconfig was introduced and some configs have been moved to Kconfig,
-many of configs are still defined in C header files. It will take a very
-long term to move all of them to Kconfig. In the interim, the two different
-configuration infrastructures should coexist.
-The configuration files are generated by both Kconfig and the old preprocessor
-based configuration as follows:
-
-Configuration files for use in C sources
- - include/generated/autoconf.h (generated by Kconfig for Normal)
- - include/configs/<board>.h (exists for all boards)
-
-Configuration file for use in makefiles
- - include/config/auto.conf (generated by Kconfig)
- - include/autoconf.mk (generated by the old config for Normal)
- - spl/include/autoconfig.mk (generated by the old config for SPL)
- - tpl/include/autoconfig.mk (generated by the old config for TPL)
-
-When adding a new CONFIG macro, it is highly recommended to add it to Kconfig
-rather than to a header file.
-
-
-Conversion from boards.cfg to Kconfig
--------------------------------------
-
-Prior to Kconfig, boards.cfg was a primary database that contained Arch, CPU,
-SoC, etc. of all the supported boards. It was deleted when switching to
-Kconfig. Each field of boards.cfg was converted as follows:
-
- Status -> "S:" entry of MAINTAINERS
- Arch -> CONFIG_SYS_ARCH defined by Kconfig
- CPU -> CONFIG_SYS_CPU defined by Kconfig
- SoC -> CONFIG_SYS_SOC defined by Kconfig
- Vendor -> CONFIG_SYS_VENDOR defined by Kconfig
- Board -> CONFIG_SYS_BOARD defined by Kconfig
- Target -> File name of defconfig (configs/<target>_defconfig)
- Maintainers -> "M:" entry of MAINTAINERS
-
-
-Tips to add/remove boards
--------------------------
-
-When adding a new board, the following steps are generally needed:
-
- [1] Add a header file include/configs/<target>.h
- [2] Make sure to define necessary CONFIG_SYS_* in Kconfig:
- Define CONFIG_SYS_CPU="cpu" to compile arch/<arch>/cpu/<cpu>
- Define CONFIG_SYS_SOC="soc" to compile arch/<arch>/cpu/<cpu>/<soc>
- Define CONFIG_SYS_VENDOR="vendor" to compile board/<vendor>/common/*
- and board/<vendor>/<board>/*
- Define CONFIG_SYS_BOARD="board" to compile board/<board>/*
- (or board/<vendor>/<board>/* if CONFIG_SYS_VENDOR is defined)
- Define CONFIG_SYS_CONFIG_NAME="target" to include
- include/configs/<target>.h
- [3] Add a new entry to the board select menu in Kconfig.
- The board select menu is located in arch/<arch>/Kconfig or
- arch/<arch>/*/Kconfig.
- [4] Add a MAINTAINERS file
- It is generally placed at board/<board>/MAINTAINERS or
- board/<vendor>/<board>/MAINTAINERS
- [5] Add configs/<target>_defconfig
-
-When removing an obsolete board, the following steps are generally needed:
-
- [1] Remove configs/<target>_defconfig
- [2] Remove include/configs/<target>.h if it is not used by any other boards
- [3] Remove board/<vendor>/<board>/* or board/<board>/* if it is not used
- by any other boards
- [4] Update MAINTAINERS if necessary
- [5] Remove the unused entry from the board select menu in Kconfig
- [6] Add an entry to doc/README.scrapyard
-
-
-TODO
-----
-
-- In the pre-Kconfig, a single board had multiple entries in the boards.cfg
- file with differences in the option fields. The corresponding defconfig
- files were auto-generated when switching to Kconfig. Now we have too many
- defconfig files compared with the number of the supported boards. It is
- recommended to have only one defconfig per board and allow users to select
- the config options.
-
-- Move the config macros in header files to Kconfig. When we move at least
- macros used in makefiles, we can drop include/autoconfig.mk, which makes
- the build scripts much simpler.
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index 30f7fdb..d9f2a83 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -13,6 +13,7 @@
codingstyle
designprinciples
docstyle
+ kconfig
memory
patman
process
diff --git a/doc/develop/kconfig.rst b/doc/develop/kconfig.rst
new file mode 100644
index 0000000..227074d
--- /dev/null
+++ b/doc/develop/kconfig.rst
@@ -0,0 +1,157 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Kconfig in U-Boot
+=================
+
+This document describes the configuration infrastructure of U-Boot.
+
+The conventional configuration was replaced by Kconfig at v2014.10-rc1 release.
+
+Language Specification
+----------------------
+
+The Kconfig configuration language originates in Linux kernel.
+See the Linux document
+`Kconfig Language <https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html>`_
+for a description of Kconfig.
+
+Difference from Linux's Kconfig
+-------------------------------
+
+Here are some worth-mentioning configuration targets.
+
+silentoldconfig
+ This target updates .config, include/generated/autoconf.h and
+ include/configs/* as in Linux. In U-Boot, it also does the following
+ for the compatibility with the old configuration system:
+
+ * create a symbolic link "arch/${ARCH}/include/asm/arch" pointing to
+ the SoC/CPU specific header directory
+ * create include/config.h
+ * create include/autoconf.mk
+ * create spl/include/autoconf.mk (SPL and TPL only)
+ * create tpl/include/autoconf.mk (TPL only)
+
+ If we could completely switch to Kconfig in a long run
+ (i.e. remove all the include/configs/\*.h), those additional processings
+ above would be removed.
+
+defconfig
+ In U-Boot, "make defconfig" is a shorthand of "make sandbox_defconfig"
+
+<board>_defconfig
+ Now it works as in Linux.
+ The prefixes such as "+S:" in \*_defconfig are deprecated.
+ You can simply remove the prefixes. Do not add them for new boards.
+
+<board>_config
+ This does not exist in Linux's Kconfig.
+ "make <board>_config" works the same as "make <board>_defconfig".
+ Prior to Kconfig, in U-Boot, "make <board>_config" was used for the
+ configuration. It is still supported for backward compatibility, so
+ we do not need to update the distro recipes.
+
+The other configuration targets work as in Linux Kernel.
+
+Migration steps to Kconfig
+--------------------------
+
+Prior to Kconfig, the C preprocessor based board configuration had been used
+in U-Boot.
+
+Although Kconfig was introduced and some configs have been moved to Kconfig,
+many of configs are still defined in C header files. It will take a very
+long term to move all of them to Kconfig. In the interim, the two different
+configuration infrastructures should coexist.
+The configuration files are generated by both Kconfig and the old preprocessor
+based configuration as follows:
+
+Configuration files for use in C sources
+ - include/generated/autoconf.h (generated by Kconfig for Normal)
+ - include/configs/<board>.h (exists for all boards)
+
+Configuration file for use in makefiles
+ - include/config/auto.conf (generated by Kconfig)
+ - include/autoconf.mk (generated by the old config for Normal)
+ - spl/include/autoconfig.mk (generated by the old config for SPL)
+ - tpl/include/autoconfig.mk (generated by the old config for TPL)
+
+When adding a new CONFIG macro, it is highly recommended to add it to Kconfig
+rather than to a header file.
+
+Conversion from boards.cfg to Kconfig
+-------------------------------------
+
+Prior to Kconfig, boards.cfg was a primary database that contained Arch, CPU,
+SoC, etc. of all the supported boards. It was deleted when switching to
+Kconfig. Each field of boards.cfg was converted as follows:
+
+=========== ====================================================
+From To
+=========== ====================================================
+Arch CONFIG_SYS_ARCH defined by Kconfig
+Board CONFIG_SYS_BOARD defined by Kconfig
+CPU CONFIG_SYS_CPU defined by Kconfig
+Maintainers "M:" entry of MAINTAINERS
+SoC CONFIG_SYS_SOC defined by Kconfig
+Status "S:" entry of MAINTAINERS
+Target File name of defconfig (configs/<target>\_defconfig)
+Vendor CONFIG_SYS_VENDOR defined by Kconfig
+=========== ====================================================
+
+Tips to add/remove boards
+-------------------------
+
+When adding a new board, the following steps are generally needed:
+
+1. Add a header file include/configs/<target>.h
+
+2. Make sure to define necessary CONFIG_SYS_* in Kconfig:
+
+ * Define CONFIG_SYS_CPU="cpu" to compile arch/<arch>/cpu/<cpu>
+ * Define CONFIG_SYS_SOC="soc" to compile arch/<arch>/cpu/<cpu>/<soc>
+ * Define CONFIG_SYS_VENDOR="vendor" to compile board/<vendor>/common/\*
+ and board/<vendor>/<board>/\*
+ * Define CONFIG_SYS_BOARD="board" to compile board/<board>/\*
+ (or board/<vendor>/<board>/* if CONFIG_SYS_VENDOR is defined)
+ Define CONFIG_SYS_CONFIG_NAME="target" to include
+ include/configs/<target>.h
+
+3. Add a new entry to the board select menu in Kconfig.
+ The board select menu is located in arch/<arch>/Kconfig or
+ arch/<arch>/\*/Kconfig.
+
+4. Add a MAINTAINERS file
+ It is generally placed at board/<board>/MAINTAINERS or
+ board/<vendor>/<board>/MAINTAINERS
+
+5. Add configs/<target>_defconfig
+
+When removing an obsolete board, the following steps are generally needed:
+
+1. Remove configs/<target>_defconfig
+
+2. Remove include/configs/<target>.h if it is not used by any other boards
+
+3. Remove board/<vendor>/<board>/\* or board/<board>/\* if it is not used
+ by any other boards
+
+4. Update MAINTAINERS if necessary
+
+5. Remove the unused entry from the board select menu in Kconfig
+
+6. Add an entry to doc/README.scrapyard
+
+TODO
+----
+
+* In the pre-Kconfig, a single board had multiple entries in the boards.cfg
+ file with differences in the option fields. The corresponding defconfig
+ files were auto-generated when switching to Kconfig. Now we have too many
+ defconfig files compared with the number of the supported boards. It is
+ recommended to have only one defconfig per board and allow users to select
+ the config options.
+
+* Move the config macros in header files to Kconfig. When we move at least
+ macros used in makefiles, we can drop include/autoconfig.mk, which makes
+ the build scripts much simpler.
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 1548d26..c742c2f 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -71,7 +71,7 @@
* U-Boot v2025.01-rc2 was released on Mon 11 November 2024.
-.. * U-Boot v2025.01-rc3 was released on Mon 25 November 2024.
+* U-Boot v2025.01-rc3 was released on Mon 25 November 2024.
.. * U-Boot v2025.01-rc4 was released on Mon 09 December 2024.
diff --git a/doc/usage/cmd/wget.rst b/doc/usage/cmd/wget.rst
index b8ca35b..48bedf1 100644
--- a/doc/usage/cmd/wget.rst
+++ b/doc/usage/cmd/wget.rst
@@ -11,29 +11,54 @@
::
- wget address [[hostIPaddr:]path]
+ wget [address] [host:]path
+ wget [address] url # lwIP only
+
Description
-----------
+The wget command is used to download a file from an HTTP(S) server.
+In order to use HTTPS you will need to compile wget with lwIP support.
+
-The wget command is used to download a file from an HTTP server.
+Legacy syntax
+~~~~~~~~~~~~~
-wget command will use HTTP over TCP to download files from an HTTP server.
+The legacy syntax is supported by the legacy network stack (CONFIG_NET=y)
+as well as by the lwIP base network stack (CONFIG_NET_LWIP=y). It supports HTTP
+only.
+
By default the destination port is 80 and the source port is pseudo-random.
-The environment variable *httpdstp* can be used to set the destination port.
+On the legacy nework stack the environment variable *httpdstp* can be used to
+set the destination port
address
memory address for the data downloaded
-hostIPaddr
- IP address of the HTTP server, defaults to the value of environment
- variable *serverip*
+host
+ IP address (or host name if `CONFIG_CMD_DNS` is enabled) of the HTTP
+ server, defaults to the value of environment variable *serverip*.
path
path of the file to be downloaded.
+New syntax (lwIP only)
+~~~~~~~~~~~~~~~~~~~~~~
+
+In addition to the syntax described above, wget accepts URLs if the network
+stack is lwIP.
+
+address
+ memory address for the data downloaded
+
+url
+ HTTP or HTTPS URL, that is: http[s]://<host>[:<port>]/<path>.
+
+Examples
+--------
+
-Example
--------
+Example with the legacy network stack
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In the example the following steps are executed:
@@ -52,13 +77,42 @@
HTTP/1.0 302 Found
Packets received 4, Transfer Successful
+Example with lwIP
+~~~~~~~~~~~~~~~~~
+
+In the example the following steps are executed:
+
+* setup client network address
+* download a file from the HTTPS server
+
+::
+
+ => dhcp
+ DHCP client bound to address 10.0.2.15 (3 ms)
+ => wget https://download.rockylinux.org/pub/rocky/9/isos/aarch64/Rocky-9.4-aarch64-minimal.iso
+ ##########################################################################
+ ##########################################################################
+ ##########################################################################
+ [...]
+ 1694892032 bytes transferred in 492181 ms (3.3 MiB/s)
+ Bytes transferred = 1694892032 (65060000 hex)
+
Configuration
-------------
The command is only available if CONFIG_CMD_WGET=y.
+To enable lwIP support set CONFIG_NET_LWIP=y.
+
+TCP Selective Acknowledgments in the legacy network stack can be enabled via
+CONFIG_PROT_TCP_SACK=y. This will improve the download speed. Selective
+Acknowledgments are enabled by default with lwIP.
+
+.. note::
-TCP Selective Acknowledgments can be enabled via CONFIG_PROT_TCP_SACK=y.
-This will improve the download speed.
+ U-Boot currently has no way to verify certificates for HTTPS.
+ A place to store the root CA certificates is needed, and then MBed TLS would
+ need to walk the entire chain. Therefore, man-in-the middle attacks are
+ possible and HTTPS should not be relied upon for payload authentication.
Return value
------------
diff --git a/doc/usage/dfu.rst b/doc/usage/dfu.rst
index 8cc09c3..af80551 100644
--- a/doc/usage/dfu.rst
+++ b/doc/usage/dfu.rst
@@ -22,6 +22,7 @@
Today the supported DFU backends are:
- MMC (RAW or FAT / EXT2 / EXT3 / EXT4 file system / SKIP / SCRIPT)
+- SCSI (UFS, RAW partition, FAT / EXT2 / EXT3 / EXT4 file system / SKIP / SCRIPT)
- NAND
- RAM
- SF (serial flash)
@@ -51,6 +52,7 @@
* CONFIG_DFU_MTD
* CONFIG_DFU_NAND
* CONFIG_DFU_RAM
+* CONFIG_DFU_SCSI
* CONFIG_DFU_SF
* CONFIG_DFU_SF_PART
* CONFIG_DFU_TIMEOUT
@@ -167,6 +169,36 @@
Please note that this means the user will be able to execute any
arbitrary commands just like in the u-boot's shell.
+scsi
+ for UFS storage::
+
+ dfu 0 scsi <dev>
+
+ each element in *dfu_alt_info* being
+
+ * <name> raw <offset> <size> raw access to SCSI LUN
+ * <name> part <part_id> raw access to partition
+ * <name> fat <part_id> file in FAT partition
+ * <name> ext4 <part_id> file in EXT4 partition
+ * <name> skip 0 0 ignore flashed data
+ * <name> script 0 0 execute commands in shell
+
+ with
+
+ size
+ is the size of the access area (hexadecimal without "0x")
+ or 0 which means whole device
+ partid
+ is the GPT or DOS partition index.
+ dev
+ is the SCSI LU (Logical Unit) index (decimal only)
+
+ A value of environment variable *dfu_alt_info* for UFS could be::
+
+ u-boot part 4;bl2 raw 0x1e 0x1d
+
+ See mmc section above for details on the skip and script types.
+
nand
raw slc nand device::
@@ -278,6 +310,7 @@
mmc <dev>=<alt1>;....;<altN>
nand <dev>=<alt1>;....;<altN>
ram <dev>=<alt1>;....;<altN>
+ scsi <dev>=<alt1>;....;<altN>
sf <dev>=<alt1>;....;<altN>
mtd <dev>=<alt1>;....;<altN>
virt <dev>=<alt1>;....;<altN>
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index fa6d8e7..0080d2a 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -164,6 +164,13 @@
Accessing the backend is done using the regmap interface.
+config DM_BOOTCOUNT_ZYNQMP
+ bool "Support ZynqMP PMUFW as a backing store for bootcount"
+ depends on ARCH_ZYNQMP
+ help
+ Enable support for the bootcount API by utilising the Persistent
+ Global General Storage Register 2 of the PMU.
+
endmenu
endif
diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
index 245f879..0cf79e4 100644
--- a/drivers/bootcount/Makefile
+++ b/drivers/bootcount/Makefile
@@ -16,3 +16,4 @@
obj-$(CONFIG_DM_BOOTCOUNT_I2C) += bootcount_dm_i2c.o
obj-$(CONFIG_DM_BOOTCOUNT_SPI_FLASH) += spi-flash.o
obj-$(CONFIG_DM_BOOTCOUNT_SYSCON) += bootcount_syscon.o
+obj-$(CONFIG_DM_BOOTCOUNT_ZYNQMP) += bootcount_zynqmp.o
diff --git a/drivers/bootcount/bootcount_zynqmp.c b/drivers/bootcount/bootcount_zynqmp.c
new file mode 100644
index 0000000..bc0984e
--- /dev/null
+++ b/drivers/bootcount/bootcount_zynqmp.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+// SPDX-FileCopyrightText: 2024 CERN (home.cern)
+
+#include <bootcount.h>
+#include <dm.h>
+#include <stdio.h>
+#include <zynqmp_firmware.h>
+#include <asm/arch/hardware.h>
+#include <dm/platdata.h>
+
+static int bootcount_zynqmp_set(struct udevice *dev, const u32 val)
+{
+ int ret;
+
+ ret = zynqmp_mmio_write((ulong)&pmu_base->pers_gen_storage2, 0xFF, val);
+ if (ret)
+ pr_info("%s write fail\n", __func__);
+
+ return ret;
+}
+
+static int bootcount_zynqmp_get(struct udevice *dev, u32 *val)
+{
+ int ret;
+
+ *val = 0;
+ ret = zynqmp_mmio_read((ulong)&pmu_base->pers_gen_storage2, val);
+ if (ret)
+ pr_info("%s read fail\n", __func__);
+
+ return ret;
+}
+
+U_BOOT_DRVINFO(bootcount_zynqmp) = {
+ .name = "bootcount_zynqmp",
+};
+
+static const struct bootcount_ops bootcount_zynqmp_ops = {
+ .get = bootcount_zynqmp_get,
+ .set = bootcount_zynqmp_set,
+};
+
+U_BOOT_DRIVER(bootcount_zynqmp) = {
+ .name = "bootcount_zynqmp",
+ .id = UCLASS_BOOTCOUNT,
+ .ops = &bootcount_zynqmp_ops,
+};
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 7a714f5..c7fb582 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -147,6 +147,13 @@
return 0;
}
+
+void dm_remove_devices_active(void)
+{
+ /* Remove non-vital devices first */
+ device_remove(dm_root(), DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL);
+ device_remove(dm_root(), DM_REMOVE_ACTIVE_ALL);
+}
#endif
int dm_scan_plat(bool pre_reloc_only)
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index 604386b..e33b005 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -89,6 +89,13 @@
used at board level to manage specific behavior
(OTP update for example).
+config DFU_SCSI
+ bool "SCSI flash back end for DFU"
+ help
+ This option enables using DFU to read and write to SCSI devices
+ used at board level to manage specific behavior
+ (OTP update for example).
+
config SET_DFU_ALT_INFO
bool "Dynamic set of DFU alternate information"
help
diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile
index 05d7cc6..6e1ab1c 100644
--- a/drivers/dfu/Makefile
+++ b/drivers/dfu/Makefile
@@ -11,3 +11,4 @@
obj-$(CONFIG_$(XPL_)DFU_SF) += dfu_sf.o
obj-$(CONFIG_$(XPL_)DFU_WRITE_ALT) += dfu_alt.o
obj-$(CONFIG_$(XPL_)DFU_VIRT) += dfu_virt.o
+obj-$(CONFIG_$(XPL_)DFU_SCSI) += dfu_scsi.o
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 7a4d7ba..7565692 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -564,6 +564,9 @@
} else if (strcmp(interface, "virt") == 0) {
if (dfu_fill_entity_virt(dfu, devstr, argv, argc))
return -1;
+ } else if (strcmp(interface, "scsi") == 0) {
+ if (dfu_fill_entity_scsi(dfu, devstr, argv, argc))
+ return -1;
} else {
printf("%s: Device %s not (yet) supported!\n",
__func__, interface);
@@ -660,7 +663,7 @@
const char *dfu_get_dev_type(enum dfu_device_type t)
{
const char *const dev_t[] = {NULL, "eMMC", "OneNAND", "NAND", "RAM",
- "SF", "MTD", "VIRT"};
+ "SF", "MTD", "VIRT", "SCSI"};
return dev_t[t];
}
diff --git a/drivers/dfu/dfu_scsi.c b/drivers/dfu/dfu_scsi.c
new file mode 100644
index 0000000..9f95194
--- /dev/null
+++ b/drivers/dfu/dfu_scsi.c
@@ -0,0 +1,435 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DFU SCSI backend (based on MMC backend).
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * author: Lukasz Majewski <l.majewski@samsung.com>
+ * Copyright (C) 2024 Linaro Ltd.
+ */
+
+#include <log.h>
+#include <malloc.h>
+#include <errno.h>
+#include <div64.h>
+#include <dfu.h>
+#include <ext4fs.h>
+#include <fat.h>
+#include <scsi.h>
+#include <part.h>
+#include <command.h>
+#include <linux/printk.h>
+
+static unsigned char *dfu_file_buf;
+static u64 dfu_file_buf_len;
+static u64 dfu_file_buf_offset;
+
+#define scsi_get_blk_desc(dev) ((struct blk_desc *)dev_get_uclass_plat(dev))
+
+#define find_scsi_device(dev_num, scsi) blk_get_device(UCLASS_SCSI, dev_num, scsi)
+
+static int scsi_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len)
+{
+ struct udevice *scsi;
+ u32 blk_start, blk_count, n = 0;
+ int ret;
+
+ ret = find_scsi_device(dfu->data.scsi.lun, &scsi);
+ if (ret < 0) {
+ pr_err("Device scsi %d - not found!", dfu->data.scsi.lun);
+ return -ENODEV;
+ }
+
+ /*
+ * We must ensure that we work in lba_blk_size chunks, so ALIGN
+ * this value.
+ */
+ *len = ALIGN(*len, dfu->data.scsi.lba_blk_size);
+
+ blk_start = dfu->data.scsi.lba_start + (u32)lldiv(offset, dfu->data.scsi.lba_blk_size);
+ blk_count = *len / dfu->data.scsi.lba_blk_size;
+ if (blk_start + blk_count > dfu->data.scsi.lba_start + dfu->data.scsi.lba_size) {
+ puts("Request would exceed designated area!\n");
+ return -EINVAL;
+ }
+
+ debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__,
+ op == DFU_OP_READ ? "scsi READ" : "scsi WRITE", dfu->data.scsi.lun, blk_start,
+ blk_count, buf);
+ switch (op) {
+ case DFU_OP_READ:
+ n = blk_dread(scsi_get_blk_desc(scsi), blk_start, blk_count, buf);
+ break;
+ case DFU_OP_WRITE:
+ n = blk_dwrite(scsi_get_blk_desc(scsi), blk_start, blk_count, buf);
+ break;
+ default:
+ pr_err("Operation not supported\n");
+ }
+
+ if (n != blk_count) {
+ pr_err("scsi block operation failed");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int scsi_file_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, u64 *len)
+{
+ char dev_part_str[8];
+ int ret;
+ int fstype;
+ loff_t size = 0;
+
+ switch (dfu->layout) {
+ case DFU_FS_FAT:
+ fstype = FS_TYPE_FAT;
+ break;
+ case DFU_FS_EXT4:
+ fstype = FS_TYPE_EXT;
+ break;
+ case DFU_SKIP:
+ return 0;
+ default:
+ printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+ dfu_get_layout(dfu->layout));
+ return -1;
+ }
+
+ snprintf(dev_part_str, sizeof(dev_part_str), "%d:%d", dfu->data.scsi.dev,
+ dfu->data.scsi.part);
+
+ ret = fs_set_blk_dev("scsi", dev_part_str, fstype);
+ if (ret) {
+ puts("dfu: fs_set_blk_dev error!\n");
+ return ret;
+ }
+
+ switch (op) {
+ case DFU_OP_READ:
+ ret = fs_read(dfu->name, (size_t)buf, offset, *len, &size);
+ if (ret) {
+ puts("dfu: fs_read error!\n");
+ return ret;
+ }
+ *len = size;
+ break;
+ case DFU_OP_WRITE:
+ ret = fs_write(dfu->name, (size_t)buf, offset, *len, &size);
+ if (ret) {
+ puts("dfu: fs_write error!\n");
+ return ret;
+ }
+ break;
+ case DFU_OP_SIZE:
+ ret = fs_size(dfu->name, &size);
+ if (ret) {
+ puts("dfu: fs_size error!\n");
+ return ret;
+ }
+ *len = size;
+ break;
+ default:
+ return -1;
+ }
+
+ return ret;
+}
+
+static int scsi_file_buf_write(struct dfu_entity *dfu, u64 offset, void *buf, long *len)
+{
+ int ret = 0;
+
+ if (offset == 0) {
+ dfu_file_buf_len = 0;
+ dfu_file_buf_offset = 0;
+ }
+
+ /* Add to the current buffer. */
+ if (dfu_file_buf_len + *len > CONFIG_SYS_DFU_MAX_FILE_SIZE)
+ *len = CONFIG_SYS_DFU_MAX_FILE_SIZE - dfu_file_buf_len;
+ memcpy(dfu_file_buf + dfu_file_buf_len, buf, *len);
+ dfu_file_buf_len += *len;
+
+ if (dfu_file_buf_len == CONFIG_SYS_DFU_MAX_FILE_SIZE) {
+ ret = scsi_file_op(DFU_OP_WRITE, dfu, dfu_file_buf_offset, dfu_file_buf,
+ &dfu_file_buf_len);
+ dfu_file_buf_offset += dfu_file_buf_len;
+ dfu_file_buf_len = 0;
+ }
+
+ return ret;
+}
+
+static int scsi_file_buf_write_finish(struct dfu_entity *dfu)
+{
+ int ret = scsi_file_op(DFU_OP_WRITE, dfu, dfu_file_buf_offset, dfu_file_buf,
+ &dfu_file_buf_len);
+
+ /* Now that we're done */
+ dfu_file_buf_len = 0;
+ dfu_file_buf_offset = 0;
+
+ return ret;
+}
+
+int dfu_write_medium_scsi(struct dfu_entity *dfu, u64 offset, void *buf, long *len)
+{
+ int ret = -1;
+
+ switch (dfu->layout) {
+ case DFU_RAW_ADDR:
+ ret = scsi_block_op(DFU_OP_WRITE, dfu, offset, buf, len);
+ break;
+ case DFU_FS_FAT:
+ case DFU_FS_EXT4:
+ ret = scsi_file_buf_write(dfu, offset, buf, len);
+ break;
+ case DFU_SCRIPT:
+ ret = run_command_list(buf, *len, 0);
+ break;
+ case DFU_SKIP:
+ ret = 0;
+ break;
+ default:
+ printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+ dfu_get_layout(dfu->layout));
+ }
+
+ return ret;
+}
+
+int dfu_flush_medium_scsi(struct dfu_entity *dfu)
+{
+ int ret = 0;
+
+ switch (dfu->layout) {
+ case DFU_FS_FAT:
+ case DFU_FS_EXT4:
+ ret = scsi_file_buf_write_finish(dfu);
+ break;
+ case DFU_SCRIPT:
+ /* script may have changed the dfu_alt_info */
+ dfu_reinit_needed = true;
+ break;
+ case DFU_RAW_ADDR:
+ case DFU_SKIP:
+ break;
+ default:
+ printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+ dfu_get_layout(dfu->layout));
+ }
+
+ return ret;
+}
+
+int dfu_get_medium_size_scsi(struct dfu_entity *dfu, u64 *size)
+{
+ int ret;
+
+ switch (dfu->layout) {
+ case DFU_RAW_ADDR:
+ *size = dfu->data.scsi.lba_size * dfu->data.scsi.lba_blk_size;
+ return 0;
+ case DFU_FS_FAT:
+ case DFU_FS_EXT4:
+ ret = scsi_file_op(DFU_OP_SIZE, dfu, 0, NULL, size);
+ if (ret < 0)
+ return ret;
+ return 0;
+ case DFU_SCRIPT:
+ case DFU_SKIP:
+ return 0;
+ default:
+ printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+ dfu_get_layout(dfu->layout));
+ return -1;
+ }
+}
+
+static int scsi_file_buf_read(struct dfu_entity *dfu, u64 offset, void *buf, long *len)
+{
+ int ret;
+
+ if (offset == 0 || offset >= dfu_file_buf_offset + dfu_file_buf_len ||
+ offset + *len < dfu_file_buf_offset) {
+ u64 file_len = CONFIG_SYS_DFU_MAX_FILE_SIZE;
+
+ ret = scsi_file_op(DFU_OP_READ, dfu, offset, dfu_file_buf, &file_len);
+ if (ret < 0)
+ return ret;
+ dfu_file_buf_len = file_len;
+ dfu_file_buf_offset = offset;
+ }
+ if (offset + *len > dfu_file_buf_offset + dfu_file_buf_len)
+ return -EINVAL;
+
+ /* Add to the current buffer. */
+ memcpy(buf, dfu_file_buf + offset - dfu_file_buf_offset, *len);
+
+ return 0;
+}
+
+int dfu_read_medium_scsi(struct dfu_entity *dfu, u64 offset, void *buf, long *len)
+{
+ int ret = -1;
+
+ switch (dfu->layout) {
+ case DFU_RAW_ADDR:
+ ret = scsi_block_op(DFU_OP_READ, dfu, offset, buf, len);
+ break;
+ case DFU_FS_FAT:
+ case DFU_FS_EXT4:
+ ret = scsi_file_buf_read(dfu, offset, buf, len);
+ break;
+ default:
+ printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+ dfu_get_layout(dfu->layout));
+ }
+
+ return ret;
+}
+
+void dfu_free_entity_scsi(struct dfu_entity *dfu)
+{
+ if (dfu_file_buf) {
+ free(dfu_file_buf);
+ dfu_file_buf = NULL;
+ }
+}
+
+/*
+ * @param s Parameter string containing space-separated arguments:
+ * 1st:
+ * raw (raw read/write)
+ * fat (files)
+ * ext4 (^)
+ * part (partition image)
+ * 2nd and 3rd:
+ * lba_start and lba_size, for raw write
+ * scsi_dev and scsi_part, for filesystems and part
+ */
+int dfu_fill_entity_scsi(struct dfu_entity *dfu, char *devstr, char **argv, int argc)
+{
+ const char *entity_type;
+ ssize_t second_arg;
+ ssize_t third_arg = -1;
+ struct udevice *scsi;
+ struct blk_desc *blk_dev;
+ int ret;
+ char *s;
+
+ if (argc < 2) {
+ pr_err("Need at least one argument\n");
+ return -EINVAL;
+ }
+
+ dfu->data.scsi.lun = dectoul(devstr, &s);
+ if (*s)
+ return -EINVAL;
+
+ entity_type = argv[0];
+ /*
+ * Base 0 means we'll accept (prefixed with 0x or 0) base 16, 8,
+ * with default 10.
+ */
+ second_arg = simple_strtol(argv[1], &s, 0);
+ if (*s)
+ return -EINVAL;
+ if (argc >= 3) {
+ third_arg = simple_strtoul(argv[2], &s, 0);
+ if (*s)
+ return -EINVAL;
+ }
+
+ if (scsi_scan(false)) {
+ pr_err("Couldn't init scsi device.\n");
+ return -ENODEV;
+ }
+
+ ret = find_scsi_device(dfu->data.scsi.lun, &scsi);
+ if (ret < 0) {
+ pr_err("Couldn't find scsi device no. %d.\n", dfu->data.scsi.lun);
+ return -ENODEV;
+ }
+
+ blk_dev = scsi_get_blk_desc(scsi);
+ if (!blk_dev) {
+ pr_err("Couldn't get block device for scsi device no. %d.\n", dfu->data.scsi.lun);
+ return -ENODEV;
+ }
+
+ /* if it's NOT a raw write */
+ if (strcmp(entity_type, "raw")) {
+ dfu->data.scsi.dev = (second_arg != -1) ? second_arg : dfu->data.scsi.lun;
+ dfu->data.scsi.part = third_arg;
+ }
+
+ if (!strcmp(entity_type, "raw")) {
+ dfu->layout = DFU_RAW_ADDR;
+ dfu->data.scsi.lba_start = second_arg;
+ if (third_arg < 0) {
+ pr_err("raw requires two arguments\n");
+ return -EINVAL;
+ }
+ dfu->data.scsi.lba_size = third_arg;
+ dfu->data.scsi.lba_blk_size = blk_dev->blksz;
+
+ /*
+ * In case the size is zero (i.e. scsi raw 0x10 0),
+ * assume the user intends to use whole device.
+ */
+ if (third_arg == 0)
+ dfu->data.scsi.lba_size = blk_dev->lba;
+
+ } else if (!strcmp(entity_type, "part")) {
+ struct disk_partition partinfo;
+ int scsipart = second_arg;
+
+ if (third_arg >= 0) {
+ pr_err("part only accepts one argument\n");
+ return -EINVAL;
+ }
+
+ if (part_get_info(blk_dev, scsipart, &partinfo) != 0) {
+ pr_err("Couldn't find part #%d on scsi device #%d\n", scsipart,
+ dfu->data.scsi.lun);
+ return -ENODEV;
+ }
+
+ dfu->layout = DFU_RAW_ADDR;
+ dfu->data.scsi.lba_start = partinfo.start;
+ dfu->data.scsi.lba_size = partinfo.size;
+ dfu->data.scsi.lba_blk_size = partinfo.blksz;
+ } else if (!strcmp(entity_type, "fat")) {
+ dfu->layout = DFU_FS_FAT;
+ } else if (!strcmp(entity_type, "ext4")) {
+ dfu->layout = DFU_FS_EXT4;
+ } else if (!strcmp(entity_type, "skip")) {
+ dfu->layout = DFU_SKIP;
+ } else if (!strcmp(entity_type, "script")) {
+ dfu->layout = DFU_SCRIPT;
+ } else {
+ pr_err("Memory layout (%s) not supported!\n", entity_type);
+ return -ENODEV;
+ }
+
+ dfu->dev_type = DFU_DEV_SCSI;
+ dfu->get_medium_size = dfu_get_medium_size_scsi;
+ dfu->read_medium = dfu_read_medium_scsi;
+ dfu->write_medium = dfu_write_medium_scsi;
+ dfu->flush_medium = dfu_flush_medium_scsi;
+ dfu->inited = 0;
+ dfu->free_entity = dfu_free_entity_scsi;
+
+ /* Check if file buffer is ready */
+ if (!dfu_file_buf) {
+ dfu_file_buf = memalign(CONFIG_SYS_CACHELINE_SIZE, CONFIG_SYS_DFU_MAX_FILE_SIZE);
+ if (!dfu_file_buf) {
+ pr_err("Could not memalign 0x%x bytes\n", CONFIG_SYS_DFU_MAX_FILE_SIZE);
+ return -ENOMEM;
+ }
+ }
+
+ return 0;
+}
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index f2ef4e5..cd9f392 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -69,6 +69,17 @@
#define REG_EN_CTL 0x46
#define REG_EN_CTL_ENABLE (1 << 7)
+/**
+ * pmic_gpio_match_data - platform specific configuration
+ *
+ * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them.
+ * This is a workaround for an unknown bug on some platforms where trying to write the
+ * GPIO configuration registers causes the board to hang.
+ */
+enum pmic_gpio_quirks {
+ QCOM_PMIC_QUIRK_READONLY = (1 << 0),
+};
+
struct qcom_pmic_gpio_data {
uint32_t pid; /* Peripheral ID on SPMI bus */
bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
@@ -117,8 +128,13 @@
{
struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
+ ulong quirks = dev_get_driver_data(dev);
int ret = 0;
+ /* Some PMICs don't like their GPIOs being configured */
+ if (quirks & QCOM_PMIC_QUIRK_READONLY)
+ return 0;
+
/* Disable the GPIO */
ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
REG_EN_CTL_ENABLE, 0);
@@ -262,6 +278,7 @@
{
struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+ ulong quirks = dev_get_driver_data(dev);
struct udevice *child;
struct driver *drv;
int ret;
@@ -275,7 +292,7 @@
/* Bind the GPIO driver as a child of the PMIC. */
ret = device_bind_with_driver_data(dev, drv,
dev->name,
- 0, dev_ofnode(dev), &child);
+ quirks, dev_ofnode(dev), &child);
if (ret)
return log_msg_ret("bind", ret);
@@ -348,7 +365,7 @@
{ .compatible = "qcom,pms405-gpio" },
{ .compatible = "qcom,pm6125-gpio" },
{ .compatible = "qcom,pm8150-gpio" },
- { .compatible = "qcom,pm8550-gpio" },
+ { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
{ }
};
diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c
index 3e9e7819..bfd4ad2 100644
--- a/drivers/iommu/apple_dart.c
+++ b/drivers/iommu/apple_dart.c
@@ -322,5 +322,5 @@
.ops = &apple_dart_ops,
.probe = apple_dart_probe,
.remove = apple_dart_remove,
- .flags = DM_FLAG_OS_PREPARE
+ .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL
};
diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c
index 1b5a09b..c1b95bc 100644
--- a/drivers/iommu/qcom-hyp-smmu.c
+++ b/drivers/iommu/qcom-hyp-smmu.c
@@ -91,6 +91,8 @@
phys_addr_t base;
struct list_head devices;
struct udevice *dev;
+ /* SMMU is not needed when running in EL2 */
+ bool disable;
/* Read-once config */
int num_cb;
@@ -134,7 +136,7 @@
int count = ofnode_parse_phandle_with_args(node, "iommus",
"#iommu-cells", 0, 0, &args);
- if (count < 0 || args.args[0] == 0) {
+ if (count < 0) {
printf("Error: %s: iommus property not found or wrong number of cells\n",
__func__);
return -EINVAL;
@@ -277,6 +279,9 @@
if (WARN_ON(!priv))
return -EINVAL;
+ if (priv->disable)
+ return 0;
+
mdev = alloc_dev(dev);
if (IS_ERR(mdev) && PTR_ERR(mdev) != -EEXIST) {
printf("%s: %s Couldn't create mmu context\n", __func__,
@@ -348,6 +353,8 @@
priv->base = dev_read_addr(dev);
INIT_LIST_HEAD(&priv->devices);
+ priv->disable = current_el() > 1;
+
/* Read SMMU config */
val = gr0_readl(priv, ARM_SMMU_GR0_ID0);
priv->num_smr = FIELD_GET(ARM_SMMU_ID0_NUMSMRG, val);
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 4e5c932..27bb705 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -15,6 +15,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
+#include <power/regulator.h>
/* Non-standard registers needed for SDHCI startup */
#define SDCC_MCI_POWER 0x0
@@ -43,6 +44,7 @@
struct sdhci_host host;
void *base;
struct clk_bulk clks;
+ struct udevice *vqmmc;
};
struct msm_sdhc_variant_info {
@@ -163,6 +165,16 @@
if (ret)
return ret;
+ /* Get the vqmmc regulator and enable it if available */
+ device_get_supply_regulator(dev, "vqmmc-supply", &prv->vqmmc);
+ if (prv->vqmmc) {
+ ret = regulator_set_enable_if_allowed(prv->vqmmc, true);
+ if (ret) {
+ printf("Failed to enable the VQMMC regulator\n");
+ return ret;
+ }
+ }
+
var_info = (void *)dev_get_driver_data(dev);
if (!var_info->mci_removed) {
ret = msm_sdc_mci_init(prv);
diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
index 8908a34..5c90d60 100644
--- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
@@ -84,12 +84,6 @@
QPHY_LAYOUT_SIZE
};
-static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
- [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
- [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
-};
-
static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START,
[QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS,
@@ -189,6 +183,29 @@
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
};
+static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
+};
+
+static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
+};
+
static const struct qmp_ufs_init_tbl sm8150_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
@@ -461,6 +478,112 @@
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
};
+
+static const struct qmp_ufs_init_tbl sc7280_ufsphy_tx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
+};
+
+static const struct qmp_ufs_init_tbl sc7280_ufsphy_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+};
+
+static const struct qmp_ufs_init_tbl sc7280_ufsphy_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
+};
+
+static const struct qmp_ufs_init_tbl sc7280_ufsphy_hs_g4_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f),
+};
+
struct qmp_ufs_offsets {
u16 serdes;
u16 pcs;
@@ -623,6 +746,44 @@
.no_pcs_sw_reset = true,
};
+static const struct qmp_ufs_cfg sm8150_ufsphy_cfg = {
+ .lanes = 2,
+
+ .offsets = &qmp_ufs_offsets,
+
+ .tbls = {
+ .serdes = sm8150_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
+ .tx = sm8150_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
+ .rx = sm8150_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
+ .pcs = sm8150_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
+ },
+ .tbls_hs_b = {
+ .serdes = sm8150_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
+ },
+ .tbls_hs_g4 = {
+ .tx = sm8150_ufsphy_hs_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
+ .rx = sm8150_ufsphy_hs_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
+ .pcs = sm8150_ufsphy_hs_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ },
+ .clk_list = sdm845_ufs_phy_clk_l,
+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+ .vreg_list = qmp_ufs_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l),
+ .reset_list = qmp_ufs_reset_l,
+ .num_resets = ARRAY_SIZE(qmp_ufs_reset_l),
+ .regs = ufsphy_v4_regs_layout,
+
+ .no_pcs_sw_reset = false,
+};
+
static const struct qmp_ufs_cfg sm8250_ufsphy_cfg = {
.lanes = 2,
@@ -713,6 +874,41 @@
.no_pcs_sw_reset = false,
};
+
+static const struct qmp_ufs_cfg sc7280_ufsphy_cfg = {
+ .lanes = 2,
+
+ .offsets = &qmp_ufs_offsets,
+
+ .tbls = {
+ .serdes = sm8150_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
+ .tx = sc7280_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx),
+ .rx = sc7280_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx),
+ .pcs = sc7280_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs),
+ },
+ .tbls_hs_b = {
+ .serdes = sm8150_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
+ },
+ .tbls_hs_g4 = {
+ .tx = sm8250_ufsphy_hs_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
+ .rx = sc7280_ufsphy_hs_g4_rx,
+ .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
+ .pcs = sm8150_ufsphy_hs_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ },
+ .clk_list = sdm845_ufs_phy_clk_l,
+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+ .vreg_list = qmp_ufs_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l),
+ .regs = ufsphy_v4_regs_layout,
+};
+
static void qmp_ufs_configure_lane(void __iomem *base,
const struct qmp_ufs_init_tbl tbl[],
int num,
@@ -1100,9 +1296,11 @@
static const struct udevice_id qmp_ufs_ids[] = {
{ .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
+ { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg },
{ .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg },
{ .compatible = "qcom,sm8550-qmp-ufs-phy", .data = (ulong)&sm8550_ufsphy_cfg },
{ .compatible = "qcom,sm8650-qmp-ufs-phy", .data = (ulong)&sm8650_ufsphy_cfg },
+ { .compatible = "qcom,sc7280-qmp-ufs-phy", .data = (ulong)&sc7280_ufsphy_cfg, },
{ }
};
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 9c466f8..331a46d 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -251,13 +251,6 @@
priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
- /* Versal and Versal-NET use spi calibration to set read delay */
- if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
- CONFIG_IS_ENABLED(ARCH_VERSAL_NET) ||
- CONFIG_IS_ENABLED(ARCH_VERSAL2))
- if (priv->read_delay >= 0)
- priv->read_delay = -1;
-
/* Reset ospi flash device */
return cadence_qspi_versal_flash_reset(bus);
}
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 36b7d38..d604975 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -446,7 +446,7 @@
slave = dev_get_parent_priv(dev);
bus_data = dev_get_uclass_priv(bus);
-#if CONFIG_IS_ENABLED(SPI_ADVANCE)
+#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)
if ((dev_read_bool(dev, "parallel-memories")) && !slave->multi_cs_cap) {
dev_err(dev, "controller doesn't support multi CS\n");
return -EINVAL;
@@ -515,7 +515,7 @@
int mode = 0;
int value;
-#if CONFIG_IS_ENABLED(SPI_ADVANCE)
+#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)
int ret;
ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX);
diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c
index 4bd3b9d..69d3073 100644
--- a/drivers/usb/eth/asix88179.c
+++ b/drivers/usb/eth/asix88179.c
@@ -173,9 +173,10 @@
#define USB_BULK_SEND_TIMEOUT 5000
#define USB_BULK_RECV_TIMEOUT 5000
-#define AX_RX_URB_SIZE 1024 * 0x12
+#define AX_RX_URB_SIZE 1024 * 0x1a
#define BLK_FRAME_SIZE 0x200
#define PHY_CONNECT_TIMEOUT 5000
+#define PHY_RESET_TIMEOUT 500
#define TIMEOUT_RESOLUTION 50 /* ms */
@@ -192,10 +193,10 @@
static const struct {
unsigned char ctrl, timer_l, timer_h, size, ifg;
} AX88179_BULKIN_SIZE[] = {
- {7, 0x4f, 0, 0x02, 0xff},
- {7, 0x20, 3, 0x03, 0xff},
- {7, 0xae, 7, 0x04, 0xff},
- {7, 0xcc, 0x4c, 0x04, 8},
+ {7, 0x4f, 0, 0x12, 0xff},
+ {7, 0x20, 3, 0x16, 0xff},
+ {7, 0xae, 7, 0x18, 0xff},
+ {7, 0xcc, 0x4c, 0x18, 8},
};
/* driver private */
@@ -285,6 +286,26 @@
return ret;
}
+static int asix_reset_phy(struct ueth_data *dev)
+{
+ u16 bmcr;
+ u32 t;
+
+ /* Reset the PHY */
+ bmcr = BMCR_RESET;
+ asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
+
+ for (t = 0; t < PHY_RESET_TIMEOUT; t += TIMEOUT_RESOLUTION) {
+ asix_read_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
+ if (!(bmcr & BMCR_RESET))
+ return 0;
+ mdelay(TIMEOUT_RESOLUTION);
+ }
+
+ debug("Reset PHY timeout\n");
+ return -ETIMEDOUT;
+}
+
static int asix_basic_reset(struct ueth_data *dev,
struct asix_private *dev_priv)
{
@@ -311,7 +332,7 @@
memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
- dev_priv->rx_urb_size = 128 * 20;
+ dev_priv->rx_urb_size = 1024 * 20;
/* Water Level configuration */
*tmp = 0x34;
@@ -344,14 +365,22 @@
AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16);
+ asix_reset_phy(dev);
+
u16 adv = 0;
- adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK |
- ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
+ adv = ADVERTISE_ALL | ADVERTISE_CSMA |
+ ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv);
adv = ADVERTISE_1000FULL;
asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv);
+ /* Restart auto-negotiation */
+ u16 bmcr = 0;
+ asix_read_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
+ bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
+ asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
+
return 0;
}
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
index 21fe194..014cf18 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
@@ -124,6 +124,7 @@
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 6740ab2..3bcc4c4 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -82,7 +82,7 @@
"nor0=flash-0\0"\
"mtdparts=mtdparts=flash-0:"\
"256k(u-boot),256k(env),3m(kernel),"\
- "1m(romfs),1m(cramfs),-(jffs2)\0"\
+ "1m(romfs),1m(cramfs),-(fs)\0"\
"nc=setenv stdout nc;"\
"setenv stdin nc\0" \
"serial=setenv stdout serial;"\
diff --git a/include/configs/qcom.h b/include/configs/qcom.h
index 5b5ebbd..9b41ab9 100644
--- a/include/configs/qcom.h
+++ b/include/configs/qcom.h
@@ -11,4 +11,9 @@
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
+// 2a5aa852-b856-4d97-baa9-5c5f4421551f
+#define QUALCOMM_UBOOT_BOOT_IMAGE_GUID \
+ EFI_GUID(0x2a5aa852, 0xb856, 0x4d97, 0xba, 0xa9, \
+ 0x5c, 0x5f, 0x44, 0x21, 0x55, 0x1f)
+
#endif
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index 4e0b3c6..0a5f23e 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -12,13 +12,4 @@
#include "mv-common.h"
-/*
- * Environment variables configurations
- */
-#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
- "=ttyS0,115200 mtdparts=" CONFIG_MTDPARTS_DEFAULT \
- "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
-
#endif /* _CONFIG_SHEEVAPLUG_H */
diff --git a/include/configs/x240.h b/include/configs/x240.h
index 3601df5..05241f3 100644
--- a/include/configs/x240.h
+++ b/include/configs/x240.h
@@ -11,22 +11,14 @@
/* additions for new ARM relocation support */
#define CFG_SYS_SDRAM_BASE 0x200000000
-#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200, 230400, 460800, 921600 }
-
/* Default Env vars */
-
-#define BOOT_TARGET_DEVICES(func) \
- func(USB, usb, 0) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
+#define BOOT_TARGETS "usb dhcp"
#define CFG_EXTRA_ENV_SETTINGS \
- BOOTENV \
"kernel_addr_r=0x202000000\0" \
"fdt_addr_r=0x201000000\0" \
"ramdisk_addr_r=0x206000000\0" \
+ "boot_targets=" BOOT_TARGETS "\0" \
"fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
/*
diff --git a/include/configs/x250.h b/include/configs/x250.h
new file mode 100644
index 0000000..39f523f
--- /dev/null
+++ b/include/configs/x250.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 Allied Telesis
+ */
+
+#ifndef __X250_H_
+#define __X250_H_
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CFG_SYS_TCLK 250000000 /* 250MHz */
+
+/* additions for new ARM relocation support */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+
+#define BOOT_TARGETS "usb scsi pxe dhcp"
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x6d00000\0" \
+ "pxefile_addr_r=0x6e00000\0" \
+ "fdt_addr_r=0x6f00000\0" \
+ "kernel_addr_r=0x7000000\0" \
+ "ramdisk_addr_r=0xa000000\0" \
+ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "boot_targets=" BOOT_TARGETS "\0"
+
+#endif /* __X250_H_ */
diff --git a/include/configs/x530.h b/include/configs/x530.h
index 982b129..c7bfd1d 100644
--- a/include/configs/x530.h
+++ b/include/configs/x530.h
@@ -18,30 +18,14 @@
#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
#endif
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
/* NAND */
#define BBT_CUSTOM_SCAN
#define BBT_CUSTOM_SCAN_PAGE 0
#define BBT_CUSTOM_SCAN_POSITION 2048
-/* SPI NOR flash default params, used by sf commands */
-
#define MTDPARTS_MTDOOPS "errlog"
-/* Partition support */
-
-/* Additional FS support/configuration */
-
-/* Environment in SPI NOR flash */
-
-/* NAND */
-
#include <asm/arch/config.h>
/* Keep device tree and initrd in low memory so the kernel can access them */
diff --git a/include/dfu.h b/include/dfu.h
index e25588c..12f9dfc 100644
--- a/include/dfu.h
+++ b/include/dfu.h
@@ -24,6 +24,7 @@
DFU_DEV_SF,
DFU_DEV_MTD,
DFU_DEV_VIRT,
+ DFU_DEV_SCSI,
};
enum dfu_layout {
@@ -99,6 +100,19 @@
int dev_num;
};
+struct scsi_internal_data {
+ int lun;
+
+ /* RAW programming */
+ unsigned int lba_start;
+ unsigned int lba_size;
+ unsigned int lba_blk_size;
+
+ /* FAT/EXT */
+ unsigned int dev; // Always 0???
+ unsigned int part;
+};
+
#if defined(CONFIG_DFU_NAME_MAX_SIZE)
#define DFU_NAME_SIZE CONFIG_DFU_NAME_MAX_SIZE
#else
@@ -126,6 +140,7 @@
struct ram_internal_data ram;
struct sf_internal_data sf;
struct virt_internal_data virt;
+ struct scsi_internal_data scsi;
} data;
int (*get_medium_size)(struct dfu_entity *dfu, u64 *size);
@@ -516,6 +531,18 @@
}
#endif
+#if CONFIG_IS_ENABLED(DFU_SCSI)
+int dfu_fill_entity_scsi(struct dfu_entity *dfu, char *devstr,
+ char **argv, int argc);
+#else
+static inline int dfu_fill_entity_scsi(struct dfu_entity *dfu, char *devstr,
+ char **argv, int argc)
+{
+ puts("SCSI support not available!\n");
+ return -1;
+}
+#endif
+
extern bool dfu_reinit_needed;
extern bool dfu_alt_info_changed;
diff --git a/include/dm/root.h b/include/dm/root.h
index b2f30a8..5651b86 100644
--- a/include/dm/root.h
+++ b/include/dm/root.h
@@ -167,8 +167,18 @@
* Return: 0 if OK, -ve on error
*/
int dm_remove_devices_flags(uint flags);
+
+/**
+ * dm_remove_devices_active - Call remove function of all active drivers heeding
+ * device dependencies as far as know, i.e. removing
+ * devices marked with DM_FLAG_VITAL last.
+ *
+ * All active devices will be removed
+ */
+void dm_remove_devices_active(void);
#else
static inline int dm_remove_devices_flags(uint flags) { return 0; }
+static inline void dm_remove_devices_active(void) { }
#endif
/**
diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h
deleted file mode 100644
index 4f7a2d2..0000000
--- a/include/dt-bindings/clock/qcom,camcc-sdm845.h
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
-
-/* CAM_CC clock registers */
-#define CAM_CC_BPS_AHB_CLK 0
-#define CAM_CC_BPS_AREG_CLK 1
-#define CAM_CC_BPS_AXI_CLK 2
-#define CAM_CC_BPS_CLK 3
-#define CAM_CC_BPS_CLK_SRC 4
-#define CAM_CC_CAMNOC_ATB_CLK 5
-#define CAM_CC_CAMNOC_AXI_CLK 6
-#define CAM_CC_CCI_CLK 7
-#define CAM_CC_CCI_CLK_SRC 8
-#define CAM_CC_CPAS_AHB_CLK 9
-#define CAM_CC_CPHY_RX_CLK_SRC 10
-#define CAM_CC_CSI0PHYTIMER_CLK 11
-#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12
-#define CAM_CC_CSI1PHYTIMER_CLK 13
-#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14
-#define CAM_CC_CSI2PHYTIMER_CLK 15
-#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16
-#define CAM_CC_CSI3PHYTIMER_CLK 17
-#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18
-#define CAM_CC_CSIPHY0_CLK 19
-#define CAM_CC_CSIPHY1_CLK 20
-#define CAM_CC_CSIPHY2_CLK 21
-#define CAM_CC_CSIPHY3_CLK 22
-#define CAM_CC_FAST_AHB_CLK_SRC 23
-#define CAM_CC_FD_CORE_CLK 24
-#define CAM_CC_FD_CORE_CLK_SRC 25
-#define CAM_CC_FD_CORE_UAR_CLK 26
-#define CAM_CC_ICP_APB_CLK 27
-#define CAM_CC_ICP_ATB_CLK 28
-#define CAM_CC_ICP_CLK 29
-#define CAM_CC_ICP_CLK_SRC 30
-#define CAM_CC_ICP_CTI_CLK 31
-#define CAM_CC_ICP_TS_CLK 32
-#define CAM_CC_IFE_0_AXI_CLK 33
-#define CAM_CC_IFE_0_CLK 34
-#define CAM_CC_IFE_0_CLK_SRC 35
-#define CAM_CC_IFE_0_CPHY_RX_CLK 36
-#define CAM_CC_IFE_0_CSID_CLK 37
-#define CAM_CC_IFE_0_CSID_CLK_SRC 38
-#define CAM_CC_IFE_0_DSP_CLK 39
-#define CAM_CC_IFE_1_AXI_CLK 40
-#define CAM_CC_IFE_1_CLK 41
-#define CAM_CC_IFE_1_CLK_SRC 42
-#define CAM_CC_IFE_1_CPHY_RX_CLK 43
-#define CAM_CC_IFE_1_CSID_CLK 44
-#define CAM_CC_IFE_1_CSID_CLK_SRC 45
-#define CAM_CC_IFE_1_DSP_CLK 46
-#define CAM_CC_IFE_LITE_CLK 47
-#define CAM_CC_IFE_LITE_CLK_SRC 48
-#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49
-#define CAM_CC_IFE_LITE_CSID_CLK 50
-#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51
-#define CAM_CC_IPE_0_AHB_CLK 52
-#define CAM_CC_IPE_0_AREG_CLK 53
-#define CAM_CC_IPE_0_AXI_CLK 54
-#define CAM_CC_IPE_0_CLK 55
-#define CAM_CC_IPE_0_CLK_SRC 56
-#define CAM_CC_IPE_1_AHB_CLK 57
-#define CAM_CC_IPE_1_AREG_CLK 58
-#define CAM_CC_IPE_1_AXI_CLK 59
-#define CAM_CC_IPE_1_CLK 60
-#define CAM_CC_IPE_1_CLK_SRC 61
-#define CAM_CC_JPEG_CLK 62
-#define CAM_CC_JPEG_CLK_SRC 63
-#define CAM_CC_LRME_CLK 64
-#define CAM_CC_LRME_CLK_SRC 65
-#define CAM_CC_MCLK0_CLK 66
-#define CAM_CC_MCLK0_CLK_SRC 67
-#define CAM_CC_MCLK1_CLK 68
-#define CAM_CC_MCLK1_CLK_SRC 69
-#define CAM_CC_MCLK2_CLK 70
-#define CAM_CC_MCLK2_CLK_SRC 71
-#define CAM_CC_MCLK3_CLK 72
-#define CAM_CC_MCLK3_CLK_SRC 73
-#define CAM_CC_PLL0 74
-#define CAM_CC_PLL0_OUT_EVEN 75
-#define CAM_CC_PLL1 76
-#define CAM_CC_PLL1_OUT_EVEN 77
-#define CAM_CC_PLL2 78
-#define CAM_CC_PLL2_OUT_EVEN 79
-#define CAM_CC_PLL3 80
-#define CAM_CC_PLL3_OUT_EVEN 81
-#define CAM_CC_SLOW_AHB_CLK_SRC 82
-#define CAM_CC_SOC_AHB_CLK 83
-#define CAM_CC_SYS_TMR_CLK 84
-
-/* CAM_CC Resets */
-#define TITAN_CAM_CC_CCI_BCR 0
-#define TITAN_CAM_CC_CPAS_BCR 1
-#define TITAN_CAM_CC_CSI0PHY_BCR 2
-#define TITAN_CAM_CC_CSI1PHY_BCR 3
-#define TITAN_CAM_CC_CSI2PHY_BCR 4
-#define TITAN_CAM_CC_MCLK0_BCR 5
-#define TITAN_CAM_CC_MCLK1_BCR 6
-#define TITAN_CAM_CC_MCLK2_BCR 7
-#define TITAN_CAM_CC_MCLK3_BCR 8
-#define TITAN_CAM_CC_TITAN_TOP_BCR 9
-
-/* CAM_CC GDSCRs */
-#define BPS_GDSC 0
-#define IPE_0_GDSC 1
-#define IPE_1_GDSC 2
-#define IFE_0_GDSC 3
-#define IFE_1_GDSC 4
-#define TITAN_TOP_GDSC 5
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
deleted file mode 100644
index 4016fd1..0000000
--- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
-
-/* DISP_CC clock registers */
-#define DISP_CC_MDSS_AHB_CLK 0
-#define DISP_CC_MDSS_AXI_CLK 1
-#define DISP_CC_MDSS_BYTE0_CLK 2
-#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
-#define DISP_CC_MDSS_BYTE0_INTF_CLK 4
-#define DISP_CC_MDSS_BYTE1_CLK 5
-#define DISP_CC_MDSS_BYTE1_CLK_SRC 6
-#define DISP_CC_MDSS_BYTE1_INTF_CLK 7
-#define DISP_CC_MDSS_ESC0_CLK 8
-#define DISP_CC_MDSS_ESC0_CLK_SRC 9
-#define DISP_CC_MDSS_ESC1_CLK 10
-#define DISP_CC_MDSS_ESC1_CLK_SRC 11
-#define DISP_CC_MDSS_MDP_CLK 12
-#define DISP_CC_MDSS_MDP_CLK_SRC 13
-#define DISP_CC_MDSS_MDP_LUT_CLK 14
-#define DISP_CC_MDSS_PCLK0_CLK 15
-#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
-#define DISP_CC_MDSS_PCLK1_CLK 17
-#define DISP_CC_MDSS_PCLK1_CLK_SRC 18
-#define DISP_CC_MDSS_ROT_CLK 19
-#define DISP_CC_MDSS_ROT_CLK_SRC 20
-#define DISP_CC_MDSS_RSCC_AHB_CLK 21
-#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22
-#define DISP_CC_MDSS_VSYNC_CLK 23
-#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
-#define DISP_CC_PLL0 25
-#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26
-#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27
-#define DISP_CC_MDSS_DP_AUX_CLK 28
-#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29
-#define DISP_CC_MDSS_DP_CRYPTO_CLK 30
-#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31
-#define DISP_CC_MDSS_DP_LINK_CLK 32
-#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33
-#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34
-#define DISP_CC_MDSS_DP_PIXEL1_CLK 35
-#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36
-#define DISP_CC_MDSS_DP_PIXEL_CLK 37
-#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38
-
-/* DISP_CC Reset */
-#define DISP_CC_MDSS_RSCC_BCR 0
-
-/* DISP_CC GDSCR */
-#define MDSS_GDSC 0
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
deleted file mode 100644
index 5630344..0000000
--- a/include/dt-bindings/clock/qcom,gcc-msm8916.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2015 Linaro Limited
- */
-
-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
-#define _DT_BINDINGS_CLK_MSM_GCC_8916_H
-
-#define GPLL0 0
-#define GPLL0_VOTE 1
-#define BIMC_PLL 2
-#define BIMC_PLL_VOTE 3
-#define GPLL1 4
-#define GPLL1_VOTE 5
-#define GPLL2 6
-#define GPLL2_VOTE 7
-#define PCNOC_BFDCD_CLK_SRC 8
-#define SYSTEM_NOC_BFDCD_CLK_SRC 9
-#define CAMSS_AHB_CLK_SRC 10
-#define APSS_AHB_CLK_SRC 11
-#define CSI0_CLK_SRC 12
-#define CSI1_CLK_SRC 13
-#define GFX3D_CLK_SRC 14
-#define VFE0_CLK_SRC 15
-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16
-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17
-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18
-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20
-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21
-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22
-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23
-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24
-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25
-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26
-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27
-#define BLSP1_UART1_APPS_CLK_SRC 28
-#define BLSP1_UART2_APPS_CLK_SRC 29
-#define CCI_CLK_SRC 30
-#define CAMSS_GP0_CLK_SRC 31
-#define CAMSS_GP1_CLK_SRC 32
-#define JPEG0_CLK_SRC 33
-#define MCLK0_CLK_SRC 34
-#define MCLK1_CLK_SRC 35
-#define CSI0PHYTIMER_CLK_SRC 36
-#define CSI1PHYTIMER_CLK_SRC 37
-#define CPP_CLK_SRC 38
-#define CRYPTO_CLK_SRC 39
-#define GP1_CLK_SRC 40
-#define GP2_CLK_SRC 41
-#define GP3_CLK_SRC 42
-#define BYTE0_CLK_SRC 43
-#define ESC0_CLK_SRC 44
-#define MDP_CLK_SRC 45
-#define PCLK0_CLK_SRC 46
-#define VSYNC_CLK_SRC 47
-#define PDM2_CLK_SRC 48
-#define SDCC1_APPS_CLK_SRC 49
-#define SDCC2_APPS_CLK_SRC 50
-#define APSS_TCU_CLK_SRC 51
-#define USB_HS_SYSTEM_CLK_SRC 52
-#define VCODEC0_CLK_SRC 53
-#define GCC_BLSP1_AHB_CLK 54
-#define GCC_BLSP1_SLEEP_CLK 55
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63
-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64
-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65
-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66
-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67
-#define GCC_BLSP1_UART1_APPS_CLK 68
-#define GCC_BLSP1_UART2_APPS_CLK 69
-#define GCC_BOOT_ROM_AHB_CLK 70
-#define GCC_CAMSS_CCI_AHB_CLK 71
-#define GCC_CAMSS_CCI_CLK 72
-#define GCC_CAMSS_CSI0_AHB_CLK 73
-#define GCC_CAMSS_CSI0_CLK 74
-#define GCC_CAMSS_CSI0PHY_CLK 75
-#define GCC_CAMSS_CSI0PIX_CLK 76
-#define GCC_CAMSS_CSI0RDI_CLK 77
-#define GCC_CAMSS_CSI1_AHB_CLK 78
-#define GCC_CAMSS_CSI1_CLK 79
-#define GCC_CAMSS_CSI1PHY_CLK 80
-#define GCC_CAMSS_CSI1PIX_CLK 81
-#define GCC_CAMSS_CSI1RDI_CLK 82
-#define GCC_CAMSS_CSI_VFE0_CLK 83
-#define GCC_CAMSS_GP0_CLK 84
-#define GCC_CAMSS_GP1_CLK 85
-#define GCC_CAMSS_ISPIF_AHB_CLK 86
-#define GCC_CAMSS_JPEG0_CLK 87
-#define GCC_CAMSS_JPEG_AHB_CLK 88
-#define GCC_CAMSS_JPEG_AXI_CLK 89
-#define GCC_CAMSS_MCLK0_CLK 90
-#define GCC_CAMSS_MCLK1_CLK 91
-#define GCC_CAMSS_MICRO_AHB_CLK 92
-#define GCC_CAMSS_CSI0PHYTIMER_CLK 93
-#define GCC_CAMSS_CSI1PHYTIMER_CLK 94
-#define GCC_CAMSS_AHB_CLK 95
-#define GCC_CAMSS_TOP_AHB_CLK 96
-#define GCC_CAMSS_CPP_AHB_CLK 97
-#define GCC_CAMSS_CPP_CLK 98
-#define GCC_CAMSS_VFE0_CLK 99
-#define GCC_CAMSS_VFE_AHB_CLK 100
-#define GCC_CAMSS_VFE_AXI_CLK 101
-#define GCC_CRYPTO_AHB_CLK 102
-#define GCC_CRYPTO_AXI_CLK 103
-#define GCC_CRYPTO_CLK 104
-#define GCC_OXILI_GMEM_CLK 105
-#define GCC_GP1_CLK 106
-#define GCC_GP2_CLK 107
-#define GCC_GP3_CLK 108
-#define GCC_MDSS_AHB_CLK 109
-#define GCC_MDSS_AXI_CLK 110
-#define GCC_MDSS_BYTE0_CLK 111
-#define GCC_MDSS_ESC0_CLK 112
-#define GCC_MDSS_MDP_CLK 113
-#define GCC_MDSS_PCLK0_CLK 114
-#define GCC_MDSS_VSYNC_CLK 115
-#define GCC_MSS_CFG_AHB_CLK 116
-#define GCC_OXILI_AHB_CLK 117
-#define GCC_OXILI_GFX3D_CLK 118
-#define GCC_PDM2_CLK 119
-#define GCC_PDM_AHB_CLK 120
-#define GCC_PRNG_AHB_CLK 121
-#define GCC_SDCC1_AHB_CLK 122
-#define GCC_SDCC1_APPS_CLK 123
-#define GCC_SDCC2_AHB_CLK 124
-#define GCC_SDCC2_APPS_CLK 125
-#define GCC_GTCU_AHB_CLK 126
-#define GCC_JPEG_TBU_CLK 127
-#define GCC_MDP_TBU_CLK 128
-#define GCC_SMMU_CFG_CLK 129
-#define GCC_VENUS_TBU_CLK 130
-#define GCC_VFE_TBU_CLK 131
-#define GCC_USB2A_PHY_SLEEP_CLK 132
-#define GCC_USB_HS_AHB_CLK 133
-#define GCC_USB_HS_SYSTEM_CLK 134
-#define GCC_VENUS0_AHB_CLK 135
-#define GCC_VENUS0_AXI_CLK 136
-#define GCC_VENUS0_VCODEC0_CLK 137
-#define BIMC_DDR_CLK_SRC 138
-#define GCC_APSS_TCU_CLK 139
-#define GCC_GFX_TCU_CLK 140
-#define BIMC_GPU_CLK_SRC 141
-#define GCC_BIMC_GFX_CLK 142
-#define GCC_BIMC_GPU_CLK 143
-#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144
-#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145
-#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146
-#define ULTAUDIO_XO_CLK_SRC 147
-#define ULTAUDIO_AHBFABRIC_CLK_SRC 148
-#define CODEC_DIGCODEC_CLK_SRC 149
-#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150
-#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151
-#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152
-#define GCC_ULTAUDIO_STC_XO_CLK 153
-#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154
-#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155
-#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156
-#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157
-#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158
-#define GCC_CODEC_DIGCODEC_CLK 159
-#define GCC_MSS_Q6_BIMC_AXI_CLK 160
-
-/* Indexes for GDSCs */
-#define BIMC_GDSC 0
-#define VENUS_GDSC 1
-#define MDSS_GDSC 2
-#define JPEG_GDSC 3
-#define VFE_GDSC 4
-#define OXILI_GDSC 5
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
deleted file mode 100644
index de5c36c..0000000
--- a/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
-#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
-
-#define GPLL0_EARLY 0
-#define GPLL0 1
-#define GPLL1_EARLY 2
-#define GPLL1 3
-#define GPLL2_EARLY 4
-#define GPLL2 5
-#define GPLL3_EARLY 6
-#define GPLL3 7
-#define GPLL4_EARLY 8
-#define GPLL4 9
-#define SYSTEM_NOC_CLK_SRC 10
-/* U-Boot: KConfig check in CI erroneously picks this up, it's unused
- * anyway so comment it out for now
- */
-//#define CONFIG _NOC_CLK_SRC 11
-#define PERIPH_NOC_CLK_SRC 12
-#define MMSS_BIMC_GFX_CLK_SRC 13
-#define USB30_MASTER_CLK_SRC 14
-#define USB30_MOCK_UTMI_CLK_SRC 15
-#define USB3_PHY_AUX_CLK_SRC 16
-#define USB20_MASTER_CLK_SRC 17
-#define USB20_MOCK_UTMI_CLK_SRC 18
-#define SDCC1_APPS_CLK_SRC 19
-#define SDCC1_ICE_CORE_CLK_SRC 20
-#define SDCC2_APPS_CLK_SRC 21
-#define SDCC3_APPS_CLK_SRC 22
-#define SDCC4_APPS_CLK_SRC 23
-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24
-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25
-#define BLSP1_UART1_APPS_CLK_SRC 26
-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27
-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28
-#define BLSP1_UART2_APPS_CLK_SRC 29
-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30
-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31
-#define BLSP1_UART3_APPS_CLK_SRC 32
-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33
-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34
-#define BLSP1_UART4_APPS_CLK_SRC 35
-#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36
-#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37
-#define BLSP1_UART5_APPS_CLK_SRC 38
-#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39
-#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40
-#define BLSP1_UART6_APPS_CLK_SRC 41
-#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42
-#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43
-#define BLSP2_UART1_APPS_CLK_SRC 44
-#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45
-#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46
-#define BLSP2_UART2_APPS_CLK_SRC 47
-#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48
-#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49
-#define BLSP2_UART3_APPS_CLK_SRC 50
-#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51
-#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52
-#define BLSP2_UART4_APPS_CLK_SRC 53
-#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54
-#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55
-#define BLSP2_UART5_APPS_CLK_SRC 56
-#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57
-#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58
-#define BLSP2_UART6_APPS_CLK_SRC 59
-#define PDM2_CLK_SRC 60
-#define TSIF_REF_CLK_SRC 61
-#define CE1_CLK_SRC 62
-#define GCC_SLEEP_CLK_SRC 63
-#define BIMC_CLK_SRC 64
-#define HMSS_AHB_CLK_SRC 65
-#define BIMC_HMSS_AXI_CLK_SRC 66
-#define HMSS_RBCPR_CLK_SRC 67
-#define HMSS_GPLL0_CLK_SRC 68
-#define GP1_CLK_SRC 69
-#define GP2_CLK_SRC 70
-#define GP3_CLK_SRC 71
-#define PCIE_AUX_CLK_SRC 72
-#define UFS_AXI_CLK_SRC 73
-#define UFS_ICE_CORE_CLK_SRC 74
-#define QSPI_SER_CLK_SRC 75
-#define GCC_SYS_NOC_AXI_CLK 76
-#define GCC_SYS_NOC_HMSS_AHB_CLK 77
-#define GCC_SNOC_CNOC_AHB_CLK 78
-#define GCC_SNOC_PNOC_AHB_CLK 79
-#define GCC_SYS_NOC_AT_CLK 80
-#define GCC_SYS_NOC_USB3_AXI_CLK 81
-#define GCC_SYS_NOC_UFS_AXI_CLK 82
-#define GCC_CFG_NOC_AHB_CLK 83
-#define GCC_PERIPH_NOC_AHB_CLK 84
-#define GCC_PERIPH_NOC_USB20_AHB_CLK 85
-#define GCC_TIC_CLK 86
-#define GCC_IMEM_AXI_CLK 87
-#define GCC_MMSS_SYS_NOC_AXI_CLK 88
-#define GCC_MMSS_NOC_CFG_AHB_CLK 89
-#define GCC_MMSS_BIMC_GFX_CLK 90
-#define GCC_USB30_MASTER_CLK 91
-#define GCC_USB30_SLEEP_CLK 92
-#define GCC_USB30_MOCK_UTMI_CLK 93
-#define GCC_USB3_PHY_AUX_CLK 94
-#define GCC_USB3_PHY_PIPE_CLK 95
-#define GCC_USB20_MASTER_CLK 96
-#define GCC_USB20_SLEEP_CLK 97
-#define GCC_USB20_MOCK_UTMI_CLK 98
-#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
-#define GCC_SDCC1_APPS_CLK 100
-#define GCC_SDCC1_AHB_CLK 101
-#define GCC_SDCC1_ICE_CORE_CLK 102
-#define GCC_SDCC2_APPS_CLK 103
-#define GCC_SDCC2_AHB_CLK 104
-#define GCC_SDCC3_APPS_CLK 105
-#define GCC_SDCC3_AHB_CLK 106
-#define GCC_SDCC4_APPS_CLK 107
-#define GCC_SDCC4_AHB_CLK 108
-#define GCC_BLSP1_AHB_CLK 109
-#define GCC_BLSP1_SLEEP_CLK 110
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112
-#define GCC_BLSP1_UART1_APPS_CLK 113
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115
-#define GCC_BLSP1_UART2_APPS_CLK 116
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118
-#define GCC_BLSP1_UART3_APPS_CLK 119
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121
-#define GCC_BLSP1_UART4_APPS_CLK 122
-#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123
-#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124
-#define GCC_BLSP1_UART5_APPS_CLK 125
-#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126
-#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127
-#define GCC_BLSP1_UART6_APPS_CLK 128
-#define GCC_BLSP2_AHB_CLK 129
-#define GCC_BLSP2_SLEEP_CLK 130
-#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131
-#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132
-#define GCC_BLSP2_UART1_APPS_CLK 133
-#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134
-#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135
-#define GCC_BLSP2_UART2_APPS_CLK 136
-#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137
-#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138
-#define GCC_BLSP2_UART3_APPS_CLK 139
-#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140
-#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141
-#define GCC_BLSP2_UART4_APPS_CLK 142
-#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143
-#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144
-#define GCC_BLSP2_UART5_APPS_CLK 145
-#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146
-#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147
-#define GCC_BLSP2_UART6_APPS_CLK 148
-#define GCC_PDM_AHB_CLK 149
-#define GCC_PDM_XO4_CLK 150
-#define GCC_PDM2_CLK 151
-#define GCC_PRNG_AHB_CLK 152
-#define GCC_TSIF_AHB_CLK 153
-#define GCC_TSIF_REF_CLK 154
-#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155
-#define GCC_TCSR_AHB_CLK 156
-#define GCC_BOOT_ROM_AHB_CLK 157
-#define GCC_MSG_RAM_AHB_CLK 158
-#define GCC_TLMM_AHB_CLK 159
-#define GCC_TLMM_CLK 160
-#define GCC_MPM_AHB_CLK 161
-#define GCC_SPMI_SER_CLK 162
-#define GCC_SPMI_CNOC_AHB_CLK 163
-#define GCC_CE1_CLK 164
-#define GCC_CE1_AXI_CLK 165
-#define GCC_CE1_AHB_CLK 166
-#define GCC_BIMC_HMSS_AXI_CLK 167
-#define GCC_BIMC_GFX_CLK 168
-#define GCC_HMSS_AHB_CLK 169
-#define GCC_HMSS_SLV_AXI_CLK 170
-#define GCC_HMSS_MSTR_AXI_CLK 171
-#define GCC_HMSS_RBCPR_CLK 172
-#define GCC_GP1_CLK 173
-#define GCC_GP2_CLK 174
-#define GCC_GP3_CLK 175
-#define GCC_PCIE_0_SLV_AXI_CLK 176
-#define GCC_PCIE_0_MSTR_AXI_CLK 177
-#define GCC_PCIE_0_CFG_AHB_CLK 178
-#define GCC_PCIE_0_AUX_CLK 179
-#define GCC_PCIE_0_PIPE_CLK 180
-#define GCC_PCIE_1_SLV_AXI_CLK 181
-#define GCC_PCIE_1_MSTR_AXI_CLK 182
-#define GCC_PCIE_1_CFG_AHB_CLK 183
-#define GCC_PCIE_1_AUX_CLK 184
-#define GCC_PCIE_1_PIPE_CLK 185
-#define GCC_PCIE_2_SLV_AXI_CLK 186
-#define GCC_PCIE_2_MSTR_AXI_CLK 187
-#define GCC_PCIE_2_CFG_AHB_CLK 188
-#define GCC_PCIE_2_AUX_CLK 189
-#define GCC_PCIE_2_PIPE_CLK 190
-#define GCC_PCIE_PHY_CFG_AHB_CLK 191
-#define GCC_PCIE_PHY_AUX_CLK 192
-#define GCC_UFS_AXI_CLK 193
-#define GCC_UFS_AHB_CLK 194
-#define GCC_UFS_TX_CFG_CLK 195
-#define GCC_UFS_RX_CFG_CLK 196
-#define GCC_UFS_TX_SYMBOL_0_CLK 197
-#define GCC_UFS_RX_SYMBOL_0_CLK 198
-#define GCC_UFS_RX_SYMBOL_1_CLK 199
-#define GCC_UFS_UNIPRO_CORE_CLK 200
-#define GCC_UFS_ICE_CORE_CLK 201
-#define GCC_UFS_SYS_CLK_CORE_CLK 202
-#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203
-#define GCC_AGGRE0_SNOC_AXI_CLK 204
-#define GCC_AGGRE0_CNOC_AHB_CLK 205
-#define GCC_SMMU_AGGRE0_AXI_CLK 206
-#define GCC_SMMU_AGGRE0_AHB_CLK 207
-#define GCC_AGGRE1_PNOC_AHB_CLK 208
-#define GCC_AGGRE2_UFS_AXI_CLK 209
-#define GCC_AGGRE2_USB3_AXI_CLK 210
-#define GCC_QSPI_AHB_CLK 211
-#define GCC_QSPI_SER_CLK 212
-#define GCC_USB3_CLKREF_CLK 213
-#define GCC_HDMI_CLKREF_CLK 214
-#define GCC_UFS_CLKREF_CLK 215
-#define GCC_PCIE_CLKREF_CLK 216
-#define GCC_RX2_USB2_CLKREF_CLK 217
-#define GCC_RX1_USB2_CLKREF_CLK 218
-#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219
-#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220
-#define GCC_EDP_CLKREF_CLK 221
-#define GCC_MSS_CFG_AHB_CLK 222
-#define GCC_MSS_Q6_BIMC_AXI_CLK 223
-#define GCC_MSS_SNOC_AXI_CLK 224
-#define GCC_MSS_MNOC_BIMC_AXI_CLK 225
-#define GCC_DCC_AHB_CLK 226
-#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227
-#define GCC_MMSS_GPLL0_DIV_CLK 228
-#define GCC_MSS_GPLL0_DIV_CLK 229
-
-#define GCC_SYSTEM_NOC_BCR 0
-#define GCC_CONFIG_NOC_BCR 1
-#define GCC_PERIPH_NOC_BCR 2
-#define GCC_IMEM_BCR 3
-#define GCC_MMSS_BCR 4
-#define GCC_PIMEM_BCR 5
-#define GCC_QDSS_BCR 6
-#define GCC_USB_30_BCR 7
-#define GCC_USB_20_BCR 8
-#define GCC_QUSB2PHY_PRIM_BCR 9
-#define GCC_QUSB2PHY_SEC_BCR 10
-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11
-#define GCC_SDCC1_BCR 12
-#define GCC_SDCC2_BCR 13
-#define GCC_SDCC3_BCR 14
-#define GCC_SDCC4_BCR 15
-#define GCC_BLSP1_BCR 16
-#define GCC_BLSP1_QUP1_BCR 17
-#define GCC_BLSP1_UART1_BCR 18
-#define GCC_BLSP1_QUP2_BCR 19
-#define GCC_BLSP1_UART2_BCR 20
-#define GCC_BLSP1_QUP3_BCR 21
-#define GCC_BLSP1_UART3_BCR 22
-#define GCC_BLSP1_QUP4_BCR 23
-#define GCC_BLSP1_UART4_BCR 24
-#define GCC_BLSP1_QUP5_BCR 25
-#define GCC_BLSP1_UART5_BCR 26
-#define GCC_BLSP1_QUP6_BCR 27
-#define GCC_BLSP1_UART6_BCR 28
-#define GCC_BLSP2_BCR 29
-#define GCC_BLSP2_QUP1_BCR 30
-#define GCC_BLSP2_UART1_BCR 31
-#define GCC_BLSP2_QUP2_BCR 32
-#define GCC_BLSP2_UART2_BCR 33
-#define GCC_BLSP2_QUP3_BCR 34
-#define GCC_BLSP2_UART3_BCR 35
-#define GCC_BLSP2_QUP4_BCR 36
-#define GCC_BLSP2_UART4_BCR 37
-#define GCC_BLSP2_QUP5_BCR 38
-#define GCC_BLSP2_UART5_BCR 39
-#define GCC_BLSP2_QUP6_BCR 40
-#define GCC_BLSP2_UART6_BCR 41
-#define GCC_PDM_BCR 42
-#define GCC_PRNG_BCR 43
-#define GCC_TSIF_BCR 44
-#define GCC_TCSR_BCR 45
-#define GCC_BOOT_ROM_BCR 46
-#define GCC_MSG_RAM_BCR 47
-#define GCC_TLMM_BCR 48
-#define GCC_MPM_BCR 49
-#define GCC_SEC_CTRL_BCR 50
-#define GCC_SPMI_BCR 51
-#define GCC_SPDM_BCR 52
-#define GCC_CE1_BCR 53
-#define GCC_BIMC_BCR 54
-#define GCC_SNOC_BUS_TIMEOUT0_BCR 55
-#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
-#define GCC_SNOC_BUS_TIMEOUT1_BCR 57
-#define GCC_SNOC_BUS_TIMEOUT3_BCR 58
-#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59
-#define GCC_PNOC_BUS_TIMEOUT0_BCR 60
-#define GCC_PNOC_BUS_TIMEOUT1_BCR 61
-#define GCC_PNOC_BUS_TIMEOUT2_BCR 62
-#define GCC_PNOC_BUS_TIMEOUT3_BCR 63
-#define GCC_PNOC_BUS_TIMEOUT4_BCR 64
-#define GCC_CNOC_BUS_TIMEOUT0_BCR 65
-#define GCC_CNOC_BUS_TIMEOUT1_BCR 66
-#define GCC_CNOC_BUS_TIMEOUT2_BCR 67
-#define GCC_CNOC_BUS_TIMEOUT3_BCR 68
-#define GCC_CNOC_BUS_TIMEOUT4_BCR 69
-#define GCC_CNOC_BUS_TIMEOUT5_BCR 70
-#define GCC_CNOC_BUS_TIMEOUT6_BCR 71
-#define GCC_CNOC_BUS_TIMEOUT7_BCR 72
-#define GCC_CNOC_BUS_TIMEOUT8_BCR 73
-#define GCC_CNOC_BUS_TIMEOUT9_BCR 74
-#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75
-#define GCC_APB2JTAG_BCR 76
-#define GCC_RBCPR_CX_BCR 77
-#define GCC_RBCPR_MX_BCR 78
-#define GCC_PCIE_0_BCR 79
-#define GCC_PCIE_0_PHY_BCR 80
-#define GCC_PCIE_1_BCR 81
-#define GCC_PCIE_1_PHY_BCR 82
-#define GCC_PCIE_2_BCR 83
-#define GCC_PCIE_2_PHY_BCR 84
-#define GCC_PCIE_PHY_BCR 85
-#define GCC_DCD_BCR 86
-#define GCC_OBT_ODT_BCR 87
-#define GCC_UFS_BCR 88
-#define GCC_SSC_BCR 89
-#define GCC_VS_BCR 90
-#define GCC_AGGRE0_NOC_BCR 91
-#define GCC_AGGRE1_NOC_BCR 92
-#define GCC_AGGRE2_NOC_BCR 93
-#define GCC_DCC_BCR 94
-#define GCC_IPA_BCR 95
-#define GCC_QSPI_BCR 96
-#define GCC_SKL_BCR 97
-#define GCC_MSMPU_BCR 98
-#define GCC_MSS_Q6_BCR 99
-#define GCC_QREFS_VBG_CAL_BCR 100
-#define GCC_PCIE_PHY_COM_BCR 101
-#define GCC_PCIE_PHY_COM_NOCSR_BCR 102
-#define GCC_USB3_PHY_BCR 103
-#define GCC_USB3PHY_PHY_BCR 104
-#define GCC_MSS_RESTART 105
-
-/* Indexes for GDSCs */
-#define AGGRE0_NOC_GDSC 0
-#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1
-#define HLOS1_VOTE_LPASS_ADSP_GDSC 2
-#define HLOS1_VOTE_LPASS_CORE_GDSC 3
-#define USB30_GDSC 4
-#define PCIE0_GDSC 5
-#define PCIE1_GDSC 6
-#define PCIE2_GDSC 7
-#define UFS_GDSC 8
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
deleted file mode 100644
index bc30515..0000000
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
-#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
-
-#define GCC_APSS_AHB_CLK_SRC 0
-#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1
-#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10
-#define GCC_BLSP1_UART0_APPS_CLK_SRC 11
-#define GCC_BLSP1_UART1_APPS_CLK_SRC 12
-#define GCC_BLSP1_UART2_APPS_CLK_SRC 13
-#define GCC_BLSP1_UART3_APPS_CLK_SRC 14
-#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15
-#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16
-#define GCC_BLSP2_UART0_APPS_CLK_SRC 17
-#define GCC_BYTE0_CLK_SRC 18
-#define GCC_EMAC_CLK_SRC 19
-#define GCC_EMAC_PTP_CLK_SRC 20
-#define GCC_ESC0_CLK_SRC 21
-#define GCC_APSS_AHB_CLK 22
-#define GCC_APSS_AXI_CLK 23
-#define GCC_BIMC_APSS_AXI_CLK 24
-#define GCC_BIMC_GFX_CLK 25
-#define GCC_BIMC_MDSS_CLK 26
-#define GCC_BLSP1_AHB_CLK 27
-#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28
-#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37
-#define GCC_BLSP1_UART0_APPS_CLK 38
-#define GCC_BLSP1_UART1_APPS_CLK 39
-#define GCC_BLSP1_UART2_APPS_CLK 40
-#define GCC_BLSP1_UART3_APPS_CLK 41
-#define GCC_BLSP2_AHB_CLK 42
-#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43
-#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44
-#define GCC_BLSP2_UART0_APPS_CLK 45
-#define GCC_BOOT_ROM_AHB_CLK 46
-#define GCC_DCC_CLK 47
-#define GCC_GENI_IR_H_CLK 48
-#define GCC_ETH_AXI_CLK 49
-#define GCC_ETH_PTP_CLK 50
-#define GCC_ETH_RGMII_CLK 51
-#define GCC_ETH_SLAVE_AHB_CLK 52
-#define GCC_GENI_IR_S_CLK 53
-#define GCC_GP1_CLK 54
-#define GCC_GP2_CLK 55
-#define GCC_GP3_CLK 56
-#define GCC_MDSS_AHB_CLK 57
-#define GCC_MDSS_AXI_CLK 58
-#define GCC_MDSS_BYTE0_CLK 59
-#define GCC_MDSS_ESC0_CLK 60
-#define GCC_MDSS_HDMI_APP_CLK 61
-#define GCC_MDSS_HDMI_PCLK_CLK 62
-#define GCC_MDSS_MDP_CLK 63
-#define GCC_MDSS_PCLK0_CLK 64
-#define GCC_MDSS_VSYNC_CLK 65
-#define GCC_OXILI_AHB_CLK 66
-#define GCC_OXILI_GFX3D_CLK 67
-#define GCC_PCIE_0_AUX_CLK 68
-#define GCC_PCIE_0_CFG_AHB_CLK 69
-#define GCC_PCIE_0_MSTR_AXI_CLK 70
-#define GCC_PCIE_0_PIPE_CLK 71
-#define GCC_PCIE_0_SLV_AXI_CLK 72
-#define GCC_PCNOC_USB2_CLK 73
-#define GCC_PCNOC_USB3_CLK 74
-#define GCC_PDM2_CLK 75
-#define GCC_PDM_AHB_CLK 76
-#define GCC_VSYNC_CLK_SRC 77
-#define GCC_PRNG_AHB_CLK 78
-#define GCC_PWM0_XO512_CLK 79
-#define GCC_PWM1_XO512_CLK 80
-#define GCC_PWM2_XO512_CLK 81
-#define GCC_SDCC1_AHB_CLK 82
-#define GCC_SDCC1_APPS_CLK 83
-#define GCC_SDCC1_ICE_CORE_CLK 84
-#define GCC_SDCC2_AHB_CLK 85
-#define GCC_SDCC2_APPS_CLK 86
-#define GCC_SYS_NOC_USB3_CLK 87
-#define GCC_USB20_MOCK_UTMI_CLK 88
-#define GCC_USB2A_PHY_SLEEP_CLK 89
-#define GCC_USB30_MASTER_CLK 90
-#define GCC_USB30_MOCK_UTMI_CLK 91
-#define GCC_USB30_SLEEP_CLK 92
-#define GCC_USB3_PHY_AUX_CLK 93
-#define GCC_USB3_PHY_PIPE_CLK 94
-#define GCC_USB_HS_PHY_CFG_AHB_CLK 95
-#define GCC_USB_HS_SYSTEM_CLK 96
-#define GCC_GFX3D_CLK_SRC 97
-#define GCC_GP1_CLK_SRC 98
-#define GCC_GP2_CLK_SRC 99
-#define GCC_GP3_CLK_SRC 100
-#define GCC_GPLL0_OUT_MAIN 101
-#define GCC_GPLL1_OUT_MAIN 102
-#define GCC_GPLL3_OUT_MAIN 103
-#define GCC_GPLL4_OUT_MAIN 104
-#define GCC_HDMI_APP_CLK_SRC 105
-#define GCC_HDMI_PCLK_CLK_SRC 106
-#define GCC_MDP_CLK_SRC 107
-#define GCC_PCIE_0_AUX_CLK_SRC 108
-#define GCC_PCIE_0_PIPE_CLK_SRC 109
-#define GCC_PCLK0_CLK_SRC 110
-#define GCC_PDM2_CLK_SRC 111
-#define GCC_SDCC1_APPS_CLK_SRC 112
-#define GCC_SDCC1_ICE_CORE_CLK_SRC 113
-#define GCC_SDCC2_APPS_CLK_SRC 114
-#define GCC_USB20_MOCK_UTMI_CLK_SRC 115
-#define GCC_USB30_MASTER_CLK_SRC 116
-#define GCC_USB30_MOCK_UTMI_CLK_SRC 117
-#define GCC_USB3_PHY_AUX_CLK_SRC 118
-#define GCC_USB_HS_SYSTEM_CLK_SRC 119
-#define GCC_GPLL0_AO_CLK_SRC 120
-#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122
-#define GCC_GPLL0_AO_OUT_MAIN 123
-#define GCC_GPLL0_SLEEP_CLK_SRC 124
-#define GCC_GPLL6 125
-#define GCC_GPLL6_OUT_AUX 126
-#define GCC_MDSS_MDP_VOTE_CLK 127
-#define GCC_MDSS_ROTATOR_VOTE_CLK 128
-#define GCC_BIMC_GPU_CLK 129
-#define GCC_GTCU_AHB_CLK 130
-#define GCC_GFX_TCU_CLK 131
-#define GCC_GFX_TBU_CLK 132
-#define GCC_SMMU_CFG_CLK 133
-#define GCC_APSS_TCU_CLK 134
-#define GCC_CRYPTO_AHB_CLK 135
-#define GCC_CRYPTO_AXI_CLK 136
-#define GCC_CRYPTO_CLK 137
-#define GCC_MDP_TBU_CLK 138
-#define GCC_QDSS_DAP_CLK 139
-#define GCC_DCC_XO_CLK 140
-#define GCC_WCSS_Q6_AHB_CLK 141
-#define GCC_WCSS_Q6_AXIM_CLK 142
-#define GCC_CDSP_CFG_AHB_CLK 143
-#define GCC_BIMC_CDSP_CLK 144
-#define GCC_CDSP_TBU_CLK 145
-#define GCC_CDSP_BIMC_CLK_SRC 146
-
-#define GCC_GENI_IR_BCR 0
-#define GCC_USB_HS_BCR 1
-#define GCC_USB2_HS_PHY_ONLY_BCR 2
-#define GCC_QUSB2_PHY_BCR 3
-#define GCC_USB_HS_PHY_CFG_AHB_BCR 4
-#define GCC_USB2A_PHY_BCR 5
-#define GCC_USB3_PHY_BCR 6
-#define GCC_USB_30_BCR 7
-#define GCC_USB3PHY_PHY_BCR 8
-#define GCC_PCIE_0_BCR 9
-#define GCC_PCIE_0_PHY_BCR 10
-#define GCC_PCIE_0_LINK_DOWN_BCR 11
-#define GCC_PCIEPHY_0_PHY_BCR 12
-#define GCC_EMAC_BCR 13
-#define GCC_CDSP_RESTART 14
-#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15
-#define GCC_PCIE_0_AHB_ARES 16
-#define GCC_PCIE_0_AXI_SLAVE_ARES 17
-#define GCC_PCIE_0_AXI_MASTER_ARES 18
-#define GCC_PCIE_0_CORE_STICKY_ARES 19
-#define GCC_PCIE_0_SLEEP_ARES 20
-#define GCC_PCIE_0_PIPE_ARES 21
-#define GCC_WDSP_RESTART 22
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h
deleted file mode 100644
index 968fa65..0000000
--- a/include/dt-bindings/clock/qcom,gcc-sdm845.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
-
-/* GCC clock registers */
-#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
-#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
-#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
-#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
-#define GCC_AGGRE_USB3_SEC_AXI_CLK 4
-#define GCC_BOOT_ROM_AHB_CLK 5
-#define GCC_CAMERA_AHB_CLK 6
-#define GCC_CAMERA_AXI_CLK 7
-#define GCC_CAMERA_XO_CLK 8
-#define GCC_CE1_AHB_CLK 9
-#define GCC_CE1_AXI_CLK 10
-#define GCC_CE1_CLK 11
-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
-#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
-#define GCC_CPUSS_AHB_CLK 14
-#define GCC_CPUSS_AHB_CLK_SRC 15
-#define GCC_CPUSS_RBCPR_CLK 16
-#define GCC_CPUSS_RBCPR_CLK_SRC 17
-#define GCC_DDRSS_GPU_AXI_CLK 18
-#define GCC_DISP_AHB_CLK 19
-#define GCC_DISP_AXI_CLK 20
-#define GCC_DISP_GPLL0_CLK_SRC 21
-#define GCC_DISP_GPLL0_DIV_CLK_SRC 22
-#define GCC_DISP_XO_CLK 23
-#define GCC_GP1_CLK 24
-#define GCC_GP1_CLK_SRC 25
-#define GCC_GP2_CLK 26
-#define GCC_GP2_CLK_SRC 27
-#define GCC_GP3_CLK 28
-#define GCC_GP3_CLK_SRC 29
-#define GCC_GPU_CFG_AHB_CLK 30
-#define GCC_GPU_GPLL0_CLK_SRC 31
-#define GCC_GPU_GPLL0_DIV_CLK_SRC 32
-#define GCC_GPU_MEMNOC_GFX_CLK 33
-#define GCC_GPU_SNOC_DVM_GFX_CLK 34
-#define GCC_MSS_AXIS2_CLK 35
-#define GCC_MSS_CFG_AHB_CLK 36
-#define GCC_MSS_GPLL0_DIV_CLK_SRC 37
-#define GCC_MSS_MFAB_AXIS_CLK 38
-#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39
-#define GCC_MSS_SNOC_AXI_CLK 40
-#define GCC_PCIE_0_AUX_CLK 41
-#define GCC_PCIE_0_AUX_CLK_SRC 42
-#define GCC_PCIE_0_CFG_AHB_CLK 43
-#define GCC_PCIE_0_CLKREF_CLK 44
-#define GCC_PCIE_0_MSTR_AXI_CLK 45
-#define GCC_PCIE_0_PIPE_CLK 46
-#define GCC_PCIE_0_SLV_AXI_CLK 47
-#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
-#define GCC_PCIE_1_AUX_CLK 49
-#define GCC_PCIE_1_AUX_CLK_SRC 50
-#define GCC_PCIE_1_CFG_AHB_CLK 51
-#define GCC_PCIE_1_CLKREF_CLK 52
-#define GCC_PCIE_1_MSTR_AXI_CLK 53
-#define GCC_PCIE_1_PIPE_CLK 54
-#define GCC_PCIE_1_SLV_AXI_CLK 55
-#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56
-#define GCC_PCIE_PHY_AUX_CLK 57
-#define GCC_PCIE_PHY_REFGEN_CLK 58
-#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59
-#define GCC_PDM2_CLK 60
-#define GCC_PDM2_CLK_SRC 61
-#define GCC_PDM_AHB_CLK 62
-#define GCC_PDM_XO4_CLK 63
-#define GCC_PRNG_AHB_CLK 64
-#define GCC_QMIP_CAMERA_AHB_CLK 65
-#define GCC_QMIP_DISP_AHB_CLK 66
-#define GCC_QMIP_VIDEO_AHB_CLK 67
-#define GCC_QUPV3_WRAP0_S0_CLK 68
-#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69
-#define GCC_QUPV3_WRAP0_S1_CLK 70
-#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71
-#define GCC_QUPV3_WRAP0_S2_CLK 72
-#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73
-#define GCC_QUPV3_WRAP0_S3_CLK 74
-#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75
-#define GCC_QUPV3_WRAP0_S4_CLK 76
-#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77
-#define GCC_QUPV3_WRAP0_S5_CLK 78
-#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79
-#define GCC_QUPV3_WRAP0_S6_CLK 80
-#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81
-#define GCC_QUPV3_WRAP0_S7_CLK 82
-#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83
-#define GCC_QUPV3_WRAP1_S0_CLK 84
-#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85
-#define GCC_QUPV3_WRAP1_S1_CLK 86
-#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87
-#define GCC_QUPV3_WRAP1_S2_CLK 88
-#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89
-#define GCC_QUPV3_WRAP1_S3_CLK 90
-#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91
-#define GCC_QUPV3_WRAP1_S4_CLK 92
-#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93
-#define GCC_QUPV3_WRAP1_S5_CLK 94
-#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95
-#define GCC_QUPV3_WRAP1_S6_CLK 96
-#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97
-#define GCC_QUPV3_WRAP1_S7_CLK 98
-#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99
-#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100
-#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101
-#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102
-#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103
-#define GCC_SDCC2_AHB_CLK 104
-#define GCC_SDCC2_APPS_CLK 105
-#define GCC_SDCC2_APPS_CLK_SRC 106
-#define GCC_SDCC4_AHB_CLK 107
-#define GCC_SDCC4_APPS_CLK 108
-#define GCC_SDCC4_APPS_CLK_SRC 109
-#define GCC_SYS_NOC_CPUSS_AHB_CLK 110
-#define GCC_TSIF_AHB_CLK 111
-#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112
-#define GCC_TSIF_REF_CLK 113
-#define GCC_TSIF_REF_CLK_SRC 114
-#define GCC_UFS_CARD_AHB_CLK 115
-#define GCC_UFS_CARD_AXI_CLK 116
-#define GCC_UFS_CARD_AXI_CLK_SRC 117
-#define GCC_UFS_CARD_CLKREF_CLK 118
-#define GCC_UFS_CARD_ICE_CORE_CLK 119
-#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120
-#define GCC_UFS_CARD_PHY_AUX_CLK 121
-#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122
-#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123
-#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124
-#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125
-#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126
-#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127
-#define GCC_UFS_MEM_CLKREF_CLK 128
-#define GCC_UFS_PHY_AHB_CLK 129
-#define GCC_UFS_PHY_AXI_CLK 130
-#define GCC_UFS_PHY_AXI_CLK_SRC 131
-#define GCC_UFS_PHY_ICE_CORE_CLK 132
-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133
-#define GCC_UFS_PHY_PHY_AUX_CLK 134
-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135
-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136
-#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137
-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138
-#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139
-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140
-#define GCC_USB30_PRIM_MASTER_CLK 141
-#define GCC_USB30_PRIM_MASTER_CLK_SRC 142
-#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143
-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144
-#define GCC_USB30_PRIM_SLEEP_CLK 145
-#define GCC_USB30_SEC_MASTER_CLK 146
-#define GCC_USB30_SEC_MASTER_CLK_SRC 147
-#define GCC_USB30_SEC_MOCK_UTMI_CLK 148
-#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149
-#define GCC_USB30_SEC_SLEEP_CLK 150
-#define GCC_USB3_PRIM_CLKREF_CLK 151
-#define GCC_USB3_PRIM_PHY_AUX_CLK 152
-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153
-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154
-#define GCC_USB3_PRIM_PHY_PIPE_CLK 155
-#define GCC_USB3_SEC_CLKREF_CLK 156
-#define GCC_USB3_SEC_PHY_AUX_CLK 157
-#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158
-#define GCC_USB3_SEC_PHY_PIPE_CLK 159
-#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160
-#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
-#define GCC_VIDEO_AHB_CLK 162
-#define GCC_VIDEO_AXI_CLK 163
-#define GCC_VIDEO_XO_CLK 164
-#define GPLL0 165
-#define GPLL0_OUT_EVEN 166
-#define GPLL0_OUT_MAIN 167
-#define GCC_GPU_IREF_CLK 168
-#define GCC_SDCC1_AHB_CLK 169
-#define GCC_SDCC1_APPS_CLK 170
-#define GCC_SDCC1_ICE_CORE_CLK 171
-#define GCC_SDCC1_APPS_CLK_SRC 172
-#define GCC_SDCC1_ICE_CORE_CLK_SRC 173
-#define GCC_APC_VS_CLK 174
-#define GCC_GPU_VS_CLK 175
-#define GCC_MSS_VS_CLK 176
-#define GCC_VDDA_VS_CLK 177
-#define GCC_VDDCX_VS_CLK 178
-#define GCC_VDDMX_VS_CLK 179
-#define GCC_VS_CTRL_AHB_CLK 180
-#define GCC_VS_CTRL_CLK 181
-#define GCC_VS_CTRL_CLK_SRC 182
-#define GCC_VSENSOR_CLK_SRC 183
-#define GPLL4 184
-#define GCC_CPUSS_DVM_BUS_CLK 185
-#define GCC_CPUSS_GNOC_CLK 186
-#define GCC_QSPI_CORE_CLK_SRC 187
-#define GCC_QSPI_CORE_CLK 188
-#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
-#define GCC_LPASS_Q6_AXI_CLK 190
-#define GCC_LPASS_SWAY_CLK 191
-
-/* GCC Resets */
-#define GCC_MMSS_BCR 0
-#define GCC_PCIE_0_BCR 1
-#define GCC_PCIE_1_BCR 2
-#define GCC_PCIE_PHY_BCR 3
-#define GCC_PDM_BCR 4
-#define GCC_PRNG_BCR 5
-#define GCC_QUPV3_WRAPPER_0_BCR 6
-#define GCC_QUPV3_WRAPPER_1_BCR 7
-#define GCC_QUSB2PHY_PRIM_BCR 8
-#define GCC_QUSB2PHY_SEC_BCR 9
-#define GCC_SDCC2_BCR 10
-#define GCC_SDCC4_BCR 11
-#define GCC_TSIF_BCR 12
-#define GCC_UFS_CARD_BCR 13
-#define GCC_UFS_PHY_BCR 14
-#define GCC_USB30_PRIM_BCR 15
-#define GCC_USB30_SEC_BCR 16
-#define GCC_USB3_PHY_PRIM_BCR 17
-#define GCC_USB3PHY_PHY_PRIM_BCR 18
-#define GCC_USB3_DP_PHY_PRIM_BCR 19
-#define GCC_USB3_PHY_SEC_BCR 20
-#define GCC_USB3PHY_PHY_SEC_BCR 21
-#define GCC_USB3_DP_PHY_SEC_BCR 22
-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
-#define GCC_PCIE_0_PHY_BCR 24
-#define GCC_PCIE_1_PHY_BCR 25
-
-/* GCC GDSCRs */
-#define PCIE_0_GDSC 0
-#define PCIE_1_GDSC 1
-#define UFS_CARD_GDSC 2
-#define UFS_PHY_GDSC 3
-#define USB30_PRIM_GDSC 4
-#define USB30_SEC_GDSC 5
-#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6
-#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7
-#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8
-#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9
-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10
-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11
-#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h
deleted file mode 100644
index 9690d90..0000000
--- a/include/dt-bindings/clock/qcom,gpucc-sdm845.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H
-
-/* GPU_CC clock registers */
-#define GPU_CC_CX_GMU_CLK 0
-#define GPU_CC_CXO_CLK 1
-#define GPU_CC_GMU_CLK_SRC 2
-#define GPU_CC_PLL1 3
-
-/* GPU_CC Resets */
-#define GPUCC_GPU_CC_CX_BCR 0
-#define GPUCC_GPU_CC_GMU_BCR 1
-#define GPUCC_GPU_CC_XO_BCR 2
-
-/* GPU_CC GDSCRs */
-#define GPU_CX_GDSC 0
-#define GPU_GX_GDSC 1
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,lpass-sdm845.h b/include/dt-bindings/clock/qcom,lpass-sdm845.h
deleted file mode 100644
index 6590508..0000000
--- a/include/dt-bindings/clock/qcom,lpass-sdm845.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H
-
-#define LPASS_Q6SS_AHBM_AON_CLK 0
-#define LPASS_Q6SS_AHBS_AON_CLK 1
-#define LPASS_QDSP6SS_XO_CLK 2
-#define LPASS_QDSP6SS_SLEEP_CLK 3
-#define LPASS_QDSP6SS_CORE_CLK 4
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
deleted file mode 100644
index d51f9ac..0000000
--- a/include/dt-bindings/clock/qcom,mmcc-msm8996.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
-#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H
-
-#define MMPLL0_EARLY 0
-#define MMPLL0_PLL 1
-#define MMPLL1_EARLY 2
-#define MMPLL1_PLL 3
-#define MMPLL2_EARLY 4
-#define MMPLL2_PLL 5
-#define MMPLL3_EARLY 6
-#define MMPLL3_PLL 7
-#define MMPLL4_EARLY 8
-#define MMPLL4_PLL 9
-#define MMPLL5_EARLY 10
-#define MMPLL5_PLL 11
-#define MMPLL8_EARLY 12
-#define MMPLL8_PLL 13
-#define MMPLL9_EARLY 14
-#define MMPLL9_PLL 15
-#define AHB_CLK_SRC 16
-#define AXI_CLK_SRC 17
-#define MAXI_CLK_SRC 18
-#define DSA_CORE_CLK_SRC 19
-#define GFX3D_CLK_SRC 20
-#define RBBMTIMER_CLK_SRC 21
-#define ISENSE_CLK_SRC 22
-#define RBCPR_CLK_SRC 23
-#define VIDEO_CORE_CLK_SRC 24
-#define VIDEO_SUBCORE0_CLK_SRC 25
-#define VIDEO_SUBCORE1_CLK_SRC 26
-#define PCLK0_CLK_SRC 27
-#define PCLK1_CLK_SRC 28
-#define MDP_CLK_SRC 29
-#define EXTPCLK_CLK_SRC 30
-#define VSYNC_CLK_SRC 31
-#define HDMI_CLK_SRC 32
-#define BYTE0_CLK_SRC 33
-#define BYTE1_CLK_SRC 34
-#define ESC0_CLK_SRC 35
-#define ESC1_CLK_SRC 36
-#define CAMSS_GP0_CLK_SRC 37
-#define CAMSS_GP1_CLK_SRC 38
-#define MCLK0_CLK_SRC 39
-#define MCLK1_CLK_SRC 40
-#define MCLK2_CLK_SRC 41
-#define MCLK3_CLK_SRC 42
-#define CCI_CLK_SRC 43
-#define CSI0PHYTIMER_CLK_SRC 44
-#define CSI1PHYTIMER_CLK_SRC 45
-#define CSI2PHYTIMER_CLK_SRC 46
-#define CSIPHY0_3P_CLK_SRC 47
-#define CSIPHY1_3P_CLK_SRC 48
-#define CSIPHY2_3P_CLK_SRC 49
-#define JPEG0_CLK_SRC 50
-#define JPEG2_CLK_SRC 51
-#define JPEG_DMA_CLK_SRC 52
-#define VFE0_CLK_SRC 53
-#define VFE1_CLK_SRC 54
-#define CPP_CLK_SRC 55
-#define CSI0_CLK_SRC 56
-#define CSI1_CLK_SRC 57
-#define CSI2_CLK_SRC 58
-#define CSI3_CLK_SRC 59
-#define FD_CORE_CLK_SRC 60
-#define MMSS_CXO_CLK 61
-#define MMSS_SLEEPCLK_CLK 62
-#define MMSS_MMAGIC_AHB_CLK 63
-#define MMSS_MMAGIC_CFG_AHB_CLK 64
-#define MMSS_MISC_AHB_CLK 65
-#define MMSS_MISC_CXO_CLK 66
-#define MMSS_BTO_AHB_CLK 67
-#define MMSS_MMAGIC_AXI_CLK 68
-#define MMSS_S0_AXI_CLK 69
-#define MMSS_MMAGIC_MAXI_CLK 70
-#define DSA_CORE_CLK 71
-#define DSA_NOC_CFG_AHB_CLK 72
-#define MMAGIC_CAMSS_AXI_CLK 73
-#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74
-#define THROTTLE_CAMSS_CXO_CLK 75
-#define THROTTLE_CAMSS_AHB_CLK 76
-#define THROTTLE_CAMSS_AXI_CLK 77
-#define SMMU_VFE_AHB_CLK 78
-#define SMMU_VFE_AXI_CLK 79
-#define SMMU_CPP_AHB_CLK 80
-#define SMMU_CPP_AXI_CLK 81
-#define SMMU_JPEG_AHB_CLK 82
-#define SMMU_JPEG_AXI_CLK 83
-#define MMAGIC_MDSS_AXI_CLK 84
-#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85
-#define THROTTLE_MDSS_CXO_CLK 86
-#define THROTTLE_MDSS_AHB_CLK 87
-#define THROTTLE_MDSS_AXI_CLK 88
-#define SMMU_ROT_AHB_CLK 89
-#define SMMU_ROT_AXI_CLK 90
-#define SMMU_MDP_AHB_CLK 91
-#define SMMU_MDP_AXI_CLK 92
-#define MMAGIC_VIDEO_AXI_CLK 93
-#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94
-#define THROTTLE_VIDEO_CXO_CLK 95
-#define THROTTLE_VIDEO_AHB_CLK 96
-#define THROTTLE_VIDEO_AXI_CLK 97
-#define SMMU_VIDEO_AHB_CLK 98
-#define SMMU_VIDEO_AXI_CLK 99
-#define MMAGIC_BIMC_AXI_CLK 100
-#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101
-#define GPU_GX_GFX3D_CLK 102
-#define GPU_GX_RBBMTIMER_CLK 103
-#define GPU_AHB_CLK 104
-#define GPU_AON_ISENSE_CLK 105
-#define VMEM_MAXI_CLK 106
-#define VMEM_AHB_CLK 107
-#define MMSS_RBCPR_CLK 108
-#define MMSS_RBCPR_AHB_CLK 109
-#define VIDEO_CORE_CLK 110
-#define VIDEO_AXI_CLK 111
-#define VIDEO_MAXI_CLK 112
-#define VIDEO_AHB_CLK 113
-#define VIDEO_SUBCORE0_CLK 114
-#define VIDEO_SUBCORE1_CLK 115
-#define MDSS_AHB_CLK 116
-#define MDSS_HDMI_AHB_CLK 117
-#define MDSS_AXI_CLK 118
-#define MDSS_PCLK0_CLK 119
-#define MDSS_PCLK1_CLK 120
-#define MDSS_MDP_CLK 121
-#define MDSS_EXTPCLK_CLK 122
-#define MDSS_VSYNC_CLK 123
-#define MDSS_HDMI_CLK 124
-#define MDSS_BYTE0_CLK 125
-#define MDSS_BYTE1_CLK 126
-#define MDSS_ESC0_CLK 127
-#define MDSS_ESC1_CLK 128
-#define CAMSS_TOP_AHB_CLK 129
-#define CAMSS_AHB_CLK 130
-#define CAMSS_MICRO_AHB_CLK 131
-#define CAMSS_GP0_CLK 132
-#define CAMSS_GP1_CLK 133
-#define CAMSS_MCLK0_CLK 134
-#define CAMSS_MCLK1_CLK 135
-#define CAMSS_MCLK2_CLK 136
-#define CAMSS_MCLK3_CLK 137
-#define CAMSS_CCI_CLK 138
-#define CAMSS_CCI_AHB_CLK 139
-#define CAMSS_CSI0PHYTIMER_CLK 140
-#define CAMSS_CSI1PHYTIMER_CLK 141
-#define CAMSS_CSI2PHYTIMER_CLK 142
-#define CAMSS_CSIPHY0_3P_CLK 143
-#define CAMSS_CSIPHY1_3P_CLK 144
-#define CAMSS_CSIPHY2_3P_CLK 145
-#define CAMSS_JPEG0_CLK 146
-#define CAMSS_JPEG2_CLK 147
-#define CAMSS_JPEG_DMA_CLK 148
-#define CAMSS_JPEG_AHB_CLK 149
-#define CAMSS_JPEG_AXI_CLK 150
-#define CAMSS_VFE_AHB_CLK 151
-#define CAMSS_VFE_AXI_CLK 152
-#define CAMSS_VFE0_CLK 153
-#define CAMSS_VFE0_STREAM_CLK 154
-#define CAMSS_VFE0_AHB_CLK 155
-#define CAMSS_VFE1_CLK 156
-#define CAMSS_VFE1_STREAM_CLK 157
-#define CAMSS_VFE1_AHB_CLK 158
-#define CAMSS_CSI_VFE0_CLK 159
-#define CAMSS_CSI_VFE1_CLK 160
-#define CAMSS_CPP_VBIF_AHB_CLK 161
-#define CAMSS_CPP_AXI_CLK 162
-#define CAMSS_CPP_CLK 163
-#define CAMSS_CPP_AHB_CLK 164
-#define CAMSS_CSI0_CLK 165
-#define CAMSS_CSI0_AHB_CLK 166
-#define CAMSS_CSI0PHY_CLK 167
-#define CAMSS_CSI0RDI_CLK 168
-#define CAMSS_CSI0PIX_CLK 169
-#define CAMSS_CSI1_CLK 170
-#define CAMSS_CSI1_AHB_CLK 171
-#define CAMSS_CSI1PHY_CLK 172
-#define CAMSS_CSI1RDI_CLK 173
-#define CAMSS_CSI1PIX_CLK 174
-#define CAMSS_CSI2_CLK 175
-#define CAMSS_CSI2_AHB_CLK 176
-#define CAMSS_CSI2PHY_CLK 177
-#define CAMSS_CSI2RDI_CLK 178
-#define CAMSS_CSI2PIX_CLK 179
-#define CAMSS_CSI3_CLK 180
-#define CAMSS_CSI3_AHB_CLK 181
-#define CAMSS_CSI3PHY_CLK 182
-#define CAMSS_CSI3RDI_CLK 183
-#define CAMSS_CSI3PIX_CLK 184
-#define CAMSS_ISPIF_AHB_CLK 185
-#define FD_CORE_CLK 186
-#define FD_CORE_UAR_CLK 187
-#define FD_AHB_CLK 188
-#define MMSS_SPDM_CSI0_CLK 189
-#define MMSS_SPDM_JPEG_DMA_CLK 190
-#define MMSS_SPDM_CPP_CLK 191
-#define MMSS_SPDM_PCLK0_CLK 192
-#define MMSS_SPDM_AHB_CLK 193
-#define MMSS_SPDM_GFX3D_CLK 194
-#define MMSS_SPDM_PCLK1_CLK 195
-#define MMSS_SPDM_JPEG2_CLK 196
-#define MMSS_SPDM_DEBUG_CLK 197
-#define MMSS_SPDM_VFE1_CLK 198
-#define MMSS_SPDM_VFE0_CLK 199
-#define MMSS_SPDM_VIDEO_CORE_CLK 200
-#define MMSS_SPDM_AXI_CLK 201
-#define MMSS_SPDM_MDP_CLK 202
-#define MMSS_SPDM_JPEG0_CLK 203
-#define MMSS_SPDM_RM_AXI_CLK 204
-#define MMSS_SPDM_RM_MAXI_CLK 205
-
-#define MMAGICAHB_BCR 0
-#define MMAGIC_CFG_BCR 1
-#define MISC_BCR 2
-#define BTO_BCR 3
-#define MMAGICAXI_BCR 4
-#define MMAGICMAXI_BCR 5
-#define DSA_BCR 6
-#define MMAGIC_CAMSS_BCR 7
-#define THROTTLE_CAMSS_BCR 8
-#define SMMU_VFE_BCR 9
-#define SMMU_CPP_BCR 10
-#define SMMU_JPEG_BCR 11
-#define MMAGIC_MDSS_BCR 12
-#define THROTTLE_MDSS_BCR 13
-#define SMMU_ROT_BCR 14
-#define SMMU_MDP_BCR 15
-#define MMAGIC_VIDEO_BCR 16
-#define THROTTLE_VIDEO_BCR 17
-#define SMMU_VIDEO_BCR 18
-#define MMAGIC_BIMC_BCR 19
-#define GPU_GX_BCR 20
-#define GPU_BCR 21
-#define GPU_AON_BCR 22
-#define VMEM_BCR 23
-#define MMSS_RBCPR_BCR 24
-#define VIDEO_BCR 25
-#define MDSS_BCR 26
-#define CAMSS_TOP_BCR 27
-#define CAMSS_AHB_BCR 28
-#define CAMSS_MICRO_BCR 29
-#define CAMSS_CCI_BCR 30
-#define CAMSS_PHY0_BCR 31
-#define CAMSS_PHY1_BCR 32
-#define CAMSS_PHY2_BCR 33
-#define CAMSS_CSIPHY0_3P_BCR 34
-#define CAMSS_CSIPHY1_3P_BCR 35
-#define CAMSS_CSIPHY2_3P_BCR 36
-#define CAMSS_JPEG_BCR 37
-#define CAMSS_VFE_BCR 38
-#define CAMSS_VFE0_BCR 39
-#define CAMSS_VFE1_BCR 40
-#define CAMSS_CSI_VFE0_BCR 41
-#define CAMSS_CSI_VFE1_BCR 42
-#define CAMSS_CPP_TOP_BCR 43
-#define CAMSS_CPP_BCR 44
-#define CAMSS_CSI0_BCR 45
-#define CAMSS_CSI0RDI_BCR 46
-#define CAMSS_CSI0PIX_BCR 47
-#define CAMSS_CSI1_BCR 48
-#define CAMSS_CSI1RDI_BCR 49
-#define CAMSS_CSI1PIX_BCR 50
-#define CAMSS_CSI2_BCR 51
-#define CAMSS_CSI2RDI_BCR 52
-#define CAMSS_CSI2PIX_BCR 53
-#define CAMSS_CSI3_BCR 54
-#define CAMSS_CSI3RDI_BCR 55
-#define CAMSS_CSI3PIX_BCR 56
-#define CAMSS_ISPIF_BCR 57
-#define FD_BCR 58
-#define MMSS_SPDM_RM_BCR 59
-
-/* Indexes for GDSCs */
-#define MMAGIC_VIDEO_GDSC 0
-#define MMAGIC_MDSS_GDSC 1
-#define MMAGIC_CAMSS_GDSC 2
-#define GPU_GDSC 3
-#define VENUS_GDSC 4
-#define VENUS_CORE0_GDSC 5
-#define VENUS_CORE1_GDSC 6
-#define CAMSS_GDSC 7
-#define VFE0_GDSC 8
-#define VFE1_GDSC 9
-#define JPEG_GDSC 10
-#define CPP_GDSC 11
-#define FD_GDSC 12
-#define MDSS_GDSC 13
-#define GPU_GX_GDSC 14
-#define MMAGIC_BIMC_GDSC 15
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
deleted file mode 100644
index 46309c9..0000000
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2015 Linaro Limited
- */
-
-#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
-#define _DT_BINDINGS_CLK_MSM_RPMCC_H
-
-/* RPM clocks */
-#define RPM_PXO_CLK 0
-#define RPM_PXO_A_CLK 1
-#define RPM_CXO_CLK 2
-#define RPM_CXO_A_CLK 3
-#define RPM_APPS_FABRIC_CLK 4
-#define RPM_APPS_FABRIC_A_CLK 5
-#define RPM_CFPB_CLK 6
-#define RPM_CFPB_A_CLK 7
-#define RPM_QDSS_CLK 8
-#define RPM_QDSS_A_CLK 9
-#define RPM_DAYTONA_FABRIC_CLK 10
-#define RPM_DAYTONA_FABRIC_A_CLK 11
-#define RPM_EBI1_CLK 12
-#define RPM_EBI1_A_CLK 13
-#define RPM_MM_FABRIC_CLK 14
-#define RPM_MM_FABRIC_A_CLK 15
-#define RPM_MMFPB_CLK 16
-#define RPM_MMFPB_A_CLK 17
-#define RPM_SYS_FABRIC_CLK 18
-#define RPM_SYS_FABRIC_A_CLK 19
-#define RPM_SFPB_CLK 20
-#define RPM_SFPB_A_CLK 21
-#define RPM_SMI_CLK 22
-#define RPM_SMI_A_CLK 23
-#define RPM_PLL4_CLK 24
-#define RPM_XO_D0 25
-#define RPM_XO_D1 26
-#define RPM_XO_A0 27
-#define RPM_XO_A1 28
-#define RPM_XO_A2 29
-#define RPM_NSS_FABRIC_0_CLK 30
-#define RPM_NSS_FABRIC_0_A_CLK 31
-#define RPM_NSS_FABRIC_1_CLK 32
-#define RPM_NSS_FABRIC_1_A_CLK 33
-
-/* SMD RPM clocks */
-#define RPM_SMD_XO_CLK_SRC 0
-#define RPM_SMD_XO_A_CLK_SRC 1
-#define RPM_SMD_PCNOC_CLK 2
-#define RPM_SMD_PCNOC_A_CLK 3
-#define RPM_SMD_SNOC_CLK 4
-#define RPM_SMD_SNOC_A_CLK 5
-#define RPM_SMD_BIMC_CLK 6
-#define RPM_SMD_BIMC_A_CLK 7
-#define RPM_SMD_QDSS_CLK 8
-#define RPM_SMD_QDSS_A_CLK 9
-#define RPM_SMD_BB_CLK1 10
-#define RPM_SMD_BB_CLK1_A 11
-#define RPM_SMD_BB_CLK2 12
-#define RPM_SMD_BB_CLK2_A 13
-#define RPM_SMD_RF_CLK1 14
-#define RPM_SMD_RF_CLK1_A 15
-#define RPM_SMD_RF_CLK2 16
-#define RPM_SMD_RF_CLK2_A 17
-#define RPM_SMD_BB_CLK1_PIN 18
-#define RPM_SMD_BB_CLK1_A_PIN 19
-#define RPM_SMD_BB_CLK2_PIN 20
-#define RPM_SMD_BB_CLK2_A_PIN 21
-#define RPM_SMD_RF_CLK1_PIN 22
-#define RPM_SMD_RF_CLK1_A_PIN 23
-#define RPM_SMD_RF_CLK2_PIN 24
-#define RPM_SMD_RF_CLK2_A_PIN 25
-#define RPM_SMD_PNOC_CLK 26
-#define RPM_SMD_PNOC_A_CLK 27
-#define RPM_SMD_CNOC_CLK 28
-#define RPM_SMD_CNOC_A_CLK 29
-#define RPM_SMD_MMSSNOC_AHB_CLK 30
-#define RPM_SMD_MMSSNOC_AHB_A_CLK 31
-#define RPM_SMD_GFX3D_CLK_SRC 32
-#define RPM_SMD_GFX3D_A_CLK_SRC 33
-#define RPM_SMD_OCMEMGX_CLK 34
-#define RPM_SMD_OCMEMGX_A_CLK 35
-#define RPM_SMD_CXO_D0 36
-#define RPM_SMD_CXO_D0_A 37
-#define RPM_SMD_CXO_D1 38
-#define RPM_SMD_CXO_D1_A 39
-#define RPM_SMD_CXO_A0 40
-#define RPM_SMD_CXO_A0_A 41
-#define RPM_SMD_CXO_A1 42
-#define RPM_SMD_CXO_A1_A 43
-#define RPM_SMD_CXO_A2 44
-#define RPM_SMD_CXO_A2_A 45
-#define RPM_SMD_DIV_CLK1 46
-#define RPM_SMD_DIV_A_CLK1 47
-#define RPM_SMD_DIV_CLK2 48
-#define RPM_SMD_DIV_A_CLK2 49
-#define RPM_SMD_DIFF_CLK 50
-#define RPM_SMD_DIFF_A_CLK 51
-#define RPM_SMD_CXO_D0_PIN 52
-#define RPM_SMD_CXO_D0_A_PIN 53
-#define RPM_SMD_CXO_D1_PIN 54
-#define RPM_SMD_CXO_D1_A_PIN 55
-#define RPM_SMD_CXO_A0_PIN 56
-#define RPM_SMD_CXO_A0_A_PIN 57
-#define RPM_SMD_CXO_A1_PIN 58
-#define RPM_SMD_CXO_A1_A_PIN 59
-#define RPM_SMD_CXO_A2_PIN 60
-#define RPM_SMD_CXO_A2_A_PIN 61
-#define RPM_SMD_AGGR1_NOC_CLK 62
-#define RPM_SMD_AGGR1_NOC_A_CLK 63
-#define RPM_SMD_AGGR2_NOC_CLK 64
-#define RPM_SMD_AGGR2_NOC_A_CLK 65
-#define RPM_SMD_MMAXI_CLK 66
-#define RPM_SMD_MMAXI_A_CLK 67
-#define RPM_SMD_IPA_CLK 68
-#define RPM_SMD_IPA_A_CLK 69
-#define RPM_SMD_CE1_CLK 70
-#define RPM_SMD_CE1_A_CLK 71
-#define RPM_SMD_DIV_CLK3 72
-#define RPM_SMD_DIV_A_CLK3 73
-#define RPM_SMD_LN_BB_CLK 74
-#define RPM_SMD_LN_BB_A_CLK 75
-#define RPM_SMD_BIMC_GPU_CLK 76
-#define RPM_SMD_BIMC_GPU_A_CLK 77
-#define RPM_SMD_QPIC_CLK 78
-#define RPM_SMD_QPIC_CLK_A 79
-#define RPM_SMD_LN_BB_CLK1 80
-#define RPM_SMD_LN_BB_CLK1_A 81
-#define RPM_SMD_LN_BB_CLK2 82
-#define RPM_SMD_LN_BB_CLK2_A 83
-#define RPM_SMD_LN_BB_CLK3_PIN 84
-#define RPM_SMD_LN_BB_CLK3_A_PIN 85
-#define RPM_SMD_RF_CLK3 86
-#define RPM_SMD_RF_CLK3_A 87
-#define RPM_SMD_RF_CLK3_PIN 88
-#define RPM_SMD_RF_CLK3_A_PIN 89
-#define RPM_SMD_MMSSNOC_AXI_CLK 90
-#define RPM_SMD_MMSSNOC_AXI_CLK_A 91
-#define RPM_SMD_CNOC_PERIPH_CLK 92
-#define RPM_SMD_CNOC_PERIPH_A_CLK 93
-#define RPM_SMD_LN_BB_CLK3 94
-#define RPM_SMD_LN_BB_CLK3_A 95
-#define RPM_SMD_LN_BB_CLK1_PIN 96
-#define RPM_SMD_LN_BB_CLK1_A_PIN 97
-#define RPM_SMD_LN_BB_CLK2_PIN 98
-#define RPM_SMD_LN_BB_CLK2_A_PIN 99
-#define RPM_SMD_SYSMMNOC_CLK 100
-#define RPM_SMD_SYSMMNOC_A_CLK 101
-#define RPM_SMD_CE2_CLK 102
-#define RPM_SMD_CE2_A_CLK 103
-#define RPM_SMD_CE3_CLK 104
-#define RPM_SMD_CE3_A_CLK 105
-#define RPM_SMD_QUP_CLK 106
-#define RPM_SMD_QUP_A_CLK 107
-#define RPM_SMD_MMRT_CLK 108
-#define RPM_SMD_MMRT_A_CLK 109
-#define RPM_SMD_MMNRT_CLK 110
-#define RPM_SMD_MMNRT_A_CLK 111
-#define RPM_SMD_SNOC_PERIPH_CLK 112
-#define RPM_SMD_SNOC_PERIPH_A_CLK 113
-#define RPM_SMD_SNOC_LPASS_CLK 114
-#define RPM_SMD_SNOC_LPASS_A_CLK 115
-#define RPM_SMD_HWKM_CLK 116
-#define RPM_SMD_HWKM_A_CLK 117
-#define RPM_SMD_PKA_CLK 118
-#define RPM_SMD_PKA_A_CLK 119
-#define RPM_SMD_CPUSS_GNOC_CLK 120
-#define RPM_SMD_CPUSS_GNOC_A_CLK 121
-#define RPM_SMD_MSS_CFG_AHB_CLK 122
-#define RPM_SMD_MSS_CFG_AHB_A_CLK 123
-#define RPM_SMD_BIMC_FREQ_LOG 124
-#define RPM_SMD_LN_BB_CLK_PIN 125
-#define RPM_SMD_LN_BB_A_CLK_PIN 126
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
deleted file mode 100644
index bf5b59b..0000000
--- a/include/dt-bindings/clock/qcom,rpmh.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */
-
-#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
-#define _DT_BINDINGS_CLK_MSM_RPMH_H
-
-/* RPMh controlled clocks */
-#define RPMH_CXO_CLK 0
-#define RPMH_CXO_CLK_A 1
-#define RPMH_LN_BB_CLK2 2
-#define RPMH_LN_BB_CLK2_A 3
-#define RPMH_LN_BB_CLK3 4
-#define RPMH_LN_BB_CLK3_A 5
-#define RPMH_RF_CLK1 6
-#define RPMH_RF_CLK1_A 7
-#define RPMH_RF_CLK2 8
-#define RPMH_RF_CLK2_A 9
-#define RPMH_RF_CLK3 10
-#define RPMH_RF_CLK3_A 11
-#define RPMH_IPA_CLK 12
-#define RPMH_LN_BB_CLK1 13
-#define RPMH_LN_BB_CLK1_A 14
-#define RPMH_CE_CLK 15
-#define RPMH_QPIC_CLK 16
-#define RPMH_DIV_CLK1 17
-#define RPMH_DIV_CLK1_A 18
-#define RPMH_RF_CLK4 19
-#define RPMH_RF_CLK4_A 20
-#define RPMH_RF_CLK5 21
-#define RPMH_RF_CLK5_A 22
-#define RPMH_PKA_CLK 23
-#define RPMH_HWKM_CLK 24
-#define RPMH_QLINK_CLK 25
-#define RPMH_QLINK_CLK_A 26
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h
deleted file mode 100644
index 838faef..0000000
--- a/include/dt-bindings/clock/qcom,turingcc-qcs404.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019, Linaro Ltd
- */
-
-#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H
-#define _DT_BINDINGS_CLK_TURING_QCS404_H
-
-#define TURING_Q6SS_Q6_AXIM_CLK 0
-#define TURING_Q6SS_AHBM_AON_CLK 1
-#define TURING_WRAPPER_AON_CLK 2
-#define TURING_Q6SS_AHBS_AON_CLK 3
-#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h
deleted file mode 100644
index 1b86816..0000000
--- a/include/dt-bindings/clock/qcom,videocc-sdm845.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
-
-/* VIDEO_CC clock registers */
-#define VIDEO_CC_APB_CLK 0
-#define VIDEO_CC_AT_CLK 1
-#define VIDEO_CC_QDSS_TRIG_CLK 2
-#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3
-#define VIDEO_CC_VCODEC0_AXI_CLK 4
-#define VIDEO_CC_VCODEC0_CORE_CLK 5
-#define VIDEO_CC_VCODEC1_AXI_CLK 6
-#define VIDEO_CC_VCODEC1_CORE_CLK 7
-#define VIDEO_CC_VENUS_AHB_CLK 8
-#define VIDEO_CC_VENUS_CLK_SRC 9
-#define VIDEO_CC_VENUS_CTL_AXI_CLK 10
-#define VIDEO_CC_VENUS_CTL_CORE_CLK 11
-#define VIDEO_PLL0 12
-
-/* VIDEO_CC Resets */
-#define VIDEO_CC_VENUS_BCR 0
-#define VIDEO_CC_VCODEC0_BCR 1
-#define VIDEO_CC_VCODEC1_BCR 2
-#define VIDEO_CC_INTERFACE_BCR 3
-
-/* VIDEO_CC GDSCRs */
-#define VENUS_GDSC 0
-#define VCODEC0_GDSC 1
-#define VCODEC1_GDSC 2
-
-#endif
diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h
deleted file mode 100644
index ebda2a3..0000000
--- a/include/dt-bindings/dma/qcom-gpi.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
-/* Copyright (c) 2020, Linaro Ltd. */
-
-#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__
-#define __DT_BINDINGS_DMA_QCOM_GPI_H__
-
-#define QCOM_GPI_SPI 1
-#define QCOM_GPI_UART 2
-#define QCOM_GPI_I2C 3
-
-#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */
diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h
deleted file mode 100644
index 6de8b08..0000000
--- a/include/dt-bindings/firmware/qcom,scm.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
-/*
- * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
- * Copyright (C) 2015 Linaro Ltd.
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_FIRMWARE_QCOM_SCM_H
-#define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H
-
-#define QCOM_SCM_VMID_TZ 0x1
-#define QCOM_SCM_VMID_HLOS 0x3
-#define QCOM_SCM_VMID_SSC_Q6 0x5
-#define QCOM_SCM_VMID_ADSP_Q6 0x6
-#define QCOM_SCM_VMID_CP_TOUCH 0x8
-#define QCOM_SCM_VMID_CP_BITSTREAM 0x9
-#define QCOM_SCM_VMID_CP_PIXEL 0xA
-#define QCOM_SCM_VMID_CP_NON_PIXEL 0xB
-#define QCOM_SCM_VMID_CP_CAMERA 0xD
-#define QCOM_SCM_VMID_HLOS_FREE 0xE
-#define QCOM_SCM_VMID_MSS_MSA 0xF
-#define QCOM_SCM_VMID_MSS_NONMSA 0x10
-#define QCOM_SCM_VMID_CP_SEC_DISPLAY 0x11
-#define QCOM_SCM_VMID_CP_APP 0x12
-#define QCOM_SCM_VMID_LPASS 0x16
-#define QCOM_SCM_VMID_WLAN 0x18
-#define QCOM_SCM_VMID_WLAN_CE 0x19
-#define QCOM_SCM_VMID_CP_SPSS_SP 0x1A
-#define QCOM_SCM_VMID_CP_CAMERA_PREVIEW 0x1D
-#define QCOM_SCM_VMID_CDSP 0x1E
-#define QCOM_SCM_VMID_CP_SPSS_SP_SHARED 0x22
-#define QCOM_SCM_VMID_CP_SPSS_HLOS_SHARED 0x24
-#define QCOM_SCM_VMID_ADSP_HEAP 0x25
-#define QCOM_SCM_VMID_CP_CDSP 0x2A
-#define QCOM_SCM_VMID_NAV 0x2B
-#define QCOM_SCM_VMID_TVM 0x2D
-#define QCOM_SCM_VMID_OEMVM 0x31
-
-#endif
diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
deleted file mode 100644
index 08adfe2..0000000
--- a/include/dt-bindings/iio/qcom,spmi-vadc.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_H
-
-/* Voltage ADC channels */
-#define VADC_USBIN 0x00
-#define VADC_DCIN 0x01
-#define VADC_VCHG_SNS 0x02
-#define VADC_SPARE1_03 0x03
-#define VADC_USB_ID_MV 0x04
-#define VADC_VCOIN 0x05
-#define VADC_VBAT_SNS 0x06
-#define VADC_VSYS 0x07
-#define VADC_DIE_TEMP 0x08
-#define VADC_REF_625MV 0x09
-#define VADC_REF_1250MV 0x0a
-#define VADC_CHG_TEMP 0x0b
-#define VADC_SPARE1 0x0c
-#define VADC_SPARE2 0x0d
-#define VADC_GND_REF 0x0e
-#define VADC_VDD_VADC 0x0f
-
-#define VADC_P_MUX1_1_1 0x10
-#define VADC_P_MUX2_1_1 0x11
-#define VADC_P_MUX3_1_1 0x12
-#define VADC_P_MUX4_1_1 0x13
-#define VADC_P_MUX5_1_1 0x14
-#define VADC_P_MUX6_1_1 0x15
-#define VADC_P_MUX7_1_1 0x16
-#define VADC_P_MUX8_1_1 0x17
-#define VADC_P_MUX9_1_1 0x18
-#define VADC_P_MUX10_1_1 0x19
-#define VADC_P_MUX11_1_1 0x1a
-#define VADC_P_MUX12_1_1 0x1b
-#define VADC_P_MUX13_1_1 0x1c
-#define VADC_P_MUX14_1_1 0x1d
-#define VADC_P_MUX15_1_1 0x1e
-#define VADC_P_MUX16_1_1 0x1f
-
-#define VADC_P_MUX1_1_3 0x20
-#define VADC_P_MUX2_1_3 0x21
-#define VADC_P_MUX3_1_3 0x22
-#define VADC_P_MUX4_1_3 0x23
-#define VADC_P_MUX5_1_3 0x24
-#define VADC_P_MUX6_1_3 0x25
-#define VADC_P_MUX7_1_3 0x26
-#define VADC_P_MUX8_1_3 0x27
-#define VADC_P_MUX9_1_3 0x28
-#define VADC_P_MUX10_1_3 0x29
-#define VADC_P_MUX11_1_3 0x2a
-#define VADC_P_MUX12_1_3 0x2b
-#define VADC_P_MUX13_1_3 0x2c
-#define VADC_P_MUX14_1_3 0x2d
-#define VADC_P_MUX15_1_3 0x2e
-#define VADC_P_MUX16_1_3 0x2f
-
-#define VADC_LR_MUX1_BAT_THERM 0x30
-#define VADC_LR_MUX2_BAT_ID 0x31
-#define VADC_LR_MUX3_XO_THERM 0x32
-#define VADC_LR_MUX4_AMUX_THM1 0x33
-#define VADC_LR_MUX5_AMUX_THM2 0x34
-#define VADC_LR_MUX6_AMUX_THM3 0x35
-#define VADC_LR_MUX7_HW_ID 0x36
-#define VADC_LR_MUX8_AMUX_THM4 0x37
-#define VADC_LR_MUX9_AMUX_THM5 0x38
-#define VADC_LR_MUX10_USB_ID 0x39
-#define VADC_AMUX_PU1 0x3a
-#define VADC_AMUX_PU2 0x3b
-#define VADC_LR_MUX3_BUF_XO_THERM 0x3c
-
-#define VADC_LR_MUX1_PU1_BAT_THERM 0x70
-#define VADC_LR_MUX2_PU1_BAT_ID 0x71
-#define VADC_LR_MUX3_PU1_XO_THERM 0x72
-#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73
-#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74
-#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75
-#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76
-#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77
-#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78
-#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79
-#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c
-
-#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0
-#define VADC_LR_MUX2_PU2_BAT_ID 0xb1
-#define VADC_LR_MUX3_PU2_XO_THERM 0xb2
-#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3
-#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4
-#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5
-#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6
-#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7
-#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8
-#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9
-#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc
-
-#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0
-#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1
-#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2
-#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3
-#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4
-#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5
-#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6
-#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7
-#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8
-#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9
-#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc
-
-/* ADC channels for SPMI PMIC5 */
-
-#define ADC5_REF_GND 0x00
-#define ADC5_1P25VREF 0x01
-#define ADC5_VREF_VADC 0x02
-#define ADC5_VREF_VADC5_DIV_3 0x82
-#define ADC5_VPH_PWR 0x83
-#define ADC5_VBAT_SNS 0x84
-#define ADC5_VCOIN 0x85
-#define ADC5_DIE_TEMP 0x06
-#define ADC5_USB_IN_I 0x07
-#define ADC5_USB_IN_V_16 0x08
-#define ADC5_CHG_TEMP 0x09
-#define ADC5_BAT_THERM 0x0a
-#define ADC5_BAT_ID 0x0b
-#define ADC5_XO_THERM 0x0c
-#define ADC5_AMUX_THM1 0x0d
-#define ADC5_AMUX_THM2 0x0e
-#define ADC5_AMUX_THM3 0x0f
-#define ADC5_AMUX_THM4 0x10
-#define ADC5_AMUX_THM5 0x11
-#define ADC5_GPIO1 0x12
-#define ADC5_GPIO2 0x13
-#define ADC5_GPIO3 0x14
-#define ADC5_GPIO4 0x15
-#define ADC5_GPIO5 0x16
-#define ADC5_GPIO6 0x17
-#define ADC5_GPIO7 0x18
-#define ADC5_SBUx 0x99
-#define ADC5_MID_CHG_DIV6 0x1e
-#define ADC5_OFF 0xff
-
-/* 30k pull-up1 */
-#define ADC5_BAT_THERM_30K_PU 0x2a
-#define ADC5_BAT_ID_30K_PU 0x2b
-#define ADC5_XO_THERM_30K_PU 0x2c
-#define ADC5_AMUX_THM1_30K_PU 0x2d
-#define ADC5_AMUX_THM2_30K_PU 0x2e
-#define ADC5_AMUX_THM3_30K_PU 0x2f
-#define ADC5_AMUX_THM4_30K_PU 0x30
-#define ADC5_AMUX_THM5_30K_PU 0x31
-#define ADC5_GPIO1_30K_PU 0x32
-#define ADC5_GPIO2_30K_PU 0x33
-#define ADC5_GPIO3_30K_PU 0x34
-#define ADC5_GPIO4_30K_PU 0x35
-#define ADC5_GPIO5_30K_PU 0x36
-#define ADC5_GPIO6_30K_PU 0x37
-#define ADC5_GPIO7_30K_PU 0x38
-#define ADC5_SBUx_30K_PU 0x39
-
-/* 100k pull-up2 */
-#define ADC5_BAT_THERM_100K_PU 0x4a
-#define ADC5_BAT_ID_100K_PU 0x4b
-#define ADC5_XO_THERM_100K_PU 0x4c
-#define ADC5_AMUX_THM1_100K_PU 0x4d
-#define ADC5_AMUX_THM2_100K_PU 0x4e
-#define ADC5_AMUX_THM3_100K_PU 0x4f
-#define ADC5_AMUX_THM4_100K_PU 0x50
-#define ADC5_AMUX_THM5_100K_PU 0x51
-#define ADC5_GPIO1_100K_PU 0x52
-#define ADC5_GPIO2_100K_PU 0x53
-#define ADC5_GPIO3_100K_PU 0x54
-#define ADC5_GPIO4_100K_PU 0x55
-#define ADC5_GPIO5_100K_PU 0x56
-#define ADC5_GPIO6_100K_PU 0x57
-#define ADC5_GPIO7_100K_PU 0x58
-#define ADC5_SBUx_100K_PU 0x59
-
-/* 400k pull-up3 */
-#define ADC5_BAT_THERM_400K_PU 0x6a
-#define ADC5_BAT_ID_400K_PU 0x6b
-#define ADC5_XO_THERM_400K_PU 0x6c
-#define ADC5_AMUX_THM1_400K_PU 0x6d
-#define ADC5_AMUX_THM2_400K_PU 0x6e
-#define ADC5_AMUX_THM3_400K_PU 0x6f
-#define ADC5_AMUX_THM4_400K_PU 0x70
-#define ADC5_AMUX_THM5_400K_PU 0x71
-#define ADC5_GPIO1_400K_PU 0x72
-#define ADC5_GPIO2_400K_PU 0x73
-#define ADC5_GPIO3_400K_PU 0x74
-#define ADC5_GPIO4_400K_PU 0x75
-#define ADC5_GPIO5_400K_PU 0x76
-#define ADC5_GPIO6_400K_PU 0x77
-#define ADC5_GPIO7_400K_PU 0x78
-#define ADC5_SBUx_400K_PU 0x79
-
-/* 1/3 Divider */
-#define ADC5_GPIO1_DIV3 0x92
-#define ADC5_GPIO2_DIV3 0x93
-#define ADC5_GPIO3_DIV3 0x94
-#define ADC5_GPIO4_DIV3 0x95
-#define ADC5_GPIO5_DIV3 0x96
-#define ADC5_GPIO6_DIV3 0x97
-#define ADC5_GPIO7_DIV3 0x98
-#define ADC5_SBUx_DIV3 0x99
-
-/* Current and combined current/voltage channels */
-#define ADC5_INT_EXT_ISENSE 0xa1
-#define ADC5_PARALLEL_ISENSE 0xa5
-#define ADC5_CUR_REPLICA_VDS 0xa7
-#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9
-#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab
-#define ADC5_EXT_SENS_OFFSET 0xad
-
-#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0
-#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1
-#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2
-#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3
-#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4
-#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5
-
-#define ADC5_MAX_CHANNEL 0xc0
-
-/* ADC channels for ADC for PMIC7 */
-
-#define ADC7_REF_GND 0x00
-#define ADC7_1P25VREF 0x01
-#define ADC7_VREF_VADC 0x02
-#define ADC7_DIE_TEMP 0x03
-
-#define ADC7_AMUX_THM1 0x04
-#define ADC7_AMUX_THM2 0x05
-#define ADC7_AMUX_THM3 0x06
-#define ADC7_AMUX_THM4 0x07
-#define ADC7_AMUX_THM5 0x08
-#define ADC7_AMUX_THM6 0x09
-#define ADC7_GPIO1 0x0a
-#define ADC7_GPIO2 0x0b
-#define ADC7_GPIO3 0x0c
-#define ADC7_GPIO4 0x0d
-
-#define ADC7_CHG_TEMP 0x10
-#define ADC7_USB_IN_V_16 0x11
-#define ADC7_VDC_16 0x12
-#define ADC7_CC1_ID 0x13
-#define ADC7_VREF_BAT_THERM 0x15
-#define ADC7_IIN_FB 0x17
-
-/* 30k pull-up1 */
-#define ADC7_AMUX_THM1_30K_PU 0x24
-#define ADC7_AMUX_THM2_30K_PU 0x25
-#define ADC7_AMUX_THM3_30K_PU 0x26
-#define ADC7_AMUX_THM4_30K_PU 0x27
-#define ADC7_AMUX_THM5_30K_PU 0x28
-#define ADC7_AMUX_THM6_30K_PU 0x29
-#define ADC7_GPIO1_30K_PU 0x2a
-#define ADC7_GPIO2_30K_PU 0x2b
-#define ADC7_GPIO3_30K_PU 0x2c
-#define ADC7_GPIO4_30K_PU 0x2d
-#define ADC7_CC1_ID_30K_PU 0x33
-
-/* 100k pull-up2 */
-#define ADC7_AMUX_THM1_100K_PU 0x44
-#define ADC7_AMUX_THM2_100K_PU 0x45
-#define ADC7_AMUX_THM3_100K_PU 0x46
-#define ADC7_AMUX_THM4_100K_PU 0x47
-#define ADC7_AMUX_THM5_100K_PU 0x48
-#define ADC7_AMUX_THM6_100K_PU 0x49
-#define ADC7_GPIO1_100K_PU 0x4a
-#define ADC7_GPIO2_100K_PU 0x4b
-#define ADC7_GPIO3_100K_PU 0x4c
-#define ADC7_GPIO4_100K_PU 0x4d
-#define ADC7_CC1_ID_100K_PU 0x53
-
-/* 400k pull-up3 */
-#define ADC7_AMUX_THM1_400K_PU 0x64
-#define ADC7_AMUX_THM2_400K_PU 0x65
-#define ADC7_AMUX_THM3_400K_PU 0x66
-#define ADC7_AMUX_THM4_400K_PU 0x67
-#define ADC7_AMUX_THM5_400K_PU 0x68
-#define ADC7_AMUX_THM6_400K_PU 0x69
-#define ADC7_GPIO1_400K_PU 0x6a
-#define ADC7_GPIO2_400K_PU 0x6b
-#define ADC7_GPIO3_400K_PU 0x6c
-#define ADC7_GPIO4_400K_PU 0x6d
-#define ADC7_CC1_ID_400K_PU 0x73
-
-/* 1/3 Divider */
-#define ADC7_GPIO1_DIV3 0x8a
-#define ADC7_GPIO2_DIV3 0x8b
-#define ADC7_GPIO3_DIV3 0x8c
-#define ADC7_GPIO4_DIV3 0x8d
-
-#define ADC7_VPH_PWR 0x8e
-#define ADC7_VBAT_SNS 0x8f
-
-#define ADC7_SBUx 0x94
-#define ADC7_VBAT_2S_MID 0x96
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
diff --git a/include/dt-bindings/interconnect/qcom,msm8916.h b/include/dt-bindings/interconnect/qcom,msm8916.h
deleted file mode 100644
index 359a75f..0000000
--- a/include/dt-bindings/interconnect/qcom,msm8916.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm interconnect IDs
- *
- * Copyright (c) 2019, Linaro Ltd.
- * Author: Georgi Djakov <georgi.djakov@linaro.org>
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H
-#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H
-
-#define BIMC_SNOC_SLV 0
-#define MASTER_JPEG 1
-#define MASTER_MDP_PORT0 2
-#define MASTER_QDSS_BAM 3
-#define MASTER_QDSS_ETR 4
-#define MASTER_SNOC_CFG 5
-#define MASTER_VFE 6
-#define MASTER_VIDEO_P0 7
-#define SNOC_MM_INT_0 8
-#define SNOC_MM_INT_1 9
-#define SNOC_MM_INT_2 10
-#define SNOC_MM_INT_BIMC 11
-#define PCNOC_SNOC_SLV 12
-#define SLAVE_APSS 13
-#define SLAVE_CATS_128 14
-#define SLAVE_OCMEM_64 15
-#define SLAVE_IMEM 16
-#define SLAVE_QDSS_STM 17
-#define SLAVE_SRVC_SNOC 18
-#define SNOC_BIMC_0_MAS 19
-#define SNOC_BIMC_1_MAS 20
-#define SNOC_INT_0 21
-#define SNOC_INT_1 22
-#define SNOC_INT_BIMC 23
-#define SNOC_PCNOC_MAS 24
-#define SNOC_QDSS_INT 25
-
-#define BIMC_SNOC_MAS 0
-#define MASTER_AMPSS_M0 1
-#define MASTER_GRAPHICS_3D 2
-#define MASTER_TCU0 3
-#define MASTER_TCU1 4
-#define SLAVE_AMPSS_L2 5
-#define SLAVE_EBI_CH0 6
-#define SNOC_BIMC_0_SLV 7
-#define SNOC_BIMC_1_SLV 8
-
-#define MASTER_BLSP_1 0
-#define MASTER_DEHR 1
-#define MASTER_LPASS 2
-#define MASTER_CRYPTO_CORE0 3
-#define MASTER_SDCC_1 4
-#define MASTER_SDCC_2 5
-#define MASTER_SPDM 6
-#define MASTER_USB_HS 7
-#define PCNOC_INT_0 8
-#define PCNOC_INT_1 9
-#define PCNOC_MAS_0 10
-#define PCNOC_MAS_1 11
-#define PCNOC_SLV_0 12
-#define PCNOC_SLV_1 13
-#define PCNOC_SLV_2 14
-#define PCNOC_SLV_3 15
-#define PCNOC_SLV_4 16
-#define PCNOC_SLV_8 17
-#define PCNOC_SLV_9 18
-#define PCNOC_SNOC_MAS 19
-#define SLAVE_BIMC_CFG 20
-#define SLAVE_BLSP_1 21
-#define SLAVE_BOOT_ROM 22
-#define SLAVE_CAMERA_CFG 23
-#define SLAVE_CLK_CTL 24
-#define SLAVE_CRYPTO_0_CFG 25
-#define SLAVE_DEHR_CFG 26
-#define SLAVE_DISPLAY_CFG 27
-#define SLAVE_GRAPHICS_3D_CFG 28
-#define SLAVE_IMEM_CFG 29
-#define SLAVE_LPASS 30
-#define SLAVE_MPM 31
-#define SLAVE_MSG_RAM 32
-#define SLAVE_MSS 33
-#define SLAVE_PDM 34
-#define SLAVE_PMIC_ARB 35
-#define SLAVE_PCNOC_CFG 36
-#define SLAVE_PRNG 37
-#define SLAVE_QDSS_CFG 38
-#define SLAVE_RBCPR_CFG 39
-#define SLAVE_SDCC_1 40
-#define SLAVE_SDCC_2 41
-#define SLAVE_SECURITY 42
-#define SLAVE_SNOC_CFG 43
-#define SLAVE_SPDM 44
-#define SLAVE_TCSR 45
-#define SLAVE_TLMM 46
-#define SLAVE_USB_HS 47
-#define SLAVE_VENUS_CFG 48
-#define SNOC_PCNOC_SLV 49
-
-#endif
diff --git a/include/dt-bindings/interconnect/qcom,msm8996-cbf.h b/include/dt-bindings/interconnect/qcom,msm8996-cbf.h
deleted file mode 100644
index aac5e69..0000000
--- a/include/dt-bindings/interconnect/qcom,msm8996-cbf.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2023 Linaro Ltd. All rights reserved.
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H
-#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H
-
-#define MASTER_CBF_M4M 0
-#define SLAVE_CBF_M4M 1
-
-#endif
diff --git a/include/dt-bindings/interconnect/qcom,msm8996.h b/include/dt-bindings/interconnect/qcom,msm8996.h
deleted file mode 100644
index a0b7c0e..0000000
--- a/include/dt-bindings/interconnect/qcom,msm8996.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
-/*
- * Qualcomm MSM8996 interconnect IDs
- *
- * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
-#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
-
-/* A0NOC */
-#define MASTER_PCIE_0 0
-#define MASTER_PCIE_1 1
-#define MASTER_PCIE_2 2
-
-/* A1NOC */
-#define MASTER_CNOC_A1NOC 0
-#define MASTER_CRYPTO_CORE0 1
-#define MASTER_PNOC_A1NOC 2
-
-/* A2NOC */
-#define MASTER_USB3 0
-#define MASTER_IPA 1
-#define MASTER_UFS 2
-
-/* BIMC */
-#define MASTER_AMPSS_M0 0
-#define MASTER_GRAPHICS_3D 1
-#define MASTER_MNOC_BIMC 2
-#define MASTER_SNOC_BIMC 3
-#define SLAVE_EBI_CH0 4
-#define SLAVE_HMSS_L3 5
-#define SLAVE_BIMC_SNOC_0 6
-#define SLAVE_BIMC_SNOC_1 7
-
-/* CNOC */
-#define MASTER_SNOC_CNOC 0
-#define MASTER_QDSS_DAP 1
-#define SLAVE_CNOC_A1NOC 2
-#define SLAVE_CLK_CTL 3
-#define SLAVE_TCSR 4
-#define SLAVE_TLMM 5
-#define SLAVE_CRYPTO_0_CFG 6
-#define SLAVE_MPM 7
-#define SLAVE_PIMEM_CFG 8
-#define SLAVE_IMEM_CFG 9
-#define SLAVE_MESSAGE_RAM 10
-#define SLAVE_BIMC_CFG 11
-#define SLAVE_PMIC_ARB 12
-#define SLAVE_PRNG 13
-#define SLAVE_DCC_CFG 14
-#define SLAVE_RBCPR_MX 15
-#define SLAVE_QDSS_CFG 16
-#define SLAVE_RBCPR_CX 17
-#define SLAVE_QDSS_RBCPR_APU 18
-#define SLAVE_CNOC_MNOC_CFG 19
-#define SLAVE_SNOC_CFG 20
-#define SLAVE_SNOC_MPU_CFG 21
-#define SLAVE_EBI1_PHY_CFG 22
-#define SLAVE_A0NOC_CFG 23
-#define SLAVE_PCIE_1_CFG 24
-#define SLAVE_PCIE_2_CFG 25
-#define SLAVE_PCIE_0_CFG 26
-#define SLAVE_PCIE20_AHB2PHY 27
-#define SLAVE_A0NOC_MPU_CFG 28
-#define SLAVE_UFS_CFG 29
-#define SLAVE_A1NOC_CFG 30
-#define SLAVE_A1NOC_MPU_CFG 31
-#define SLAVE_A2NOC_CFG 32
-#define SLAVE_A2NOC_MPU_CFG 33
-#define SLAVE_SSC_CFG 34
-#define SLAVE_A0NOC_SMMU_CFG 35
-#define SLAVE_A1NOC_SMMU_CFG 36
-#define SLAVE_A2NOC_SMMU_CFG 37
-#define SLAVE_LPASS_SMMU_CFG 38
-#define SLAVE_CNOC_MNOC_MMSS_CFG 39
-
-/* MNOC */
-#define MASTER_CNOC_MNOC_CFG 0
-#define MASTER_CPP 1
-#define MASTER_JPEG 2
-#define MASTER_MDP_PORT0 3
-#define MASTER_MDP_PORT1 4
-#define MASTER_ROTATOR 5
-#define MASTER_VIDEO_P0 6
-#define MASTER_VFE 7
-#define MASTER_SNOC_VMEM 8
-#define MASTER_VIDEO_P0_OCMEM 9
-#define MASTER_CNOC_MNOC_MMSS_CFG 10
-#define SLAVE_MNOC_BIMC 11
-#define SLAVE_VMEM 12
-#define SLAVE_SERVICE_MNOC 13
-#define SLAVE_MMAGIC_CFG 14
-#define SLAVE_CPR_CFG 15
-#define SLAVE_MISC_CFG 16
-#define SLAVE_VENUS_THROTTLE_CFG 17
-#define SLAVE_VENUS_CFG 18
-#define SLAVE_VMEM_CFG 19
-#define SLAVE_DSA_CFG 20
-#define SLAVE_MMSS_CLK_CFG 21
-#define SLAVE_DSA_MPU_CFG 22
-#define SLAVE_MNOC_MPU_CFG 23
-#define SLAVE_DISPLAY_CFG 24
-#define SLAVE_DISPLAY_THROTTLE_CFG 25
-#define SLAVE_CAMERA_CFG 26
-#define SLAVE_CAMERA_THROTTLE_CFG 27
-#define SLAVE_GRAPHICS_3D_CFG 28
-#define SLAVE_SMMU_MDP_CFG 29
-#define SLAVE_SMMU_ROT_CFG 30
-#define SLAVE_SMMU_VENUS_CFG 31
-#define SLAVE_SMMU_CPP_CFG 32
-#define SLAVE_SMMU_JPEG_CFG 33
-#define SLAVE_SMMU_VFE_CFG 34
-
-/* PNOC */
-#define MASTER_SNOC_PNOC 0
-#define MASTER_SDCC_1 1
-#define MASTER_SDCC_2 2
-#define MASTER_SDCC_4 3
-#define MASTER_USB_HS 4
-#define MASTER_BLSP_1 5
-#define MASTER_BLSP_2 6
-#define MASTER_TSIF 7
-#define SLAVE_PNOC_A1NOC 8
-#define SLAVE_USB_HS 9
-#define SLAVE_SDCC_2 10
-#define SLAVE_SDCC_4 11
-#define SLAVE_TSIF 12
-#define SLAVE_BLSP_2 13
-#define SLAVE_SDCC_1 14
-#define SLAVE_BLSP_1 15
-#define SLAVE_PDM 16
-#define SLAVE_AHB2PHY 17
-
-/* SNOC */
-#define MASTER_HMSS 0
-#define MASTER_QDSS_BAM 1
-#define MASTER_SNOC_CFG 2
-#define MASTER_BIMC_SNOC_0 3
-#define MASTER_BIMC_SNOC_1 4
-#define MASTER_A0NOC_SNOC 5
-#define MASTER_A1NOC_SNOC 6
-#define MASTER_A2NOC_SNOC 7
-#define MASTER_QDSS_ETR 8
-#define SLAVE_A0NOC_SNOC 9
-#define SLAVE_A1NOC_SNOC 10
-#define SLAVE_A2NOC_SNOC 11
-#define SLAVE_HMSS 12
-#define SLAVE_LPASS 13
-#define SLAVE_USB3 14
-#define SLAVE_SNOC_BIMC 15
-#define SLAVE_SNOC_CNOC 16
-#define SLAVE_IMEM 17
-#define SLAVE_PIMEM 18
-#define SLAVE_SNOC_VMEM 19
-#define SLAVE_SNOC_PNOC 20
-#define SLAVE_QDSS_STM 21
-#define SLAVE_PCIE_0 22
-#define SLAVE_PCIE_1 23
-#define SLAVE_PCIE_2 24
-#define SLAVE_SERVICE_SNOC 25
-
-#endif
diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h
deleted file mode 100644
index 61ef649..0000000
--- a/include/dt-bindings/interconnect/qcom,osm-l3.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2019 The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
-#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
-
-#define MASTER_OSM_L3_APPS 0
-#define SLAVE_OSM_L3 1
-
-#define MASTER_EPSS_L3_APPS 0
-#define SLAVE_EPSS_L3_SHARED 1
-
-#endif
diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h
deleted file mode 100644
index 67b500e..0000000
--- a/include/dt-bindings/interconnect/qcom,sdm845.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm SDM845 interconnect IDs
- *
- * Copyright (c) 2018, Linaro Ltd.
- * Author: Georgi Djakov <georgi.djakov@linaro.org>
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
-#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
-
-#define MASTER_A1NOC_CFG 0
-#define MASTER_TSIF 1
-#define MASTER_SDCC_2 2
-#define MASTER_SDCC_4 3
-#define MASTER_UFS_CARD 4
-#define MASTER_UFS_MEM 5
-#define MASTER_PCIE_0 6
-#define SLAVE_A1NOC_SNOC 7
-#define SLAVE_SERVICE_A1NOC 8
-#define SLAVE_ANOC_PCIE_A1NOC_SNOC 9
-#define MASTER_QUP_1 10
-
-#define MASTER_A2NOC_CFG 0
-#define MASTER_QDSS_BAM 1
-#define MASTER_CNOC_A2NOC 2
-#define MASTER_CRYPTO 3
-#define MASTER_IPA 4
-#define MASTER_PCIE_1 5
-#define MASTER_QDSS_ETR 6
-#define MASTER_USB3_0 7
-#define MASTER_USB3_1 8
-#define SLAVE_A2NOC_SNOC 9
-#define SLAVE_ANOC_PCIE_SNOC 10
-#define SLAVE_SERVICE_A2NOC 11
-#define MASTER_QUP_2 12
-
-#define MASTER_SPDM 0
-#define MASTER_TIC 1
-#define MASTER_SNOC_CNOC 2
-#define MASTER_QDSS_DAP 3
-#define SLAVE_A1NOC_CFG 4
-#define SLAVE_A2NOC_CFG 5
-#define SLAVE_AOP 6
-#define SLAVE_AOSS 7
-#define SLAVE_CAMERA_CFG 8
-#define SLAVE_CLK_CTL 9
-#define SLAVE_CDSP_CFG 10
-#define SLAVE_RBCPR_CX_CFG 11
-#define SLAVE_CRYPTO_0_CFG 12
-#define SLAVE_DCC_CFG 13
-#define SLAVE_CNOC_DDRSS 14
-#define SLAVE_DISPLAY_CFG 15
-#define SLAVE_GLM 16
-#define SLAVE_GFX3D_CFG 17
-#define SLAVE_IMEM_CFG 18
-#define SLAVE_IPA_CFG 19
-#define SLAVE_CNOC_MNOC_CFG 20
-#define SLAVE_PCIE_0_CFG 21
-#define SLAVE_PCIE_1_CFG 22
-#define SLAVE_PDM 23
-#define SLAVE_SOUTH_PHY_CFG 24
-#define SLAVE_PIMEM_CFG 25
-#define SLAVE_PRNG 26
-#define SLAVE_QDSS_CFG 27
-#define SLAVE_BLSP_2 28
-#define SLAVE_BLSP_1 29
-#define SLAVE_SDCC_2 30
-#define SLAVE_SDCC_4 31
-#define SLAVE_SNOC_CFG 32
-#define SLAVE_SPDM_WRAPPER 33
-#define SLAVE_SPSS_CFG 34
-#define SLAVE_TCSR 35
-#define SLAVE_TLMM_NORTH 36
-#define SLAVE_TLMM_SOUTH 37
-#define SLAVE_TSIF 38
-#define SLAVE_UFS_CARD_CFG 39
-#define SLAVE_UFS_MEM_CFG 40
-#define SLAVE_USB3_0 41
-#define SLAVE_USB3_1 42
-#define SLAVE_VENUS_CFG 43
-#define SLAVE_VSENSE_CTRL_CFG 44
-#define SLAVE_CNOC_A2NOC 45
-#define SLAVE_SERVICE_CNOC 46
-
-#define MASTER_CNOC_DC_NOC 0
-#define SLAVE_LLCC_CFG 1
-#define SLAVE_MEM_NOC_CFG 2
-
-#define MASTER_APPSS_PROC 0
-#define MASTER_GNOC_CFG 1
-#define SLAVE_GNOC_SNOC 2
-#define SLAVE_GNOC_MEM_NOC 3
-#define SLAVE_SERVICE_GNOC 4
-
-#define MASTER_TCU_0 0
-#define MASTER_MEM_NOC_CFG 1
-#define MASTER_GNOC_MEM_NOC 2
-#define MASTER_MNOC_HF_MEM_NOC 3
-#define MASTER_MNOC_SF_MEM_NOC 4
-#define MASTER_SNOC_GC_MEM_NOC 5
-#define MASTER_SNOC_SF_MEM_NOC 6
-#define MASTER_GFX3D 7
-#define SLAVE_MSS_PROC_MS_MPU_CFG 8
-#define SLAVE_MEM_NOC_GNOC 9
-#define SLAVE_LLCC 10
-#define SLAVE_MEM_NOC_SNOC 11
-#define SLAVE_SERVICE_MEM_NOC 12
-#define MASTER_LLCC 13
-#define SLAVE_EBI1 14
-
-#define MASTER_CNOC_MNOC_CFG 0
-#define MASTER_CAMNOC_HF0 1
-#define MASTER_CAMNOC_HF1 2
-#define MASTER_CAMNOC_SF 3
-#define MASTER_MDP0 4
-#define MASTER_MDP1 5
-#define MASTER_ROTATOR 6
-#define MASTER_VIDEO_P0 7
-#define MASTER_VIDEO_P1 8
-#define MASTER_VIDEO_PROC 9
-#define SLAVE_MNOC_SF_MEM_NOC 10
-#define SLAVE_MNOC_HF_MEM_NOC 11
-#define SLAVE_SERVICE_MNOC 12
-#define MASTER_CAMNOC_HF0_UNCOMP 13
-#define MASTER_CAMNOC_HF1_UNCOMP 14
-#define MASTER_CAMNOC_SF_UNCOMP 15
-#define SLAVE_CAMNOC_UNCOMP 16
-
-#define MASTER_SNOC_CFG 0
-#define MASTER_A1NOC_SNOC 1
-#define MASTER_A2NOC_SNOC 2
-#define MASTER_GNOC_SNOC 3
-#define MASTER_MEM_NOC_SNOC 4
-#define MASTER_ANOC_PCIE_SNOC 5
-#define MASTER_PIMEM 6
-#define MASTER_GIC 7
-#define SLAVE_APPSS 8
-#define SLAVE_SNOC_CNOC 9
-#define SLAVE_SNOC_MEM_NOC_GC 10
-#define SLAVE_SNOC_MEM_NOC_SF 11
-#define SLAVE_IMEM 12
-#define SLAVE_PCIE_0 13
-#define SLAVE_PCIE_1 14
-#define SLAVE_PIMEM 15
-#define SLAVE_SERVICE_SNOC 16
-#define SLAVE_QDSS_STM 17
-#define SLAVE_TCU 18
-
-#endif
diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h
deleted file mode 100644
index 4edec4c..0000000
--- a/include/dt-bindings/phy/phy-qcom-qmp.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
-/*
- * Qualcomm QMP PHY constants
- *
- * Copyright (C) 2022 Linaro Limited
- */
-
-#ifndef _DT_BINDINGS_PHY_QMP
-#define _DT_BINDINGS_PHY_QMP
-
-/* QMP USB4-USB3-DP clocks */
-#define QMP_USB43DP_USB3_PIPE_CLK 0
-#define QMP_USB43DP_DP_LINK_CLK 1
-#define QMP_USB43DP_DP_VCO_DIV_CLK 2
-
-/* QMP USB4-USB3-DP PHYs */
-#define QMP_USB43DP_USB3_PHY 0
-#define QMP_USB43DP_DP_PHY 1
-
-#endif /* _DT_BINDINGS_PHY_QMP */
diff --git a/include/dt-bindings/phy/phy-qcom-qusb2.h b/include/dt-bindings/phy/phy-qcom-qusb2.h
deleted file mode 100644
index 5c5e4d8..0000000
--- a/include/dt-bindings/phy/phy-qcom-qusb2.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_
-#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_
-
-/* PHY HSTX TRIM bit values (24mA to 15mA) */
-#define QUSB2_V2_HSTX_TRIM_24_0_MA 0x0
-#define QUSB2_V2_HSTX_TRIM_23_4_MA 0x1
-#define QUSB2_V2_HSTX_TRIM_22_8_MA 0x2
-#define QUSB2_V2_HSTX_TRIM_22_2_MA 0x3
-#define QUSB2_V2_HSTX_TRIM_21_6_MA 0x4
-#define QUSB2_V2_HSTX_TRIM_21_0_MA 0x5
-#define QUSB2_V2_HSTX_TRIM_20_4_MA 0x6
-#define QUSB2_V2_HSTX_TRIM_19_8_MA 0x7
-#define QUSB2_V2_HSTX_TRIM_19_2_MA 0x8
-#define QUSB2_V2_HSTX_TRIM_18_6_MA 0x9
-#define QUSB2_V2_HSTX_TRIM_18_0_MA 0xa
-#define QUSB2_V2_HSTX_TRIM_17_4_MA 0xb
-#define QUSB2_V2_HSTX_TRIM_16_8_MA 0xc
-#define QUSB2_V2_HSTX_TRIM_16_2_MA 0xd
-#define QUSB2_V2_HSTX_TRIM_15_6_MA 0xe
-#define QUSB2_V2_HSTX_TRIM_15_0_MA 0xf
-
-/* PHY PREEMPHASIS bit values */
-#define QUSB2_V2_PREEMPHASIS_NONE 0
-#define QUSB2_V2_PREEMPHASIS_5_PERCENT 1
-#define QUSB2_V2_PREEMPHASIS_10_PERCENT 2
-#define QUSB2_V2_PREEMPHASIS_15_PERCENT 3
-
-/* PHY PREEMPHASIS-WIDTH bit values */
-#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT 0
-#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT 1
-
-#endif
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
deleted file mode 100644
index e5df5ce..0000000
--- a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for the Qualcomm PMIC GPIO binding.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
-#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
-
-#define PMIC_GPIO_PULL_UP_30 0
-#define PMIC_GPIO_PULL_UP_1P5 1
-#define PMIC_GPIO_PULL_UP_31P5 2
-#define PMIC_GPIO_PULL_UP_1P5_30 3
-
-#define PMIC_GPIO_STRENGTH_NO 0
-#define PMIC_GPIO_STRENGTH_HIGH 1
-#define PMIC_GPIO_STRENGTH_MED 2
-#define PMIC_GPIO_STRENGTH_LOW 3
-
-/*
- * Note: PM8018 GPIO3 and GPIO4 are supporting
- * only S3 and L2 options (1.8V)
- */
-#define PM8018_GPIO_L6 0
-#define PM8018_GPIO_L5 1
-#define PM8018_GPIO_S3 2
-#define PM8018_GPIO_L14 3
-#define PM8018_GPIO_L2 4
-#define PM8018_GPIO_L4 5
-#define PM8018_GPIO_VDD 6
-
-/*
- * Note: PM8038 GPIO7 and GPIO8 are supporting
- * only L11 and L4 options (1.8V)
- */
-#define PM8038_GPIO_VPH 0
-#define PM8038_GPIO_BB 1
-#define PM8038_GPIO_L11 2
-#define PM8038_GPIO_L15 3
-#define PM8038_GPIO_L4 4
-#define PM8038_GPIO_L3 5
-#define PM8038_GPIO_L17 6
-
-#define PM8058_GPIO_VPH 0
-#define PM8058_GPIO_BB 1
-#define PM8058_GPIO_S3 2
-#define PM8058_GPIO_L3 3
-#define PM8058_GPIO_L7 4
-#define PM8058_GPIO_L6 5
-#define PM8058_GPIO_L5 6
-#define PM8058_GPIO_L2 7
-
-/*
- * Note: PM8916 GPIO1 and GPIO2 are supporting
- * only L2(1.15V) and L5(1.8V) options
- */
-#define PM8916_GPIO_VPH 0
-#define PM8916_GPIO_L2 2
-#define PM8916_GPIO_L5 3
-
-#define PM8917_GPIO_VPH 0
-#define PM8917_GPIO_S4 2
-#define PM8917_GPIO_L15 3
-#define PM8917_GPIO_L4 4
-#define PM8917_GPIO_L3 5
-#define PM8917_GPIO_L17 6
-
-#define PM8921_GPIO_VPH 0
-#define PM8921_GPIO_BB 1
-#define PM8921_GPIO_S4 2
-#define PM8921_GPIO_L15 3
-#define PM8921_GPIO_L4 4
-#define PM8921_GPIO_L3 5
-#define PM8921_GPIO_L17 6
-
-/*
- * Note: PM8941 gpios from 15 to 18 are supporting
- * only S3 and L6 options (1.8V)
- */
-#define PM8941_GPIO_VPH 0
-#define PM8941_GPIO_L1 1
-#define PM8941_GPIO_S3 2
-#define PM8941_GPIO_L6 3
-
-/*
- * Note: PMA8084 gpios from 15 to 18 are supporting
- * only S4 and L6 options (1.8V)
- */
-#define PMA8084_GPIO_VPH 0
-#define PMA8084_GPIO_L1 1
-#define PMA8084_GPIO_S4 2
-#define PMA8084_GPIO_L6 3
-
-#define PM8994_GPIO_VPH 0
-#define PM8994_GPIO_S4 2
-#define PM8994_GPIO_L12 3
-
-/* To be used with "function" */
-#define PMIC_GPIO_FUNC_NORMAL "normal"
-#define PMIC_GPIO_FUNC_PAIRED "paired"
-#define PMIC_GPIO_FUNC_FUNC1 "func1"
-#define PMIC_GPIO_FUNC_FUNC2 "func2"
-#define PMIC_GPIO_FUNC_FUNC3 "func3"
-#define PMIC_GPIO_FUNC_FUNC4 "func4"
-#define PMIC_GPIO_FUNC_DTEST1 "dtest1"
-#define PMIC_GPIO_FUNC_DTEST2 "dtest2"
-#define PMIC_GPIO_FUNC_DTEST3 "dtest3"
-#define PMIC_GPIO_FUNC_DTEST4 "dtest4"
-
-#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2
-
-#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2
-#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2
-#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2
-#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2
-#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2
-#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1
-
-#define PM8916_GPIO1_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
-#define PM8916_GPIO1_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
-#define PM8916_GPIO2_DIV_CLK PMIC_GPIO_FUNC_FUNC1
-#define PM8916_GPIO2_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2
-#define PM8916_GPIO3_KEYP_DRV PMIC_GPIO_FUNC_FUNC1
-#define PM8916_GPIO4_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
-
-#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1
-#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
-#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2
-#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
-#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1
-#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2
-
-#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
-#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1
-#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2
-#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
-#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2
-#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
-#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1
-#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2
-
-#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1
-#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1
-#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
-#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
-#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1
-#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2
-#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
-
-#endif
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
deleted file mode 100644
index 32e66ee..0000000
--- a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for the Qualcomm PMIC's
- * Multi-Purpose Pin binding.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
-#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
-
-/* power-source */
-
-/* Digital Input/Output: level [PM8058] */
-#define PM8058_MPP_VPH 0
-#define PM8058_MPP_S3 1
-#define PM8058_MPP_L2 2
-#define PM8058_MPP_L3 3
-
-/* Digital Input/Output: level [PM8901] */
-#define PM8901_MPP_MSMIO 0
-#define PM8901_MPP_DIG 1
-#define PM8901_MPP_L5 2
-#define PM8901_MPP_S4 3
-#define PM8901_MPP_VPH 4
-
-/* Digital Input/Output: level [PM8921] */
-#define PM8921_MPP_S4 1
-#define PM8921_MPP_L15 3
-#define PM8921_MPP_L17 4
-#define PM8921_MPP_VPH 7
-
-/* Digital Input/Output: level [PM8821] */
-#define PM8821_MPP_1P8 0
-#define PM8821_MPP_VPH 7
-
-/* Digital Input/Output: level [PM8018] */
-#define PM8018_MPP_L4 0
-#define PM8018_MPP_L14 1
-#define PM8018_MPP_S3 2
-#define PM8018_MPP_L6 3
-#define PM8018_MPP_L2 4
-#define PM8018_MPP_L5 5
-#define PM8018_MPP_VPH 7
-
-/* Digital Input/Output: level [PM8038] */
-#define PM8038_MPP_L20 0
-#define PM8038_MPP_L11 1
-#define PM8038_MPP_L5 2
-#define PM8038_MPP_L15 3
-#define PM8038_MPP_L17 4
-#define PM8038_MPP_VPH 7
-
-#define PM8841_MPP_VPH 0
-#define PM8841_MPP_S3 2
-
-#define PM8916_MPP_VPH 0
-#define PM8916_MPP_L2 2
-#define PM8916_MPP_L5 3
-
-#define PM8941_MPP_VPH 0
-#define PM8941_MPP_L1 1
-#define PM8941_MPP_S3 2
-#define PM8941_MPP_L6 3
-
-#define PMA8084_MPP_VPH 0
-#define PMA8084_MPP_L1 1
-#define PMA8084_MPP_S4 2
-#define PMA8084_MPP_L6 3
-
-#define PM8994_MPP_VPH 0
-/* Only supported for MPP_05-MPP_08 */
-#define PM8994_MPP_L19 1
-#define PM8994_MPP_S4 2
-#define PM8994_MPP_L12 3
-
-/*
- * Analog Input - Set the source for analog input.
- * To be used with "qcom,amux-route" property
- */
-#define PMIC_MPP_AMUX_ROUTE_CH5 0
-#define PMIC_MPP_AMUX_ROUTE_CH6 1
-#define PMIC_MPP_AMUX_ROUTE_CH7 2
-#define PMIC_MPP_AMUX_ROUTE_CH8 3
-#define PMIC_MPP_AMUX_ROUTE_ABUS1 4
-#define PMIC_MPP_AMUX_ROUTE_ABUS2 5
-#define PMIC_MPP_AMUX_ROUTE_ABUS3 6
-#define PMIC_MPP_AMUX_ROUTE_ABUS4 7
-
-/* Analog Output: level */
-#define PMIC_MPP_AOUT_LVL_1V25 0
-#define PMIC_MPP_AOUT_LVL_1V25_2 1
-#define PMIC_MPP_AOUT_LVL_0V625 2
-#define PMIC_MPP_AOUT_LVL_0V3125 3
-#define PMIC_MPP_AOUT_LVL_MPP 4
-#define PMIC_MPP_AOUT_LVL_ABUS1 5
-#define PMIC_MPP_AOUT_LVL_ABUS2 6
-#define PMIC_MPP_AOUT_LVL_ABUS3 7
-
-/* To be used with "function" */
-#define PMIC_MPP_FUNC_NORMAL "normal"
-#define PMIC_MPP_FUNC_PAIRED "paired"
-#define PMIC_MPP_FUNC_DTEST1 "dtest1"
-#define PMIC_MPP_FUNC_DTEST2 "dtest2"
-#define PMIC_MPP_FUNC_DTEST3 "dtest3"
-#define PMIC_MPP_FUNC_DTEST4 "dtest4"
-
-#endif
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
deleted file mode 100644
index 7f4e298..0000000
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ /dev/null
@@ -1,412 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
-
-#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
-#define _DT_BINDINGS_POWER_QCOM_RPMPD_H
-
-/* SA8775P Power Domain Indexes */
-#define SA8775P_CX 0
-#define SA8775P_CX_AO 1
-#define SA8775P_DDR 2
-#define SA8775P_EBI 3
-#define SA8775P_GFX 4
-#define SA8775P_LCX 5
-#define SA8775P_LMX 6
-#define SA8775P_MMCX 7
-#define SA8775P_MMCX_AO 8
-#define SA8775P_MSS 9
-#define SA8775P_MX 10
-#define SA8775P_MX_AO 11
-#define SA8775P_MXC 12
-#define SA8775P_MXC_AO 13
-#define SA8775P_NSP0 14
-#define SA8775P_NSP1 15
-#define SA8775P_XO 16
-
-/* SDM670 Power Domain Indexes */
-#define SDM670_MX 0
-#define SDM670_MX_AO 1
-#define SDM670_CX 2
-#define SDM670_CX_AO 3
-#define SDM670_LMX 4
-#define SDM670_LCX 5
-#define SDM670_GFX 6
-#define SDM670_MSS 7
-
-/* SDM845 Power Domain Indexes */
-#define SDM845_EBI 0
-#define SDM845_MX 1
-#define SDM845_MX_AO 2
-#define SDM845_CX 3
-#define SDM845_CX_AO 4
-#define SDM845_LMX 5
-#define SDM845_LCX 6
-#define SDM845_GFX 7
-#define SDM845_MSS 8
-
-/* SDX55 Power Domain Indexes */
-#define SDX55_MSS 0
-#define SDX55_MX 1
-#define SDX55_CX 2
-
-/* SDX65 Power Domain Indexes */
-#define SDX65_MSS 0
-#define SDX65_MX 1
-#define SDX65_MX_AO 2
-#define SDX65_CX 3
-#define SDX65_CX_AO 4
-#define SDX65_MXC 5
-
-/* SM6350 Power Domain Indexes */
-#define SM6350_CX 0
-#define SM6350_GFX 1
-#define SM6350_LCX 2
-#define SM6350_LMX 3
-#define SM6350_MSS 4
-#define SM6350_MX 5
-
-/* SM6350 Power Domain Indexes */
-#define SM6375_VDDCX 0
-#define SM6375_VDDCX_AO 1
-#define SM6375_VDDCX_VFL 2
-#define SM6375_VDDMX 3
-#define SM6375_VDDMX_AO 4
-#define SM6375_VDDMX_VFL 5
-#define SM6375_VDDGX 6
-#define SM6375_VDDGX_AO 7
-#define SM6375_VDD_LPI_CX 8
-#define SM6375_VDD_LPI_MX 9
-
-/* SM8150 Power Domain Indexes */
-#define SM8150_MSS 0
-#define SM8150_EBI 1
-#define SM8150_LMX 2
-#define SM8150_LCX 3
-#define SM8150_GFX 4
-#define SM8150_MX 5
-#define SM8150_MX_AO 6
-#define SM8150_CX 7
-#define SM8150_CX_AO 8
-#define SM8150_MMCX 9
-#define SM8150_MMCX_AO 10
-
-/* SA8155P is a special case, kept for backwards compatibility */
-#define SA8155P_CX SM8150_CX
-#define SA8155P_CX_AO SM8150_CX_AO
-#define SA8155P_EBI SM8150_EBI
-#define SA8155P_GFX SM8150_GFX
-#define SA8155P_MSS SM8150_MSS
-#define SA8155P_MX SM8150_MX
-#define SA8155P_MX_AO SM8150_MX_AO
-
-/* SM8250 Power Domain Indexes */
-#define SM8250_CX 0
-#define SM8250_CX_AO 1
-#define SM8250_EBI 2
-#define SM8250_GFX 3
-#define SM8250_LCX 4
-#define SM8250_LMX 5
-#define SM8250_MMCX 6
-#define SM8250_MMCX_AO 7
-#define SM8250_MX 8
-#define SM8250_MX_AO 9
-
-/* SM8350 Power Domain Indexes */
-#define SM8350_CX 0
-#define SM8350_CX_AO 1
-#define SM8350_EBI 2
-#define SM8350_GFX 3
-#define SM8350_LCX 4
-#define SM8350_LMX 5
-#define SM8350_MMCX 6
-#define SM8350_MMCX_AO 7
-#define SM8350_MX 8
-#define SM8350_MX_AO 9
-#define SM8350_MXC 10
-#define SM8350_MXC_AO 11
-#define SM8350_MSS 12
-
-/* SM8450 Power Domain Indexes */
-#define SM8450_CX 0
-#define SM8450_CX_AO 1
-#define SM8450_EBI 2
-#define SM8450_GFX 3
-#define SM8450_LCX 4
-#define SM8450_LMX 5
-#define SM8450_MMCX 6
-#define SM8450_MMCX_AO 7
-#define SM8450_MX 8
-#define SM8450_MX_AO 9
-#define SM8450_MXC 10
-#define SM8450_MXC_AO 11
-#define SM8450_MSS 12
-
-/* SM8550 Power Domain Indexes */
-#define SM8550_CX 0
-#define SM8550_CX_AO 1
-#define SM8550_EBI 2
-#define SM8550_GFX 3
-#define SM8550_LCX 4
-#define SM8550_LMX 5
-#define SM8550_MMCX 6
-#define SM8550_MMCX_AO 7
-#define SM8550_MX 8
-#define SM8550_MX_AO 9
-#define SM8550_MXC 10
-#define SM8550_MXC_AO 11
-#define SM8550_MSS 12
-#define SM8550_NSP 13
-
-/* QDU1000/QRU1000 Power Domain Indexes */
-#define QDU1000_EBI 0
-#define QDU1000_MSS 1
-#define QDU1000_CX 2
-#define QDU1000_MX 3
-
-/* SC7180 Power Domain Indexes */
-#define SC7180_CX 0
-#define SC7180_CX_AO 1
-#define SC7180_GFX 2
-#define SC7180_MX 3
-#define SC7180_MX_AO 4
-#define SC7180_LMX 5
-#define SC7180_LCX 6
-#define SC7180_MSS 7
-
-/* SC7280 Power Domain Indexes */
-#define SC7280_CX 0
-#define SC7280_CX_AO 1
-#define SC7280_EBI 2
-#define SC7280_GFX 3
-#define SC7280_MX 4
-#define SC7280_MX_AO 5
-#define SC7280_LMX 6
-#define SC7280_LCX 7
-#define SC7280_MSS 8
-
-/* SC8180X Power Domain Indexes */
-#define SC8180X_CX 0
-#define SC8180X_CX_AO 1
-#define SC8180X_EBI 2
-#define SC8180X_GFX 3
-#define SC8180X_LCX 4
-#define SC8180X_LMX 5
-#define SC8180X_MMCX 6
-#define SC8180X_MMCX_AO 7
-#define SC8180X_MSS 8
-#define SC8180X_MX 9
-#define SC8180X_MX_AO 10
-
-/* SC8280XP Power Domain Indexes */
-#define SC8280XP_CX 0
-#define SC8280XP_CX_AO 1
-#define SC8280XP_DDR 2
-#define SC8280XP_EBI 3
-#define SC8280XP_GFX 4
-#define SC8280XP_LCX 5
-#define SC8280XP_LMX 6
-#define SC8280XP_MMCX 7
-#define SC8280XP_MMCX_AO 8
-#define SC8280XP_MSS 9
-#define SC8280XP_MX 10
-#define SC8280XP_MXC 12
-#define SC8280XP_MX_AO 11
-#define SC8280XP_NSP 13
-#define SC8280XP_QPHY 14
-#define SC8280XP_XO 15
-
-/* SDM845 Power Domain performance levels */
-#define RPMH_REGULATOR_LEVEL_RETENTION 16
-#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60
-#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96
-#define RPMH_REGULATOR_LEVEL_SVS 128
-#define RPMH_REGULATOR_LEVEL_SVS_L0 144
-#define RPMH_REGULATOR_LEVEL_SVS_L1 192
-#define RPMH_REGULATOR_LEVEL_SVS_L2 224
-#define RPMH_REGULATOR_LEVEL_NOM 256
-#define RPMH_REGULATOR_LEVEL_NOM_L0 288
-#define RPMH_REGULATOR_LEVEL_NOM_L1 320
-#define RPMH_REGULATOR_LEVEL_NOM_L2 336
-#define RPMH_REGULATOR_LEVEL_TURBO 384
-#define RPMH_REGULATOR_LEVEL_TURBO_L0 400
-#define RPMH_REGULATOR_LEVEL_TURBO_L1 416
-#define RPMH_REGULATOR_LEVEL_TURBO_L2 432
-#define RPMH_REGULATOR_LEVEL_TURBO_L3 448
-#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464
-#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480
-
-/* MDM9607 Power Domains */
-#define MDM9607_VDDCX 0
-#define MDM9607_VDDCX_AO 1
-#define MDM9607_VDDCX_VFL 2
-#define MDM9607_VDDMX 3
-#define MDM9607_VDDMX_AO 4
-#define MDM9607_VDDMX_VFL 5
-
-/* MSM8226 Power Domain Indexes */
-#define MSM8226_VDDCX 0
-#define MSM8226_VDDCX_AO 1
-#define MSM8226_VDDCX_VFC 2
-
-/* MSM8939 Power Domains */
-#define MSM8939_VDDMDCX 0
-#define MSM8939_VDDMDCX_AO 1
-#define MSM8939_VDDMDCX_VFC 2
-#define MSM8939_VDDCX 3
-#define MSM8939_VDDCX_AO 4
-#define MSM8939_VDDCX_VFC 5
-#define MSM8939_VDDMX 6
-#define MSM8939_VDDMX_AO 7
-
-/* MSM8916 Power Domain Indexes */
-#define MSM8916_VDDCX 0
-#define MSM8916_VDDCX_AO 1
-#define MSM8916_VDDCX_VFC 2
-#define MSM8916_VDDMX 3
-#define MSM8916_VDDMX_AO 4
-
-/* MSM8909 Power Domain Indexes */
-#define MSM8909_VDDCX MSM8916_VDDCX
-#define MSM8909_VDDCX_AO MSM8916_VDDCX_AO
-#define MSM8909_VDDCX_VFC MSM8916_VDDCX_VFC
-#define MSM8909_VDDMX MSM8916_VDDMX
-#define MSM8909_VDDMX_AO MSM8916_VDDMX_AO
-
-/* MSM8917 Power Domain Indexes */
-#define MSM8917_VDDCX 0
-#define MSM8917_VDDCX_AO 1
-#define MSM8917_VDDCX_VFL 2
-#define MSM8917_VDDMX 3
-#define MSM8917_VDDMX_AO 4
-
-/* MSM8937 Power Domain Indexes */
-#define MSM8937_VDDCX MSM8917_VDDCX
-#define MSM8937_VDDCX_AO MSM8917_VDDCX_AO
-#define MSM8937_VDDCX_VFL MSM8917_VDDCX_VFL
-#define MSM8937_VDDMX MSM8917_VDDMX
-#define MSM8937_VDDMX_AO MSM8917_VDDMX_AO
-
-/* QM215 Power Domain Indexes */
-#define QM215_VDDCX MSM8917_VDDCX
-#define QM215_VDDCX_AO MSM8917_VDDCX_AO
-#define QM215_VDDCX_VFL MSM8917_VDDCX_VFL
-#define QM215_VDDMX MSM8917_VDDMX
-#define QM215_VDDMX_AO MSM8917_VDDMX_AO
-
-/* MSM8953 Power Domain Indexes */
-#define MSM8953_VDDMD 0
-#define MSM8953_VDDMD_AO 1
-#define MSM8953_VDDCX 2
-#define MSM8953_VDDCX_AO 3
-#define MSM8953_VDDCX_VFL 4
-#define MSM8953_VDDMX 5
-#define MSM8953_VDDMX_AO 6
-
-/* MSM8976 Power Domain Indexes */
-#define MSM8976_VDDCX 0
-#define MSM8976_VDDCX_AO 1
-#define MSM8976_VDDCX_VFL 2
-#define MSM8976_VDDMX 3
-#define MSM8976_VDDMX_AO 4
-#define MSM8976_VDDMX_VFL 5
-
-/* MSM8994 Power Domain Indexes */
-#define MSM8994_VDDCX 0
-#define MSM8994_VDDCX_AO 1
-#define MSM8994_VDDCX_VFC 2
-#define MSM8994_VDDMX 3
-#define MSM8994_VDDMX_AO 4
-#define MSM8994_VDDGFX 5
-#define MSM8994_VDDGFX_VFC 6
-
-/* MSM8996 Power Domain Indexes */
-#define MSM8996_VDDCX 0
-#define MSM8996_VDDCX_AO 1
-#define MSM8996_VDDCX_VFC 2
-#define MSM8996_VDDMX 3
-#define MSM8996_VDDMX_AO 4
-#define MSM8996_VDDSSCX 5
-#define MSM8996_VDDSSCX_VFC 6
-
-/* MSM8998 Power Domain Indexes */
-#define MSM8998_VDDCX 0
-#define MSM8998_VDDCX_AO 1
-#define MSM8998_VDDCX_VFL 2
-#define MSM8998_VDDMX 3
-#define MSM8998_VDDMX_AO 4
-#define MSM8998_VDDMX_VFL 5
-#define MSM8998_SSCCX 6
-#define MSM8998_SSCCX_VFL 7
-#define MSM8998_SSCMX 8
-#define MSM8998_SSCMX_VFL 9
-
-/* QCS404 Power Domains */
-#define QCS404_VDDMX 0
-#define QCS404_VDDMX_AO 1
-#define QCS404_VDDMX_VFL 2
-#define QCS404_LPICX 3
-#define QCS404_LPICX_VFL 4
-#define QCS404_LPIMX 5
-#define QCS404_LPIMX_VFL 6
-
-/* SDM660 Power Domains */
-#define SDM660_VDDCX 0
-#define SDM660_VDDCX_AO 1
-#define SDM660_VDDCX_VFL 2
-#define SDM660_VDDMX 3
-#define SDM660_VDDMX_AO 4
-#define SDM660_VDDMX_VFL 5
-#define SDM660_SSCCX 6
-#define SDM660_SSCCX_VFL 7
-#define SDM660_SSCMX 8
-#define SDM660_SSCMX_VFL 9
-
-/* SM6115 Power Domains */
-#define SM6115_VDDCX 0
-#define SM6115_VDDCX_AO 1
-#define SM6115_VDDCX_VFL 2
-#define SM6115_VDDMX 3
-#define SM6115_VDDMX_AO 4
-#define SM6115_VDDMX_VFL 5
-#define SM6115_VDD_LPI_CX 6
-#define SM6115_VDD_LPI_MX 7
-
-/* SM6125 Power Domains */
-#define SM6125_VDDCX 0
-#define SM6125_VDDCX_AO 1
-#define SM6125_VDDCX_VFL 2
-#define SM6125_VDDMX 3
-#define SM6125_VDDMX_AO 4
-#define SM6125_VDDMX_VFL 5
-
-/* QCM2290 Power Domains */
-#define QCM2290_VDDCX 0
-#define QCM2290_VDDCX_AO 1
-#define QCM2290_VDDCX_VFL 2
-#define QCM2290_VDDMX 3
-#define QCM2290_VDDMX_AO 4
-#define QCM2290_VDDMX_VFL 5
-#define QCM2290_VDD_LPI_CX 6
-#define QCM2290_VDD_LPI_MX 7
-
-/* RPM SMD Power Domain performance levels */
-#define RPM_SMD_LEVEL_RETENTION 16
-#define RPM_SMD_LEVEL_RETENTION_PLUS 32
-#define RPM_SMD_LEVEL_MIN_SVS 48
-#define RPM_SMD_LEVEL_LOW_SVS 64
-#define RPM_SMD_LEVEL_SVS 128
-#define RPM_SMD_LEVEL_SVS_PLUS 192
-#define RPM_SMD_LEVEL_NOM 256
-#define RPM_SMD_LEVEL_NOM_PLUS 320
-#define RPM_SMD_LEVEL_TURBO 384
-#define RPM_SMD_LEVEL_TURBO_NO_CPR 416
-#define RPM_SMD_LEVEL_TURBO_HIGH 448
-#define RPM_SMD_LEVEL_BINNING 512
-
-#endif
diff --git a/include/dt-bindings/regulator/qcom,rpmh-regulator.h b/include/dt-bindings/regulator/qcom,rpmh-regulator.h
deleted file mode 100644
index 86713dc..0000000
--- a/include/dt-bindings/regulator/qcom,rpmh-regulator.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
-
-#ifndef __QCOM_RPMH_REGULATOR_H
-#define __QCOM_RPMH_REGULATOR_H
-
-/*
- * These mode constants may be used to specify modes for various RPMh regulator
- * device tree properties (e.g. regulator-initial-mode). Each type of regulator
- * supports a subset of the possible modes.
- *
- * %RPMH_REGULATOR_MODE_RET: Retention mode in which only an extremely small
- * load current is allowed. This mode is supported
- * by LDO and SMPS type regulators.
- * %RPMH_REGULATOR_MODE_LPM: Low power mode in which a small load current is
- * allowed. This mode corresponds to PFM for SMPS
- * and BOB type regulators. This mode is supported
- * by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type
- * regulators.
- * %RPMH_REGULATOR_MODE_AUTO: Auto mode in which the regulator hardware
- * automatically switches between LPM and HPM based
- * upon the real-time load current. This mode is
- * supported by HFSMPS, BOB, and PMIC4 FTSMPS type
- * regulators.
- * %RPMH_REGULATOR_MODE_HPM: High power mode in which the full rated current
- * of the regulator is allowed. This mode
- * corresponds to PWM for SMPS and BOB type
- * regulators. This mode is supported by all types
- * of regulators.
- */
-#define RPMH_REGULATOR_MODE_RET 0
-#define RPMH_REGULATOR_MODE_LPM 1
-#define RPMH_REGULATOR_MODE_AUTO 2
-#define RPMH_REGULATOR_MODE_HPM 3
-
-#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8916.h b/include/dt-bindings/reset/qcom,gcc-msm8916.h
deleted file mode 100644
index 1f9be10..0000000
--- a/include/dt-bindings/reset/qcom,gcc-msm8916.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2015 Linaro Limited
- */
-
-#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H
-#define _DT_BINDINGS_RESET_MSM_GCC_8916_H
-
-#define GCC_BLSP1_BCR 0
-#define GCC_BLSP1_QUP1_BCR 1
-#define GCC_BLSP1_UART1_BCR 2
-#define GCC_BLSP1_QUP2_BCR 3
-#define GCC_BLSP1_UART2_BCR 4
-#define GCC_BLSP1_QUP3_BCR 5
-#define GCC_BLSP1_QUP4_BCR 6
-#define GCC_BLSP1_QUP5_BCR 7
-#define GCC_BLSP1_QUP6_BCR 8
-#define GCC_IMEM_BCR 9
-#define GCC_SMMU_BCR 10
-#define GCC_APSS_TCU_BCR 11
-#define GCC_SMMU_XPU_BCR 12
-#define GCC_PCNOC_TBU_BCR 13
-#define GCC_PRNG_BCR 14
-#define GCC_BOOT_ROM_BCR 15
-#define GCC_CRYPTO_BCR 16
-#define GCC_SEC_CTRL_BCR 17
-#define GCC_AUDIO_CORE_BCR 18
-#define GCC_ULT_AUDIO_BCR 19
-#define GCC_DEHR_BCR 20
-#define GCC_SYSTEM_NOC_BCR 21
-#define GCC_PCNOC_BCR 22
-#define GCC_TCSR_BCR 23
-#define GCC_QDSS_BCR 24
-#define GCC_DCD_BCR 25
-#define GCC_MSG_RAM_BCR 26
-#define GCC_MPM_BCR 27
-#define GCC_SPMI_BCR 28
-#define GCC_SPDM_BCR 29
-#define GCC_MM_SPDM_BCR 30
-#define GCC_BIMC_BCR 31
-#define GCC_RBCPR_BCR 32
-#define GCC_TLMM_BCR 33
-#define GCC_USB_HS_BCR 34
-#define GCC_USB2A_PHY_BCR 35
-#define GCC_SDCC1_BCR 36
-#define GCC_SDCC2_BCR 37
-#define GCC_PDM_BCR 38
-#define GCC_SNOC_BUS_TIMEOUT0_BCR 39
-#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40
-#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41
-#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42
-#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43
-#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44
-#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45
-#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46
-#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47
-#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48
-#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49
-#define GCC_MMSS_BCR 50
-#define GCC_VENUS0_BCR 51
-#define GCC_MDSS_BCR 52
-#define GCC_CAMSS_PHY0_BCR 53
-#define GCC_CAMSS_CSI0_BCR 54
-#define GCC_CAMSS_CSI0PHY_BCR 55
-#define GCC_CAMSS_CSI0RDI_BCR 56
-#define GCC_CAMSS_CSI0PIX_BCR 57
-#define GCC_CAMSS_PHY1_BCR 58
-#define GCC_CAMSS_CSI1_BCR 59
-#define GCC_CAMSS_CSI1PHY_BCR 60
-#define GCC_CAMSS_CSI1RDI_BCR 61
-#define GCC_CAMSS_CSI1PIX_BCR 62
-#define GCC_CAMSS_ISPIF_BCR 63
-#define GCC_CAMSS_CCI_BCR 64
-#define GCC_CAMSS_MCLK0_BCR 65
-#define GCC_CAMSS_MCLK1_BCR 66
-#define GCC_CAMSS_GP0_BCR 67
-#define GCC_CAMSS_GP1_BCR 68
-#define GCC_CAMSS_TOP_BCR 69
-#define GCC_CAMSS_MICRO_BCR 70
-#define GCC_CAMSS_JPEG_BCR 71
-#define GCC_CAMSS_VFE_BCR 72
-#define GCC_CAMSS_CSI_VFE0_BCR 73
-#define GCC_OXILI_BCR 74
-#define GCC_GMEM_BCR 75
-#define GCC_CAMSS_AHB_BCR 76
-#define GCC_MDP_TBU_BCR 77
-#define GCC_GFX_TBU_BCR 78
-#define GCC_GFX_TCU_BCR 79
-#define GCC_MSS_TBU_AXI_BCR 80
-#define GCC_MSS_TBU_GSS_AXI_BCR 81
-#define GCC_MSS_TBU_Q6_AXI_BCR 82
-#define GCC_GTCU_AHB_BCR 83
-#define GCC_SMMU_CFG_BCR 84
-#define GCC_VFE_TBU_BCR 85
-#define GCC_VENUS_TBU_BCR 86
-#define GCC_JPEG_TBU_BCR 87
-#define GCC_PRONTO_TBU_BCR 88
-#define GCC_SMMU_CATS_BCR 89
-
-#endif
diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h
deleted file mode 100644
index 476c5fc..0000000
--- a/include/dt-bindings/reset/qcom,sdm845-aoss.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
-#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
-
-#define AOSS_CC_MSS_RESTART 0
-#define AOSS_CC_CAMSS_RESTART 1
-#define AOSS_CC_VENUS_RESTART 2
-#define AOSS_CC_GPU_RESTART 3
-#define AOSS_CC_DISPSS_RESTART 4
-#define AOSS_CC_WCSS_RESTART 5
-#define AOSS_CC_LPASS_RESTART 6
-
-#endif
diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
deleted file mode 100644
index 03a0c0e..0000000
--- a/include/dt-bindings/reset/qcom,sdm845-pdc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H
-#define _DT_BINDINGS_RESET_PDC_SDM_845_H
-
-#define PDC_APPS_SYNC_RESET 0
-#define PDC_SP_SYNC_RESET 1
-#define PDC_AUDIO_SYNC_RESET 2
-#define PDC_SENSORS_SYNC_RESET 3
-#define PDC_AOP_SYNC_RESET 4
-#define PDC_DEBUG_SYNC_RESET 5
-#define PDC_GPU_SYNC_RESET 6
-#define PDC_DISPLAY_SYNC_RESET 7
-#define PDC_COMPUTE_SYNC_RESET 8
-#define PDC_MODEM_SYNC_RESET 9
-#define PDC_WLAN_RF_SYNC_RESET 10
-#define PDC_WPSS_SYNC_RESET 11
-
-#endif
diff --git a/include/dt-bindings/soc/qcom,apr.h b/include/dt-bindings/soc/qcom,apr.h
deleted file mode 100644
index 0063624..0000000
--- a/include/dt-bindings/soc/qcom,apr.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_BINDINGS_QCOM_APR_H
-#define __DT_BINDINGS_QCOM_APR_H
-
-/* Domain IDs */
-#define APR_DOMAIN_SIM 0x1
-#define APR_DOMAIN_PC 0x2
-#define APR_DOMAIN_MODEM 0x3
-#define APR_DOMAIN_ADSP 0x4
-#define APR_DOMAIN_APPS 0x5
-#define APR_DOMAIN_MAX 0x6
-
-/* ADSP service IDs */
-#define APR_SVC_ADSP_CORE 0x3
-#define APR_SVC_AFE 0x4
-#define APR_SVC_VSM 0x5
-#define APR_SVC_VPM 0x6
-#define APR_SVC_ASM 0x7
-#define APR_SVC_ADM 0x8
-#define APR_SVC_ADSP_MVM 0x09
-#define APR_SVC_ADSP_CVS 0x0A
-#define APR_SVC_ADSP_CVP 0x0B
-#define APR_SVC_USM 0x0C
-#define APR_SVC_LSM 0x0D
-#define APR_SVC_VIDC 0x16
-#define APR_SVC_MAX 0x17
-
-#endif /* __DT_BINDINGS_QCOM_APR_H */
diff --git a/include/dt-bindings/soc/qcom,rpmh-rsc.h b/include/dt-bindings/soc/qcom,rpmh-rsc.h
deleted file mode 100644
index 868f998..0000000
--- a/include/dt-bindings/soc/qcom,rpmh-rsc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DT_QCOM_RPMH_RSC_H__
-#define __DT_QCOM_RPMH_RSC_H__
-
-#define SLEEP_TCS 0
-#define WAKE_TCS 1
-#define ACTIVE_TCS 2
-#define CONTROL_TCS 3
-
-#endif /* __DT_QCOM_RPMH_RSC_H__ */
diff --git a/include/dt-bindings/sound/qcom,lpass.h b/include/dt-bindings/sound/qcom,lpass.h
deleted file mode 100644
index a9404c3..0000000
--- a/include/dt-bindings/sound/qcom,lpass.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_QCOM_LPASS_H
-#define __DT_QCOM_LPASS_H
-
-#define MI2S_PRIMARY 0
-#define MI2S_SECONDARY 1
-#define MI2S_TERTIARY 2
-#define MI2S_QUATERNARY 3
-#define MI2S_QUINARY 4
-
-#define LPASS_DP_RX 5
-
-#define LPASS_CDC_DMA_RX0 6
-#define LPASS_CDC_DMA_RX1 7
-#define LPASS_CDC_DMA_RX2 8
-#define LPASS_CDC_DMA_RX3 9
-#define LPASS_CDC_DMA_RX4 10
-#define LPASS_CDC_DMA_RX5 11
-#define LPASS_CDC_DMA_RX6 12
-#define LPASS_CDC_DMA_RX7 13
-#define LPASS_CDC_DMA_RX8 14
-#define LPASS_CDC_DMA_RX9 15
-
-#define LPASS_CDC_DMA_TX0 16
-#define LPASS_CDC_DMA_TX1 17
-#define LPASS_CDC_DMA_TX2 18
-#define LPASS_CDC_DMA_TX3 19
-#define LPASS_CDC_DMA_TX4 20
-#define LPASS_CDC_DMA_TX5 21
-#define LPASS_CDC_DMA_TX6 22
-#define LPASS_CDC_DMA_TX7 23
-#define LPASS_CDC_DMA_TX8 24
-
-#define LPASS_CDC_DMA_VA_TX0 25
-#define LPASS_CDC_DMA_VA_TX1 26
-#define LPASS_CDC_DMA_VA_TX2 27
-#define LPASS_CDC_DMA_VA_TX3 28
-#define LPASS_CDC_DMA_VA_TX4 29
-#define LPASS_CDC_DMA_VA_TX5 30
-#define LPASS_CDC_DMA_VA_TX6 31
-#define LPASS_CDC_DMA_VA_TX7 32
-#define LPASS_CDC_DMA_VA_TX8 33
-
-#define LPASS_MCLK0 0
-
-#endif /* __DT_QCOM_LPASS_H */
diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h
deleted file mode 100644
index 9d5d89c..0000000
--- a/include/dt-bindings/sound/qcom,q6afe.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_BINDINGS_Q6_AFE_H__
-#define __DT_BINDINGS_Q6_AFE_H__
-
-/* This file exists due to backward compatibility reasons, Please do not DELETE! */
-
-#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
-
-#endif /* __DT_BINDINGS_Q6_AFE_H__ */
diff --git a/include/dt-bindings/sound/qcom,q6asm.h b/include/dt-bindings/sound/qcom,q6asm.h
deleted file mode 100644
index f59d74f..0000000
--- a/include/dt-bindings/sound/qcom,q6asm.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_BINDINGS_Q6_ASM_H__
-#define __DT_BINDINGS_Q6_ASM_H__
-
-#define MSM_FRONTEND_DAI_MULTIMEDIA1 0
-#define MSM_FRONTEND_DAI_MULTIMEDIA2 1
-#define MSM_FRONTEND_DAI_MULTIMEDIA3 2
-#define MSM_FRONTEND_DAI_MULTIMEDIA4 3
-#define MSM_FRONTEND_DAI_MULTIMEDIA5 4
-#define MSM_FRONTEND_DAI_MULTIMEDIA6 5
-#define MSM_FRONTEND_DAI_MULTIMEDIA7 6
-#define MSM_FRONTEND_DAI_MULTIMEDIA8 7
-#define MSM_FRONTEND_DAI_MULTIMEDIA9 8
-#define MSM_FRONTEND_DAI_MULTIMEDIA10 9
-#define MSM_FRONTEND_DAI_MULTIMEDIA11 10
-#define MSM_FRONTEND_DAI_MULTIMEDIA12 11
-#define MSM_FRONTEND_DAI_MULTIMEDIA13 12
-#define MSM_FRONTEND_DAI_MULTIMEDIA14 13
-#define MSM_FRONTEND_DAI_MULTIMEDIA15 14
-#define MSM_FRONTEND_DAI_MULTIMEDIA16 15
-
-#define Q6ASM_DAI_TX_RX 0
-#define Q6ASM_DAI_TX 1
-#define Q6ASM_DAI_RX 2
-
-#endif /* __DT_BINDINGS_Q6_ASM_H__ */
diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
deleted file mode 100644
index 39f2032..0000000
--- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__
-#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__
-
-/* LPASS Audio virtual ports IDs */
-#define HDMI_RX 1
-#define SLIMBUS_0_RX 2
-#define SLIMBUS_0_TX 3
-#define SLIMBUS_1_RX 4
-#define SLIMBUS_1_TX 5
-#define SLIMBUS_2_RX 6
-#define SLIMBUS_2_TX 7
-#define SLIMBUS_3_RX 8
-#define SLIMBUS_3_TX 9
-#define SLIMBUS_4_RX 10
-#define SLIMBUS_4_TX 11
-#define SLIMBUS_5_RX 12
-#define SLIMBUS_5_TX 13
-#define SLIMBUS_6_RX 14
-#define SLIMBUS_6_TX 15
-#define PRIMARY_MI2S_RX 16
-#define PRIMARY_MI2S_TX 17
-#define SECONDARY_MI2S_RX 18
-#define SECONDARY_MI2S_TX 19
-#define TERTIARY_MI2S_RX 20
-#define TERTIARY_MI2S_TX 21
-#define QUATERNARY_MI2S_RX 22
-#define QUATERNARY_MI2S_TX 23
-#define PRIMARY_TDM_RX_0 24
-#define PRIMARY_TDM_TX_0 25
-#define PRIMARY_TDM_RX_1 26
-#define PRIMARY_TDM_TX_1 27
-#define PRIMARY_TDM_RX_2 28
-#define PRIMARY_TDM_TX_2 29
-#define PRIMARY_TDM_RX_3 30
-#define PRIMARY_TDM_TX_3 31
-#define PRIMARY_TDM_RX_4 32
-#define PRIMARY_TDM_TX_4 33
-#define PRIMARY_TDM_RX_5 34
-#define PRIMARY_TDM_TX_5 35
-#define PRIMARY_TDM_RX_6 36
-#define PRIMARY_TDM_TX_6 37
-#define PRIMARY_TDM_RX_7 38
-#define PRIMARY_TDM_TX_7 39
-#define SECONDARY_TDM_RX_0 40
-#define SECONDARY_TDM_TX_0 41
-#define SECONDARY_TDM_RX_1 42
-#define SECONDARY_TDM_TX_1 43
-#define SECONDARY_TDM_RX_2 44
-#define SECONDARY_TDM_TX_2 45
-#define SECONDARY_TDM_RX_3 46
-#define SECONDARY_TDM_TX_3 47
-#define SECONDARY_TDM_RX_4 48
-#define SECONDARY_TDM_TX_4 49
-#define SECONDARY_TDM_RX_5 50
-#define SECONDARY_TDM_TX_5 51
-#define SECONDARY_TDM_RX_6 52
-#define SECONDARY_TDM_TX_6 53
-#define SECONDARY_TDM_RX_7 54
-#define SECONDARY_TDM_TX_7 55
-#define TERTIARY_TDM_RX_0 56
-#define TERTIARY_TDM_TX_0 57
-#define TERTIARY_TDM_RX_1 58
-#define TERTIARY_TDM_TX_1 59
-#define TERTIARY_TDM_RX_2 60
-#define TERTIARY_TDM_TX_2 61
-#define TERTIARY_TDM_RX_3 62
-#define TERTIARY_TDM_TX_3 63
-#define TERTIARY_TDM_RX_4 64
-#define TERTIARY_TDM_TX_4 65
-#define TERTIARY_TDM_RX_5 66
-#define TERTIARY_TDM_TX_5 67
-#define TERTIARY_TDM_RX_6 68
-#define TERTIARY_TDM_TX_6 69
-#define TERTIARY_TDM_RX_7 70
-#define TERTIARY_TDM_TX_7 71
-#define QUATERNARY_TDM_RX_0 72
-#define QUATERNARY_TDM_TX_0 73
-#define QUATERNARY_TDM_RX_1 74
-#define QUATERNARY_TDM_TX_1 75
-#define QUATERNARY_TDM_RX_2 76
-#define QUATERNARY_TDM_TX_2 77
-#define QUATERNARY_TDM_RX_3 78
-#define QUATERNARY_TDM_TX_3 79
-#define QUATERNARY_TDM_RX_4 80
-#define QUATERNARY_TDM_TX_4 81
-#define QUATERNARY_TDM_RX_5 82
-#define QUATERNARY_TDM_TX_5 83
-#define QUATERNARY_TDM_RX_6 84
-#define QUATERNARY_TDM_TX_6 85
-#define QUATERNARY_TDM_RX_7 86
-#define QUATERNARY_TDM_TX_7 87
-#define QUINARY_TDM_RX_0 88
-#define QUINARY_TDM_TX_0 89
-#define QUINARY_TDM_RX_1 90
-#define QUINARY_TDM_TX_1 91
-#define QUINARY_TDM_RX_2 92
-#define QUINARY_TDM_TX_2 93
-#define QUINARY_TDM_RX_3 94
-#define QUINARY_TDM_TX_3 95
-#define QUINARY_TDM_RX_4 96
-#define QUINARY_TDM_TX_4 97
-#define QUINARY_TDM_RX_5 98
-#define QUINARY_TDM_TX_5 99
-#define QUINARY_TDM_RX_6 100
-#define QUINARY_TDM_TX_6 101
-#define QUINARY_TDM_RX_7 102
-#define QUINARY_TDM_TX_7 103
-#define DISPLAY_PORT_RX 104
-#define WSA_CODEC_DMA_RX_0 105
-#define WSA_CODEC_DMA_TX_0 106
-#define WSA_CODEC_DMA_RX_1 107
-#define WSA_CODEC_DMA_TX_1 108
-#define WSA_CODEC_DMA_TX_2 109
-#define VA_CODEC_DMA_TX_0 110
-#define VA_CODEC_DMA_TX_1 111
-#define VA_CODEC_DMA_TX_2 112
-#define RX_CODEC_DMA_RX_0 113
-#define TX_CODEC_DMA_TX_0 114
-#define RX_CODEC_DMA_RX_1 115
-#define TX_CODEC_DMA_TX_1 116
-#define RX_CODEC_DMA_RX_2 117
-#define TX_CODEC_DMA_TX_2 118
-#define RX_CODEC_DMA_RX_3 119
-#define TX_CODEC_DMA_TX_3 120
-#define RX_CODEC_DMA_RX_4 121
-#define TX_CODEC_DMA_TX_4 122
-#define RX_CODEC_DMA_RX_5 123
-#define TX_CODEC_DMA_TX_5 124
-#define RX_CODEC_DMA_RX_6 125
-#define RX_CODEC_DMA_RX_7 126
-#define QUINARY_MI2S_RX 127
-#define QUINARY_MI2S_TX 128
-#define DISPLAY_PORT_RX_0 DISPLAY_PORT_RX
-#define DISPLAY_PORT_RX_1 129
-#define DISPLAY_PORT_RX_2 130
-#define DISPLAY_PORT_RX_3 131
-#define DISPLAY_PORT_RX_4 132
-#define DISPLAY_PORT_RX_5 133
-#define DISPLAY_PORT_RX_6 134
-#define DISPLAY_PORT_RX_7 135
-
-#define LPASS_CLK_ID_PRI_MI2S_IBIT 1
-#define LPASS_CLK_ID_PRI_MI2S_EBIT 2
-#define LPASS_CLK_ID_SEC_MI2S_IBIT 3
-#define LPASS_CLK_ID_SEC_MI2S_EBIT 4
-#define LPASS_CLK_ID_TER_MI2S_IBIT 5
-#define LPASS_CLK_ID_TER_MI2S_EBIT 6
-#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7
-#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8
-#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9
-#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10
-#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11
-#define LPASS_CLK_ID_QUI_MI2S_IBIT 12
-#define LPASS_CLK_ID_QUI_MI2S_EBIT 13
-#define LPASS_CLK_ID_SEN_MI2S_IBIT 14
-#define LPASS_CLK_ID_SEN_MI2S_EBIT 15
-#define LPASS_CLK_ID_INT0_MI2S_IBIT 16
-#define LPASS_CLK_ID_INT1_MI2S_IBIT 17
-#define LPASS_CLK_ID_INT2_MI2S_IBIT 18
-#define LPASS_CLK_ID_INT3_MI2S_IBIT 19
-#define LPASS_CLK_ID_INT4_MI2S_IBIT 20
-#define LPASS_CLK_ID_INT5_MI2S_IBIT 21
-#define LPASS_CLK_ID_INT6_MI2S_IBIT 22
-#define LPASS_CLK_ID_QUI_MI2S_OSR 23
-#define LPASS_CLK_ID_PRI_PCM_IBIT 24
-#define LPASS_CLK_ID_PRI_PCM_EBIT 25
-#define LPASS_CLK_ID_SEC_PCM_IBIT 26
-#define LPASS_CLK_ID_SEC_PCM_EBIT 27
-#define LPASS_CLK_ID_TER_PCM_IBIT 28
-#define LPASS_CLK_ID_TER_PCM_EBIT 29
-#define LPASS_CLK_ID_QUAD_PCM_IBIT 30
-#define LPASS_CLK_ID_QUAD_PCM_EBIT 31
-#define LPASS_CLK_ID_QUIN_PCM_IBIT 32
-#define LPASS_CLK_ID_QUIN_PCM_EBIT 33
-#define LPASS_CLK_ID_QUI_PCM_OSR 34
-#define LPASS_CLK_ID_PRI_TDM_IBIT 35
-#define LPASS_CLK_ID_PRI_TDM_EBIT 36
-#define LPASS_CLK_ID_SEC_TDM_IBIT 37
-#define LPASS_CLK_ID_SEC_TDM_EBIT 38
-#define LPASS_CLK_ID_TER_TDM_IBIT 39
-#define LPASS_CLK_ID_TER_TDM_EBIT 40
-#define LPASS_CLK_ID_QUAD_TDM_IBIT 41
-#define LPASS_CLK_ID_QUAD_TDM_EBIT 42
-#define LPASS_CLK_ID_QUIN_TDM_IBIT 43
-#define LPASS_CLK_ID_QUIN_TDM_EBIT 44
-#define LPASS_CLK_ID_QUIN_TDM_OSR 45
-#define LPASS_CLK_ID_MCLK_1 46
-#define LPASS_CLK_ID_MCLK_2 47
-#define LPASS_CLK_ID_MCLK_3 48
-#define LPASS_CLK_ID_MCLK_4 49
-#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50
-#define LPASS_CLK_ID_INT_MCLK_0 51
-#define LPASS_CLK_ID_INT_MCLK_1 52
-#define LPASS_CLK_ID_MCLK_5 53
-#define LPASS_CLK_ID_WSA_CORE_MCLK 54
-#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55
-#define LPASS_CLK_ID_VA_CORE_MCLK 56
-#define LPASS_CLK_ID_TX_CORE_MCLK 57
-#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58
-#define LPASS_CLK_ID_RX_CORE_MCLK 59
-#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60
-#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61
-/* Clock ID for MCLK for WSA2 core */
-#define LPASS_CLK_ID_WSA2_CORE_MCLK 62
-/* Clock ID for NPL MCLK for WSA2 core */
-#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK 63
-/* Clock ID for RX Core TX MCLK */
-#define LPASS_CLK_ID_RX_CORE_TX_MCLK 64
-/* Clock ID for RX CORE TX 2X MCLK */
-#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 65
-/* Clock ID for WSA core TX MCLK */
-#define LPASS_CLK_ID_WSA_CORE_TX_MCLK 66
-/* Clock ID for WSA core TX 2X MCLK */
-#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 67
-/* Clock ID for WSA2 core TX MCLK */
-#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK 68
-/* Clock ID for WSA2 core TX 2X MCLK */
-#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 69
-/* Clock ID for RX CORE MCLK2 2X MCLK */
-#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 70
-
-#define LPASS_HW_AVTIMER_VOTE 101
-#define LPASS_HW_MACRO_VOTE 102
-#define LPASS_HW_DCODEC_VOTE 103
-
-#define Q6AFE_MAX_CLK_ID 104
-
-#define LPASS_CLK_ATTRIBUTE_INVALID 0x0
-#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
-#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
-#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
-
-#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */
diff --git a/include/dt-bindings/sound/qcom,wcd9335.h b/include/dt-bindings/sound/qcom,wcd9335.h
deleted file mode 100644
index f5e9f1d..0000000
--- a/include/dt-bindings/sound/qcom,wcd9335.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-
-#ifndef __DT_SOUND_QCOM_WCD9335_H
-#define __DT_SOUND_QCOM_WCD9335_H
-
-#define AIF1_PB 0
-#define AIF1_CAP 1
-#define AIF2_PB 2
-#define AIF2_CAP 3
-#define AIF3_PB 4
-#define AIF3_CAP 5
-#define AIF4_PB 6
-#define NUM_CODEC_DAIS 7
-
-#endif
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 6751fb5..3ffcd40 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -339,7 +339,7 @@
dev_set_ofnode(mtd->dev, node);
}
-static inline const ofnode mtd_get_ofnode(struct mtd_info *mtd)
+static inline ofnode mtd_get_ofnode(struct mtd_info *mtd)
{
return dev_ofnode(mtd->dev);
}
diff --git a/include/memtop.h b/include/memtop.h
new file mode 100644
index 0000000..28f62e2
--- /dev/null
+++ b/include/memtop.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+/**
+ * get_mem_top() - Compute the value of ram_top
+ * @ram_start: Start of RAM
+ * @ram_size: RAM size
+ * @size: Minimum RAM size requested
+ * @fdt: FDT blob
+ *
+ * The function computes the top address of RAM memory that can be
+ * used by U-Boot. This is being done by going through the list of
+ * reserved memory regions specified in the devicetree blob passed
+ * to the function. The logic used here is derived from the lmb
+ * allocation function.
+ *
+ * Return: address of ram top on success, 0 on failure
+ */
+phys_addr_t get_mem_top(phys_addr_t ram_start, phys_size_t ram_size,
+ phys_size_t size, void *fdt);
diff --git a/include/part.h b/include/part.h
index 9266267..fcb3c13 100644
--- a/include/part.h
+++ b/include/part.h
@@ -74,6 +74,7 @@
* PART_EFI_SYSTEM_PARTITION the partition is an EFI system partition
*/
int bootable;
+ u16 type_flags; /* top 16 bits of GPT partition attributes */
#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
char uuid[UUID_STR_LEN + 1]; /* filesystem UUID as string, if exists */
#endif
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 58d4978..d93f28b 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -481,7 +481,6 @@
menu "Misc options"
config EFI_LOADER_BOUNCE_BUFFER
bool "EFI Applications use bounce buffers for DMA operations"
- depends on ARM64
help
Some hardware does not support DMA to full 64bit addresses. For this
hardware we can create a bounce buffer so that payloads don't have to
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 4f52284..080e7f7 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -2234,7 +2234,7 @@
if (IS_ENABLED(CONFIG_USB_DEVICE))
udc_disconnect();
board_quiesce_devices();
- dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+ dm_remove_devices_active();
}
/* Patch out unsupported runtime function */
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index d2f5d56..e493934 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -451,7 +451,7 @@
enum efi_memory_type memory_type,
efi_uintn_t pages, uint64_t *memory)
{
- u64 len;
+ u64 efi_addr, len;
uint flags;
efi_status_t ret;
phys_addr_t addr;
@@ -499,14 +499,17 @@
return EFI_INVALID_PARAMETER;
}
- addr = (u64)(uintptr_t)map_sysmem(addr, 0);
+ efi_addr = (u64)(uintptr_t)map_sysmem(addr, 0);
/* Reserve that map in our memory maps */
- ret = efi_add_memory_map_pg(addr, pages, memory_type, true);
- if (ret != EFI_SUCCESS)
+ ret = efi_add_memory_map_pg(efi_addr, pages, memory_type, true);
+ if (ret != EFI_SUCCESS) {
/* Map would overlap, bail out */
+ lmb_free_flags(addr, (u64)pages << EFI_PAGE_SHIFT, flags);
+ unmap_sysmem((void *)(uintptr_t)efi_addr);
return EFI_OUT_OF_RESOURCES;
+ }
- *memory = addr;
+ *memory = efi_addr;
return EFI_SUCCESS;
}
@@ -546,6 +549,8 @@
if (status)
return EFI_NOT_FOUND;
+ unmap_sysmem((void *)(uintptr_t)memory);
+
return ret;
}
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index 866a529..572c6b5 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -607,12 +607,9 @@
* Format"
*/
if (flags & PE_COFF_IMAGE) {
- IMAGE_NT_HEADERS32 *nt;
-
ret = efi_check_pe((void *)(uintptr_t)data_to_hash,
- data_to_hash_len, (void **)&nt);
+ data_to_hash_len, NULL);
if (ret != EFI_SUCCESS) {
- log_err("Not a valid PE-COFF file\n");
ret = EFI_UNSUPPORTED;
goto out;
}
diff --git a/net/lwip/Kconfig b/net/lwip/Kconfig
index a9ae9bf..40345ce 100644
--- a/net/lwip/Kconfig
+++ b/net/lwip/Kconfig
@@ -6,9 +6,16 @@
config LWIP_DEBUG
bool "Enable debug traces in the lwIP library"
+ help
+ Prints messages to the console regarding network packets that go in
+ and out of the lwIP library.
config LWIP_ASSERT
bool "Enable assertions in the lwIP library"
+ help
+ Compiles additional error checking code into the lwIP library. These
+ checks are related to conditions that should not happen in typical
+ use, but may be helpful to debug new features.
config PROT_DHCP_LWIP
bool
diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c
index 23b5622..9b882cf 100644
--- a/net/lwip/dhcp.c
+++ b/net/lwip/dhcp.c
@@ -27,9 +27,9 @@
static int dhcp_loop(struct udevice *udev)
{
- char *ipstr = "ipaddr\0\0";
- char *maskstr = "netmask\0\0";
- char *gwstr = "gatewayip\0\0";
+ char ipstr[] = "ipaddr\0\0";
+ char maskstr[] = "netmask\0\0";
+ char gwstr[] = "gatewayip\0\0";
unsigned long start;
struct netif *netif;
struct dhcp *dhcp;
@@ -111,9 +111,21 @@
int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
+ int ret;
+
eth_set_current();
+ ret = dhcp_loop(eth_get_dev());
+ if (ret)
+ return ret;
+
+ if (argc > 1) {
+ struct cmd_tbl cmdtp = {};
+
- return dhcp_loop(eth_get_dev());
+ return do_tftpb(&cmdtp, 0, argc, argv);
+ }
+
+ return CMD_RET_SUCCESS;
}
int dhcp_run(ulong addr, const char *fname, bool autoload)
diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c
index 4702177..b863047 100644
--- a/net/lwip/net-lwip.c
+++ b/net/lwip/net-lwip.c
@@ -91,9 +91,9 @@
static int get_udev_ipv4_info(struct udevice *dev, ip4_addr_t *ip,
ip4_addr_t *mask, ip4_addr_t *gw)
{
- char *ipstr = "ipaddr\0\0";
- char *maskstr = "netmask\0\0";
- char *gwstr = "gatewayip\0\0";
+ char ipstr[] = "ipaddr\0\0";
+ char maskstr[] = "netmask\0\0";
+ char gwstr[] = "gatewayip\0\0";
int idx = dev_seq(dev);
char *env;
diff --git a/net/lwip/wget.c b/net/lwip/wget.c
index 26086ed..062aa7c 100644
--- a/net/lwip/wget.c
+++ b/net/lwip/wget.c
@@ -15,7 +15,7 @@
#include <time.h>
#include <dm/uclass.h>
-#define SERVER_NAME_SIZE 200
+#define SERVER_NAME_SIZE 254
#define HTTP_PORT_DEFAULT 80
#define HTTPS_PORT_DEFAULT 443
#define PROGRESS_PRINT_STEP_BYTES (100 * 1024)
@@ -42,7 +42,6 @@
size_t *olen)
{
struct udevice *dev;
- u64 rng = 0;
int ret;
*olen = 0;
@@ -52,12 +51,11 @@
log_err("Failed to get an rng: %d\n", ret);
return ret;
}
- ret = dm_rng_read(dev, &rng, sizeof(rng));
+ ret = dm_rng_read(dev, output, len);
if (ret)
return ret;
- memcpy(output, &rng, len);
- *olen = sizeof(rng);
+ *olen = len;
return 0;
}
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index 9397328..da713d8 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -1197,7 +1197,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cros, UTF_CONSOLE);
+BOOTSTD_TEST(bootflow_cros, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT);
/* Test Android bootmeth */
static int bootflow_android(struct unit_test_state *uts)
@@ -1220,7 +1220,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_android, UTF_CONSOLE);
+BOOTSTD_TEST(bootflow_android, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT);
/* Test EFI bootmeth */
static int bootflow_efi(struct unit_test_state *uts)
diff --git a/test/cmd/hash.c b/test/cmd/hash.c
index 2fcec9c..296dd76 100644
--- a/test/cmd/hash.c
+++ b/test/cmd/hash.c
@@ -33,11 +33,13 @@
strstr(uts->actual_str, "md5 for "));
ut_assert(strstr(uts->actual_str,
"d41d8cd98f00b204e9800998ecf8427e"));
- ut_check_console_line(uts, "d41d8cd98f00b204e9800998ecf8427e");
+ ut_assertok(ut_check_console_line(uts,
+ "d41d8cd98f00b204e9800998ecf8427e"));
if (!CONFIG_IS_ENABLED(HASH_VERIFY)) {
ut_assert(run_command("hash -v sha256 $loadaddr 0 foo", 0));
- ut_check_console_line(uts, "hash - compute hash message digest");
+ ut_assertok(ut_check_console_line(
+ uts, "hash - compute hash message digest"));
return 0;
}
@@ -77,12 +79,13 @@
strstr(uts->actual_str, "sha256 for "));
ut_assert(strstr(uts->actual_str,
"e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855"));
- ut_check_console_line(uts,
- "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855");
+ ut_assertok(ut_check_console_line(
+ uts, "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855"));
if (!CONFIG_IS_ENABLED(HASH_VERIFY)) {
ut_assert(run_command("hash -v sha256 $loadaddr 0 foo", 0));
- ut_check_console_line(uts, "hash - compute hash message digest");
+ ut_assertok(ut_check_console_line(
+ uts, "hash - compute hash message digest"));
return 0;
}
diff --git a/test/dm/core.c b/test/dm/core.c
index 7371d3f..c59ffc6 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -999,6 +999,56 @@
}
DM_TEST(dm_test_remove_vital, 0);
+/* Test removal of 'active' devices */
+static int dm_test_remove_active(struct unit_test_state *uts)
+{
+ struct udevice *normal, *dma, *vital, *dma_vital;
+
+ /* Skip the behaviour in test_post_probe() */
+ uts->skip_post_probe = 1;
+
+ ut_assertok(device_bind_by_name(uts->root, false, &driver_info_manual,
+ &normal));
+ ut_assertnonnull(normal);
+
+ ut_assertok(device_bind_by_name(uts->root, false, &driver_info_act_dma,
+ &dma));
+ ut_assertnonnull(dma);
+
+ ut_assertok(device_bind_by_name(uts->root, false,
+ &driver_info_vital_clk, &vital));
+ ut_assertnonnull(vital);
+
+ ut_assertok(device_bind_by_name(uts->root, false,
+ &driver_info_act_dma_vital_clk,
+ &dma_vital));
+ ut_assertnonnull(dma_vital);
+
+ /* Probe the devices */
+ ut_assertok(device_probe(normal));
+ ut_assertok(device_probe(dma));
+ ut_assertok(device_probe(vital));
+ ut_assertok(device_probe(dma_vital));
+
+ /* Check that devices are active right now */
+ ut_asserteq(true, device_active(normal));
+ ut_asserteq(true, device_active(dma));
+ ut_asserteq(true, device_active(vital));
+ ut_asserteq(true, device_active(dma_vital));
+
+ /* Remove active devices in an ordered way */
+ dm_remove_devices_active();
+
+ /* Check that all devices are inactive right now */
+ ut_asserteq(true, device_active(normal));
+ ut_asserteq(false, device_active(dma));
+ ut_asserteq(true, device_active(vital));
+ ut_asserteq(false, device_active(dma_vital));
+
+ return 0;
+}
+DM_TEST(dm_test_remove_active, 0);
+
static int dm_test_uclass_before_ready(struct unit_test_state *uts)
{
struct uclass *uc;
diff --git a/test/lib/str.c b/test/lib/str.c
index 3cc9dfe..e620453 100644
--- a/test/lib/str.c
+++ b/test/lib/str.c
@@ -18,6 +18,8 @@
static const char str5[] = "0x9876543210the last time I was deloused";
static const char str6[] = "0778octal is seldom used";
static const char str7[] = "707it is a piece of computing history";
+static const char str8[] = "0x887e2561352d80fa";
+static const char str9[] = "614FF7EAA63009DA";
static int str_upper(struct unit_test_state *uts)
{
@@ -186,6 +188,22 @@
}
LIB_TEST(str_hextoul, 0);
+static int str_hextoull(struct unit_test_state *uts)
+{
+ char *endp;
+
+ /* Just a simple test, since we know this uses simple_strtoull() */
+ ut_asserteq_64(0x887e2561352d80faULL, hextoull(str8, &endp));
+ ut_asserteq_64(0x12, endp - str8);
+ ut_asserteq_64(0x614ff7eaa63009daULL, hextoull(str9, &endp));
+ ut_asserteq_64(0x10, endp - str9);
+ ut_asserteq_64(0x887e2561352d80faULL, hextoull(str8, NULL));
+ ut_asserteq_64(0x614ff7eaa63009daULL, hextoull(str9, NULL));
+
+ return 0;
+}
+LIB_TEST(str_hextoull, 0);
+
static int str_dectoul(struct unit_test_state *uts)
{
char *endp;
diff --git a/test/lib/time.c b/test/lib/time.c
index b99e738..2095bef 100644
--- a/test/lib/time.c
+++ b/test/lib/time.c
@@ -22,7 +22,11 @@
next = get_timer(0);
} while (start == next);
- ut_asserteq(start + 1, next);
+ if (start + 1 != next) {
+ printf("%s: iter=%d, start=%lu, next=%lu, expected a difference of 1\n",
+ __func__, iter, start, next);
+ return -EINVAL;
+ }
start++;
}
@@ -31,7 +35,11 @@
* an extra millisecond may have passed.
*/
diff = get_timer(base);
- ut_assert(diff == iter || diff == iter + 1);
+ if (diff != iter && diff != iter + 1) {
+ printf("%s: expected get_timer(base) to match elapsed time: diff=%lu, expected=%d\n",
+ __func__, diff, iter);
+ return -EINVAL;
+ }
return 0;
}
@@ -49,8 +57,11 @@
next = timer_get_us();
if (next != prev) {
delta = next - prev;
- ut_assert(delta >= 0);
- if (delta) {
+ if (delta < 0) {
+ printf("%s: timer_get_us() went backwards from %lu to %lu\n",
+ __func__, prev, next);
+ return -EINVAL;
+ } else if (delta != 0) {
if (delta < min)
min = delta;
prev = next;
@@ -59,7 +70,11 @@
}
}
- ut_asserteq(1, min);
+ if (min != 1) {
+ printf("%s: Minimum microsecond delta should be 1 but is %lu\n",
+ __func__, min);
+ return -EINVAL;
+ }
return 0;
}
@@ -80,7 +95,8 @@
error = delta_us - 1000000;
printf("%s: Microsecond time for 1 second: %lu, error = %ld\n",
__func__, delta_us, error);
- ut_assert(abs(error) <= 1000);
+ if (abs(error) > 1000)
+ return -EINVAL;
return 0;
}
@@ -99,7 +115,8 @@
error = delta - 1000;
printf("%s: Delay time for 1000 udelay(1000): %lu ms, error = %ld\n",
__func__, delta, error);
- ut_assert(abs(error) <= 100);
+ if (abs(error) > 100)
+ return -EINVAL;
return 0;
}