Coding Style cleanup
diff --git a/board/RPXlite_dw/README b/board/RPXlite_dw/README
index 4551718..e88f9aa 100644
--- a/board/RPXlite_dw/README
+++ b/board/RPXlite_dw/README
@@ -38,7 +38,7 @@
To support the Platform better,I added LCD panel(NL6448BC20-08) function.
For the convenience of debug, CONFIG_PERBOOT was supported. So you just
perss ENTER if you want to get a serial console in boot downcounting.
-Then you can switch to LCD and serial console freely just typing
+Then you can switch to LCD and serial console freely just typing
'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled.
To get a LCD support u-boot,you can do the following:
@@ -93,18 +93,18 @@
like[include/configs/RPXlite.h] :
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
- "bootm"
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "bootm"
-This is enough for kernel NFS test. But as debug process goes on, you would expect
+This is enough for kernel NFS test. But as debug process goes on, you would expect
to save some time on environment variable setting and u-boot/kernel updating.
So the default environment variable setting would become more complicated. Just like
the one I did in include/configs/RPXlite_DW.h.
Two u-boot commands, ku and uu, should be careful to use. They were designed to update
-kernel and u-boot image file respectively. You must tftp your image to default address
+kernel and u-boot image file respectively. You must tftp your image to default address
'100000' and then use them correctly. Yeah, you can create your own command to do this
job. :-) The example u-boot image updating process could be :
diff --git a/board/omap2420h4/config.mk b/board/omap2420h4/config.mk
index 1c770f3..4f14be8 100644
--- a/board/omap2420h4/config.mk
+++ b/board/omap2420h4/config.mk
@@ -20,7 +20,6 @@
# Used with full SRAM boot.
# This is either with a GP system or a signed boot image.
# easiest, and safest way to go if you can.
-# Comment out //CONFIG_PARTIAL_SRAM for this one.
+# Comment out CONFIG_PARTIAL_SRAM for this one.
#
#TEXT_BASE = 0x40280000
-
diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c
index a3b3453..5e23d61 100644
--- a/board/omap2420h4/mem.c
+++ b/board/omap2420h4/mem.c
@@ -284,10 +284,10 @@
__raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
sdelay(1000);
__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
- //__raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
+ /* __raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); */
__raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
__raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
- //__raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
+ /* __raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); */
__raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
sdelay(2000);
@@ -303,4 +303,3 @@
__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
sdelay(2000);
}
-
diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c
index 4696a71..bf398f6 100644
--- a/board/omap2420h4/omap2420h4.c
+++ b/board/omap2420h4/omap2420h4.c
@@ -333,11 +333,11 @@
/* I2C1 Clock pin configuration, PIN = M19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* I2C1 Data pin configuration, PIN = L15 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* Pull-up required on data line */
/* external pull-up already present. */
@@ -379,91 +379,91 @@
/* LCD_D0 pin configuration, PIN = Y7 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D1 pin configuration, PIN = P10 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D2 pin configuration, PIN = V8 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D3 pin configuration, PIN = Y8 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D4 pin configuration, PIN = W8 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D5 pin configuration, PIN = R10 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D6 pin configuration, PIN = Y9 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D7 pin configuration, PIN = V9 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D8 pin configuration, PIN = W9 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D9 pin configuration, PIN = P11 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D10 pin configuration, PIN = V10 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D11 pin configuration, PIN = Y10 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D12 pin configuration, PIN = W10 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D13 pin configuration, PIN = R11 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D14 pin configuration, PIN = V11 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D15 pin configuration, PIN = W11 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D16 pin configuration, PIN = P12 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D17 pin configuration, PIN = R12 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_PCLK pin configuration, PIN = W6 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_VSYNC pin configuration, PIN = V7 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_HSYNC pin configuration, PIN = Y6 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_ACBIAS pin configuration, PIN = W7 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
}
/****************************************
@@ -477,63 +477,63 @@
/* CAMERA_RSTZ pin configuration, PIN = Y16 */
/* CAM_RST is connected through the I2C IO expander.*/
/* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
- /* *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled */
+ /* *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_XCLK pin configuration, PIN = U3 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_LCLK pin configuration, PIN = V5 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_VSYNC pin configuration, PIN = U2 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_HSYNC pin configuration, PIN = T3 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT0 pin configuration, PIN = T4 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT1 pin configuration, PIN = V2 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT2 pin configuration, PIN = V3 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT3 pin configuration, PIN = U4 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT4 pin configuration, PIN = W2 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT5 pin configuration, PIN = V4 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT6 pin configuration, PIN = W3 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT7 pin configuration, PIN = Y2 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT8 pin configuration, PIN = Y4 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT9 pin configuration, PIN = V6 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
}
/****************************************
@@ -546,70 +546,70 @@
/* SDMMC_CLKI pin configuration, PIN = H15 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_CLKO pin configuration, PIN = G19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_CMD pin configuration, PIN = H18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
- // External pull-ups are present.
- // *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+ /* External pull-ups are present. */
+ /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
/* SDMMC_DAT0 pin configuration, PIN = F20 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
- // External pull-ups are present.
- // *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+ /* External pull-ups are present. */
+ /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
/* SDMMC_DAT1 pin configuration, PIN = H14 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
- // External pull-ups are present.
- // *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+ /* External pull-ups are present. */
+ /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
/* SDMMC_DAT2 pin configuration, PIN = E19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
- // External pull-ups are present.
- // *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+ /* External pull-ups are present. */
+ /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
/* SDMMC_DAT3 pin configuration, PIN = D19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
- // External pull-ups are present.
- // *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+ /* External pull-ups are present. */
+ /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
/* SDMMC_DDIR0 pin configuration, PIN = F19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_DDIR1 pin configuration, PIN = E20 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_DDIR2 pin configuration, PIN = F18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_DDIR3 pin configuration, PIN = E18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_CDIR pin configuration, PIN = G18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* MMC_CD pin configuration, PIN = B3 ---2420IP ONLY---*/
/* MMC_CD for 2422IP=K1 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
- *MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
+ *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
/* MMC_WP pin configuration, PIN = B4 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
- *MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
+ *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
}
/******************************************
@@ -622,23 +622,23 @@
/* SPI1_CLK pin configuration, PIN = U18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SPI1_MOSI pin configuration, PIN = V20 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SPI1_MISO pin configuration, PIN = T18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SPI1_nCS0 pin configuration, PIN = U19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* PEN_IRQ pin configuration, PIN = P20 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
- *MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
+ *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
}
/****************************************
@@ -651,7 +651,7 @@
/* HDQ_SIO pin configuration, PIN = N18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
- *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
}
/***************************************************************
@@ -830,5 +830,3 @@
}
}
}
-
-
diff --git a/board/omap2420h4/platform.S b/board/omap2420h4/platform.S
index 3728e84..dc1b443 100644
--- a/board/omap2420h4/platform.S
+++ b/board/omap2420h4/platform.S
@@ -15,7 +15,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -41,109 +41,109 @@
*************************************************************************/
.global cpy_clk_code
cpy_clk_code:
- /* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* get addr of clock setting code */
- mov r2, #384 /* r2 size to copy (div by 32 bytes) */
- mov r1, r1 /* r1 <- dest address (passed in) */
- add r2, r2, r0 /* r2 <- source end address */
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
next2:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next2
- mov pc, lr /* back to caller */
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
-/* ****************************************************************************
+/* ****************************************************************************
* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- * -executed from SRAM.
+ * -executed from SRAM.
* R0 = PRCM_CLKCFG_CTRL - addr of valid reg
* R1 = CM_CLKEN_PLL - addr dpll ctlr reg
* R2 = dpll value
* R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- ******************************************************************************/
+ ******************************************************************************/
.global go_to_speed
go_to_speed:
- sub sp, sp, #0x4 /* get some stack space */
- str r4, [sp] /* save r4's value */
+ sub sp, sp, #0x4 /* get some stack space */
+ str r4, [sp] /* save r4's value */
- /* move into fast relock bypass */
- ldr r8, pll_ctl_add
- mov r4, #0x2
- str r4, [r8]
- ldr r4, pll_stat
+ /* move into fast relock bypass */
+ ldr r8, pll_ctl_add
+ mov r4, #0x2
+ str r4, [r8]
+ ldr r4, pll_stat
block:
- ldr r8, [r4] /* wait for bypass to take effect */
- and r8, r8, #0x3
- cmp r8, #0x1
- bne block
+ ldr r8, [r4] /* wait for bypass to take effect */
+ and r8, r8, #0x3
+ cmp r8, #0x1
+ bne block
/* set new dpll dividers _after_ in bypass */
- ldr r4, pll_div_add
- ldr r8, pll_div_val
- str r8, [r4]
-
- /* now prepare GPMC (flash) for new dpll speed */
+ ldr r4, pll_div_add
+ ldr r8, pll_div_val
+ str r8, [r4]
+
+ /* now prepare GPMC (flash) for new dpll speed */
/* flash needs to be stable when we jump back to it */
- ldr r4, cfg3_0_addr
- ldr r8, cfg3_0_val
- str r8, [r4]
- ldr r4, cfg4_0_addr
- ldr r8, cfg4_0_val
- str r8, [r4]
- ldr r4, cfg1_0_addr
- ldr r8, [r4]
- orr r8, r8, #0x3 /* up gpmc divider */
- str r8, [r4]
+ ldr r4, cfg3_0_addr
+ ldr r8, cfg3_0_val
+ str r8, [r4]
+ ldr r4, cfg4_0_addr
+ ldr r8, cfg4_0_val
+ str r8, [r4]
+ ldr r4, cfg1_0_addr
+ ldr r8, [r4]
+ orr r8, r8, #0x3 /* up gpmc divider */
+ str r8, [r4]
- /* setup to 2x loop though code. The first loop pre-loads the
- * icache, the 2nd commits the prcm config, and locks the dpll
- */
- mov r4, #0x1000 /* spin spin spin */
- mov r8, #0x4 /* first pass condition & set registers */
- cmp r8, #0x4
+ /* setup to 2x loop though code. The first loop pre-loads the
+ * icache, the 2nd commits the prcm config, and locks the dpll
+ */
+ mov r4, #0x1000 /* spin spin spin */
+ mov r8, #0x4 /* first pass condition & set registers */
+ cmp r8, #0x4
2:
- ldrne r8, [r3] /* DPLL lock check */
- and r8, r8, #0x7
- cmp r8, #0x2
- beq 4f
+ ldrne r8, [r3] /* DPLL lock check */
+ and r8, r8, #0x7
+ cmp r8, #0x2
+ beq 4f
3:
- subeq r8, r8, #0x1
- streq r8, [r0] /* commit dividers (2nd time) */
- nop
+ subeq r8, r8, #0x1
+ streq r8, [r0] /* commit dividers (2nd time) */
+ nop
lloop1:
- sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
- nop
- cmp r4, #0x0
- bne lloop1
- mov r4, #0x40000
- cmp r8, #0x1
- nop
- streq r2, [r1] /* lock dpll (2nd time) */
- nop
+ sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
+ nop
+ cmp r4, #0x0
+ bne lloop1
+ mov r4, #0x40000
+ cmp r8, #0x1
+ nop
+ streq r2, [r1] /* lock dpll (2nd time) */
+ nop
lloop2:
- sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
- nop
- cmp r4, #0x0
- bne lloop2
- mov r4, #0x40000
- cmp r8, #0x1
- nop
- ldreq r8, [r3] /* get lock condition for dpll */
- cmp r8, #0x4 /* first time though? */
- bne 2b
- moveq r8, #0x2 /* set to dpll check condition. */
- beq 3b /* if condition not true branch */
-4:
- ldr r4, [sp]
- add sp, sp, #0x4 /* return stack space */
- mov pc, lr /* back to caller, locked */
+ sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
+ nop
+ cmp r4, #0x0
+ bne lloop2
+ mov r4, #0x40000
+ cmp r8, #0x1
+ nop
+ ldreq r8, [r3] /* get lock condition for dpll */
+ cmp r8, #0x4 /* first time though? */
+ bne 2b
+ moveq r8, #0x2 /* set to dpll check condition. */
+ beq 3b /* if condition not true branch */
+4:
+ ldr r4, [sp]
+ add sp, sp, #0x4 /* return stack space */
+ mov pc, lr /* back to caller, locked */
_go_to_speed: .word go_to_speed
/* these constants need to be close for PIC code */
cfg3_0_addr:
.word GPMC_CONFIG3_0
-cfg3_0_val:
+cfg3_0_val:
.word H4_24XX_GPMC_CONFIG3_0
cfg4_0_addr:
.word GPMC_CONFIG4_0
@@ -156,10 +156,10 @@
pll_stat:
.word CM_IDLEST_CKGEN
pll_div_add:
- .word CM_CLKSEL1_PLL
+ .word CM_CLKSEL1_PLL
pll_div_val:
.word DPLL_VAL /* DPLL setting (300MHz default) */
-#endif
+#endif
.globl platformsetup
platformsetup:
@@ -175,23 +175,23 @@
ldr r0, REG_SDRC_SHARING
ldr r1, VAL_SDRC_SHARING
str r1, [r0]
- ldr r0, REG_SDRC_RFR_CTRL_0
+ ldr r0, REG_SDRC_RFR_CTRL_0
ldr r1, VAL_SDRC_RFR_CTRL_0
str r1, [r0]
/* little delay after init */
- mov r2, #0x1800
-1:
- subs r2, r2, #0x1
- bne 1b
+ mov r2, #0x1800
+1:
+ subs r2, r2, #0x1
+ bne 1b
#endif
#ifdef CONFIG_PARTIAL_SRAM
ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
+ str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
- mov r0, r3 /* pass skip info to s_init */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
+ mov r0, r3 /* pass skip info to s_init */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */
#endif
/* map interrupt controller */
@@ -219,7 +219,7 @@
REG_SDRC_MR_0:
.word SDRC_MR_0
REG_SDRC_RFR_CTRL_0:
- .word SDRC_RFR_CTRL
+ .word SDRC_RFR_CTRL
VAL_SDRC_SHARING:
.word VAL_H4_SDRC_SHARING
VAL_SDRC_MCFG_0:
@@ -227,11 +227,5 @@
VAL_SDRC_MR_0:
.word VAL_H4_SDRC_MR_0
VAL_SDRC_RFR_CTRL_0:
- .word VAL_H4_SDRC_RFR_CTRL_0
+ .word VAL_H4_SDRC_RFR_CTRL_0
#endif
-
-
-
-
-
-
diff --git a/board/omap2420h4/u-boot.lds b/board/omap2420h4/u-boot.lds
index 724c1dd..e9ff741 100644
--- a/board/omap2420h4/u-boot.lds
+++ b/board/omap2420h4/u-boot.lds
@@ -1,6 +1,6 @@
/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
@@ -15,7 +15,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -32,7 +32,7 @@
. = 0x00000000;
. = ALIGN(4);
- .text :
+ .text :
{
cpu/arm1136/start.o (.text)
*(.text)