commit 2e29b643a3a53a835b4ffb9d7cd5ce394dbc5c19
author Vignesh R <vigneshr@ti.com> Mon Nov 23 17:43:36 2015 +0530
committer Tom Rini <trini@konsulko.com> Wed Jan 20 10:19:33 2016 -0500
tree b684b75e28c93e0c9f74c1090ea913772c060d69
parent 8d11b8e906281c9c8e78b9f32d7645c9d78b22d3

spi: ti_qspi: Use 4-byte opcode for mmap read

ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for
memory-mapped read. This restricts maximum addressable flash size to
16MB.
Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped
read to allow access to addresses above 16MB.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
[vigneshr@ti.com: Re-word commit description]
Signed-off-by: Vignesh R <vigneshr@ti.com>

drivers/spi/ti_qspi.c

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 78d8b13..b5c974c 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -52,15 +52,15 @@
 
 #define QSPI_CMD_READ                   (0x3 << 0)
 #define QSPI_CMD_READ_DUAL		(0x6b << 0)
-#define QSPI_CMD_READ_QUAD              (0x6b << 0)
+#define QSPI_CMD_READ_QUAD              (0x6c << 0)
 #define QSPI_CMD_READ_FAST              (0x0b << 0)
-#define QSPI_SETUP0_NUM_A_BYTES         (0x2 << 8)
+#define QSPI_SETUP0_NUM_A_BYTES         (0x3 << 8)
 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
-#define QSPI_CMD_WRITE                  (0x2 << 16)
+#define QSPI_CMD_WRITE                  (0x12 << 16)
 #define QSPI_NUM_DUMMY_BITS             (0x0 << 24)
 
 /* ti qspi register set */